JPS63278366A - Solid-state image sensor - Google Patents

Abstract

PURPOSE:To inexpensively obtain a solid-stage image sensor without reducing S/N and reliability by so disposing photoelectric converters on the element chips of clock wirings of positive and negative phase sides that difference of the quotient of the length of the converters in parallel with the direction of the arrangements of the converters by the distance from the chips from the sum is 2% or less. CONSTITUTION:In clock wirings of wirings on a mounting board, photoelectric converters on element chips 101 of positive phase side clock wirings 104 of phase clock wirings are so disposed that the difference (S-(-S)/0.5(S+(-S) between S=SIGMA(ei/di) and -S=SIGMA(-ei)/(-di) is 5% or less, where ei is the length of the component parallel to the direction of the arrangement of the converters on the chip 101 of positive side clock wirings 104, -ei is the length of the component parallel to the direction of the arrangement of the converters on the chip 101 of reverse phase side clock wirings 105, and -di is the distance from the chip of the section. Thus, a solid-stage image sensor can be inexpensively manufactured without reducing S/N and reliability.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a mounting structure for a solid-state imaging device.

[Summary of the invention]

The present invention relates to a solid-state imaging device in which a plurality of element chips each having a plurality of photoelectric conversion elements and a scanning circuit for sequentially selecting each photoelectric conversion element are arranged on an insulating substrate. By wiring the clock and power supply for driving the element chips on the insulating mounting board for arranging, there are only two connection points with external circuit parts, and The present invention provides a method for manufacturing a solid-state imaging device at low cost without degrading S/N, reliability, etc. by devising the wiring arrangement.

[Conventional technology]

As shown in FIG. 2, the conventional mounting structure of the solid-state imaging device of the above type has a conductive pattern only in the vicinity of the input and output pads on each element chip arranged on the mounting board. External connections to the circuit section were made (via the conductive patterns) corresponding to the input and output sections of each element chip.

Using such a mounting structure eliminates the need for wiring patterns on the mounting board to intersect (it is useful in that it is possible to minimize wiring on the mounting board that may cause noise). be.

[Problem that the invention seeks to solve]

However, when such a mounting structure is used, the total length of the external circuit board is required to be approximately the same as that of the mounting board, and the size of the circuit board is often large compared to the amount of circuitry required. This tendency becomes more pronounced as the solid-state imaging device becomes longer.
This causes costs to rise. In addition, it is necessary to design individual external circuit boards depending on the length and number of the element chips used, and it is necessary to design multiple types of solid-state imaging devices with different lengths and numbers of the element chips used. It is difficult to respond quickly when manufacturing, and parts cannot be made available for commercial use, which also causes high costs.

In particular, when manufacturing a long solid-state imaging device, high dimensional accuracy is required for both the mounting board and the external circuit board, making it difficult to manufacture. When an ink connector is used to connect a circuit board, it becomes difficult to align and fix the mounting board and the external circuit board, and the resistance to vibration is also reduced.

Therefore, the present invention is intended to solve these problems, and its purpose is to provide a method for manufacturing a solid-state imaging device at low cost without reducing S/N, reliability, etc. It is in.

[Means to solve the problem]

The solid-state imaging device of the present invention includes (I) wiring for clocks, power supplies, etc. for driving the element chip using a conductive pattern provided on an insulating mounting substrate for raising and lowering the element chip; Therefore, the connection point with the external circuit section is set to one place, and (2) the clock wiring section of the wiring on the mounting board is connected to the clock wiring section of the positive phase side clock wiring of each phase clock wiring on the element chip. The length of the component running parallel to the direction in which the photoelectric conversion elements are arranged is 6+, and the length of the component running parallel to the direction in which the photoelectric conversion elements on the element chip of each part of the reverse phase side clock wiring is arranged is is arranged at a distance of 8 times from the element chip.

〔Example〕

FIG. 1 is a schematic diagram showing an example of the wiring between the mounting board and the external circuit portion of the element chip of the solid-state imaging device according to the embodiment of the present invention.

In FIG. 1, 101 is an element chip, 102 is an insulating mounting board, and 103 is an external circuit section. 1
04 is the positive-phase side clock wiring, 105 is the negative-phase side clock wiring, and in order to arrange the positive-phase side clock wiring so that the difference between S of the positive-phase side clock wiring and ≦ between the negative-phase side clock wiring is small, the positive-phase side clock wiring is connected at 108. The distance from the element chip is swapped by cross-underlining the wiring and the clock wiring on the opposite phase side.

The positive phase side clock wiring and the negative phase side clock wiring are approximately 1.
When examining the noise component nCL due to the influence of the clock wiring on the mounting board that appears in the output of an A4 size sensor of about 5 (V), a relationship as shown in Table 1 was found.

Table,■ In this way, the noise from the positive-phase side clock wiring and the noise from the negative-phase side clock wiring appear as voltages in opposite directions, so the smaller ΔS is, the more the canceling effect works, and the ncL
becomes smaller. In this way, in order to reduce noise from clock wiring, it is desirable that ΔS be as small as possible.
In order to obtain S/H of 30 dB or more for bright output, ΔS needs to be 5% or less.

106 and 107 are wirings for supplying power to the element chip, and wire bonding is usually used for connection between each wiring 109 and the element chip. 1) 0
is the connection part between the external circuit part and the wiring part on the mounting board, and the connection is made using an ink connector, anisotropic conductive resin, soldering, etc.

FIG. 3 shows an example of the wiring pattern on the mounting board of the solid-state @image device according to the embodiment of the present invention, in which wire bonding is used for the cross-under on the wiring pattern on the mounting board. It is.

In FIG. 3, 304 is a positive phase side clock wiring;
5 is a clock wiring on the opposite phase side, and a pattern 308 is provided to perform a cross-under to change the position seen from the element chip. Reference numerals 306 and 307 are wiring lines for power supply, and the width of the pattern is wider than that of the clock wiring lines in order to keep wiring resistance low. Furthermore, in order to reduce the power supply impedance for the element chip located away from the connection part with the circuit, a pattern for mounting a chip capacitor is provided on the external part 312. In principle, the wiring 304 to 307 should be placed as far away from the element chip as possible in order to reduce the influence of noise etc. on the element chip. shall be close to. With this arrangement, wire bonding for connecting the wiring on the mounting board and the element chip and wire bonding for cross-underning the wiring on the mounting board can be efficiently performed. If the number of device chips used is an odd number, or if the connection between the device chips and the wiring on the mounting board is asymmetrical with respect to the direction in which the photoelectric conversion elements are arranged, shadows from the clock wiring on the left and right sides may occur. In order to equalize the distance, a part of the wiring pattern is brought closer to the element chip side as shown at 313, so that the distance between the element chip and the wiring pattern becomes symmetrical, thereby reducing fixed pattern noise.

FIG. 4 shows the state of connection in the vicinity of the connection portion between the wiring on the mounting board and the element chip in the embodiment shown in FIG.

In FIG. 4, a wiring pad portion 400 on an element chip 401 is directly connected to wirings 402 to 403 on the mounting board, and 404 to 407 are wire bonding pads for cross-unders of wiring on the mounting board. 412 and are connected by wire bonding via an island-shaped intermediate wiring section 410. In this way, by arranging the wire bonding parts in a concentrated manner, it is possible to narrow the range that requires highly accurate positioning during the wire bonding process.
The equipment and time required during this process can be reduced. If it is necessary to cross-under a large number of wiring on a mounting board, use multiple island-shaped intermediate wiring parts such as 410 to shorten the length of wire bonding performed at one time. It can be done stably.

FIG. 5 is a schematic cross-sectional view of the connection portion shown in FIG. 4, which schematically shows the state of the cross-under using wire bonding of the wiring on the mounting board and the connection with the element chip. be.

In Figure 5, above the mounting board! ? 1505 is connected to the island-shaped pattern 510 by cross-under other wirings 503 and 504 on the mounting board by wire bonding 51), and is connected to the wiring pad part 508 on the element chip from 510 by wire bonding 51). connected with. Since bonding at a portion with a significant step difference like 51) tends to become unstable if it is made long, it is not recommended to connect a pattern like 510 near the element chip.

FIG. 6 shows another example of the wiring pattern on the mounting board of the solid-state imaging device according to the embodiment of the present invention.

In FIG. 6, wirings 603 to 607 on the mounting board are as follows:
Insulated from wiring on other mounting boards! , 613 and the contact portion 615 perform a cross-under. Normally, the insulating film 613 uses a metal scrap pattern formed by thick film firing as a wiring material, so an inorganic material such as glass, which is resistant to high temperatures (and can be formed by the same thick film firing), is used. If a material such as a conductive resin that can be formed even at a relatively low temperature is used as the material for the wiring pattern on the film, it is also possible to use a breeding material such as polyimide.

FIG. 7 is a schematic cross-sectional view of the connection portion shown in FIG. 6, and schematically shows how the wiring on the mounting board is cross-under using an insulating film.

In FIG. 7, wiring 705 on the mounting board is connected to an insulating film 71.
3, it cross-unders the wiring 714 on the insulating film. The wiring on the insulating film and the wiring on the mounting substrate are connected by contact portions 715. When the wiring on the mounting board is cross-undered in this way, the top of the cross-under part is flat, so a mold frame etc. for molding the element chip can be placed on top of this, and the mounting The degree of freedom in designing the wiring pattern on the board also increases.

〔Effect of the invention〕

As described above, according to the present invention, by wiring the clock and power supply for driving the element chips on the mounting board for arranging the element chips, external devices can be connected to the circuit section. The location is one, and the clock wiring on the positive phase side and the clock wiring on the negative phase side of the wiring section on the mounting board are connected to the same length as the length running parallel to the direction in which the photoelectric conversion elements on the element chip are arranged. By arranging the device so that the difference in the sum of the quotients of distances from the element chip is 2% or less, solid-state imaging devices can be manufactured at low cost without deteriorating S/N or reliability, etc. becomes larger as the solid-state imaging device becomes longer.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of wiring between the element chip, the mounting board, and the external circuit section of a solid-state imaging device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of the element chip, the mounting board, and the wiring of the external circuit section of a conventional solid-state imaging device. FIG. 3 is an example of a wiring pattern on the mounting board of the solid-state imaging device according to the embodiment of the present invention. 101.201,301...Element chip 102.20
2,302... Insulating mounting board 103.203...
・External circuit section 104.304... Positive phase side clock wiring 105.30
5... Reverse phase side clock wiring 106, 107, 308,
307...Power supply wiring 108.308...Clock wiring cross-under part 109...Connection part between element chip and wiring pattern on mounting board 1) 0.210,310...External connection to circuit part and mounting Connection part of wiring pattern on board 31)... Ground pattern for shield 312... Pad part for capacitor mounting 313... Pattern for left-right symmetry 1) 4.314... Wiring pattern on board for mounting The center line in FIG. 4 shows how the wiring on the mounting board and the connection area of the element chip are connected in the wiring pattern of the embodiment shown in FIG. 3, and in this case, FIG. FIG. FIG. 6 is a diagram showing another example of the wiring pattern on the mounting substrate of the solid-state imaging device according to the embodiment of the present invention, and FIG. 7 is a schematic cross-sectional view in this case. 401.501,601,70t...Element chip 40
2.602...Signal reading wiring 5'02,702・
...Insulating mounting board 403.503,603...Wiring pattern for power supply 405.505. f305,606・
・Clock wiring 408, 508, 608, 708...
・Connection pad portion 409.509. on the element chip. 609, 709... Shield grounding pattern 410.510... Island-shaped intermediate wiring pattern 41).
51), 61), 71)...Wire bonding for connection between element chip and wiring on mounting board 412.512...Wire bonding for cross-under of wiring on mounting board F313.713...Insulating film 714 ...Wiring pattern on the insulating film 715...Contact part between the wiring pattern on the insulating film and the wiring pattern on the mounting board Applicant: Seiko Epson Corporation oS Figure 4

Claims (2)

[Claims] (1) In a solid-state imaging device in which a plurality of photoelectric conversion elements and a plurality of element chips 101 each having a scanning circuit for sequentially selecting each photoelectric conversion element are arranged on an insulating substrate, the element chips Insulating mounting board 1 for arranging
Wirings 104 to 10 for clocks, power supplies, etc. for driving the element chips by conductive patterns provided on 02
A solid-state imaging device characterized in that by performing step 7, the number of connection points with an external circuit section 103 is reduced to one. (2) In the clock wiring part of the wiring on the mounting board, the length of the component of each part of the positive phase side clock wiring of each phase clock wiring running parallel to the direction in which the photoelectric conversion elements on the element chip are arranged. e_1, the distance of that part from the element chip is d_1, and the length of the component running parallel to the direction in which the photoelectric conversion elements on the element chip of each part of the reverse phase side clock wiring are arranged is @e@_1, Let the distance of that part from the element chip be @d@_1, and there are ▲mathematical formulas, chemical formulas, tables, etc.▼ and @S@=Σ(@e@_1)/(@d@_
Difference from 1) (S-@S@)/{1/2(S+@S@)
} 5% or less, the solid-state imaging device according to claim 1.