JPS6335014A - Output circuit - Google Patents

Output circuit

Info

Publication number
JPS6335014A
JPS6335014A JP61180545A JP18054586A JPS6335014A JP S6335014 A JPS6335014 A JP S6335014A JP 61180545 A JP61180545 A JP 61180545A JP 18054586 A JP18054586 A JP 18054586A JP S6335014 A JPS6335014 A JP S6335014A
Authority
JP
Japan
Prior art keywords
power supply
output buffers
output
mask pattern
shape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61180545A
Other languages
Japanese (ja)
Inventor
Hiromasa Tanabe
田辺　皓正
Hiroshi Hikichi
博 引地
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC Corp
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC IC Microcomputer Systems Co Ltd filed Critical NEC Corp
Priority to JP61180545A priority Critical patent/JPS6335014A/en
Publication of JPS6335014A publication Critical patent/JPS6335014A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microcomputers (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To allow a required voltage level to cope with increase/decrease in number of output buffers flexibly by selecting supply or interruption of power supply to/from the output buffers depending on the shape of a mask pattern in the wiring process in the stage of manufacture of a microcomputer. CONSTITUTION:In selecting a switch S3 to be opened and other switches S1, S2, S4-Sn+1 to be conducted, a power supply fed to output buffers B1, B2 is given from a 1st power terminal V1 and the power supply fed to the output buffers B3-Bn is fed from a 2nd power terminal V2 by the mask pattern shape in the wiring stage. Only one among the switches S1-Sn+1 is unconducted by the shape of mask pattern. Thus, the number of output buffers connected to the power terminal V1 is selected optionally from zero to n-set.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積された論理回路に関し、特にマイクロコン
ピュータの出力回路における電源供給方式の改良に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated logic circuit, and more particularly to an improvement in a power supply system in an output circuit of a microcomputer.

〔従来の技術〕[Conventional technology]

従来、集積化されたマイクロコンビエータ（以下、マイ
コンという）の出力バッファーにはプツシ−プル型、オ
ープンドレイン型、負荷抵抗内戚型など各種の形式があ
る。なかでも負荷抵抗内蔵形式の場合には、出力信号の
電圧振幅を通常の１源電圧ｖＤＤとは異なった値に設定
するためにＶＤＤとは別の電源を設けるのが一般的であ
る。Conventionally, there are various types of output buffers for integrated microcombinators (hereinafter referred to as microcomputers), such as push-pull type, open drain type, and load resistor type. In particular, in the case of a built-in load resistor type, it is common to provide a power source separate from VDD in order to set the voltage amplitude of the output signal to a value different from the normal single-source voltage vDD.

第３図は負荷抵抗を内蔵した出力バッファーがｎ個集積
化された場合の回路図で、Ｂｌ〜Ｂｔ１は各々負荷抵抗
Ｒ１〜Ｒａを内蔵した出力バッファ−１ｖＩは各出力バ
ッファーＢ１−Ｂｒ１に共通に電圧を供給するだめの電
源端子である。第３図における構成では各出力バッファ
ーの信号波形はＶ、とＧＮＤＯ間の振幅となる。出力信
号が通常の電圧レベルでよい場合にはｖ８としてＶＤＤ
を使用している場合もある。しかしながらいずれにして
も全ての出力バッファーの電源はＶ＋（またはＶＤＤ）
に固定されていた。Figure 3 is a circuit diagram when n output buffers with built-in load resistors are integrated, where Bl to Bt1 are output buffers with built-in load resistors R1 to Ra, and 1vI is common to each output buffer B1 to Br1. This is the power supply terminal that supplies voltage to the terminal. In the configuration shown in FIG. 3, the signal waveform of each output buffer has an amplitude between V and GNDO. If the output signal is at a normal voltage level, set it to VDD as v8.
Sometimes it is used. However, in any case, the power supply for all output buffers is V+ (or VDD)
was fixed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

マイコンの応用を考えた場合、必要な出力の端子数はユ
ーザ毎に異なるのが通例である。上述した従来の電源供
給形式ではｖｌが接続される出力バッ７アー数はたとえ
ばｎ個に固定されておシ、ユーザが必要とする出力バッ
ファー数が増減した場合に柔軟に対処することは困難で
ある。また未使用の出力端子が生ずる場合には、端子の
有効利用の点からも不経済であるという欠点を有してい
た。When considering the application of microcomputers, the number of required output terminals usually differs depending on the user. In the conventional power supply format described above, the number of output buffers to which VL is connected is fixed to n, for example, and it is difficult to deal flexibly with increases or decreases in the number of output buffers required by the user. be. Furthermore, if there are unused output terminals, this method has the disadvantage of being uneconomical in terms of effective use of the terminals.

〔問題点を解決するための手段〕[Means for solving problems]

本発明はマイコンに内蔵された出力バッファーに接続す
る電源ラインを選択可能にし、応用に柔軟に対応できる
出力回路を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide an output circuit which allows selection of a power supply line connected to an output buffer built into a microcomputer and which can be flexibly adapted to various applications.

上記目的を達成するため、本発明の出力回路はＭＯＳＩ
Ｉトランジスタと負荷抵抗で構成される出力バッファー
と、複数の電源ラインを有するマイクロコンビエータに
おいて、前記出力バッファーと前記複数の電源ラインの
いずれかとの接続を、該マイクロコンピュータの製造工
程におけるマスクパターンの形状で選択して前記出力パ
ツフア−に電源を供給することを特徴とする。In order to achieve the above object, the output circuit of the present invention is a MOSI
In a microcombinator having an output buffer composed of an I transistor and a load resistor, and a plurality of power supply lines, the connection between the output buffer and any one of the plurality of power supply lines is determined by a mask pattern in the manufacturing process of the microcomputer. It is characterized in that power is supplied to the output puffer by selecting the shape.

〔実施例〕〔Example〕

第１図は本発明の一実施例を示す回路図で、ｎ個の出力
バッファーが集積化された例である。第１図においてＢ
！−Ｂｎは各々ＭＯＳ）ランジスタと負荷抵抗で構成さ
れる出力バッファー、■、は第１の＠源端子、■、は第
２の電源端子％Ｆ１〜Ｆ　ｎ　＋　１は各々配線工程（
たとえばアルミ配線工程）のマスクパターンで接続また
は非接続の選択が可能なスイッチである。仮に、配線工
程のマスクパターン形状にてパー１ツチＳ、を非接続、
その他のスイッチ（３１−Ｓｔ　、　８４−８ｎ＋ｔ）
を接続に選択した場合、出力バッファーＢ、およびＢ、
に供給される電源は第１の電源端子ｖ１から、出力バッ
ファーＢ１〜Ｂ、に供給される電源は第２の′ｗｉ源端
子Ｖ、から導かれる。従って、マスクパターンの形状に
てスイッチＳ、〜Ｓｎ＋ｘ　　のどれか１つのみを非接
続にすることによ１電源端子ｖ１に接続される出力バッ
７アーの数が０からｎ個まで任意に選択できる。第１図
において電源端子ｖ１またはＶ。FIG. 1 is a circuit diagram showing one embodiment of the present invention, and is an example in which n output buffers are integrated. In Figure 1, B
! -Bn is an output buffer composed of a MOS) transistor and a load resistor, ■ is the first @ source terminal, ■ is the second power supply terminal %F1 to F n + 1 are the wiring process (
For example, it is a switch that can be connected or disconnected using a mask pattern (for example, in an aluminum wiring process). If part 1, S, is not connected due to the mask pattern shape of the wiring process,
Other switches (31-St, 84-8n+t)
If you select to connect output buffers B and B,
The power supplied to the output buffers B1 to B is led from the first power supply terminal v1, and the power supplied to the output buffers B1 to B is led from the second 'wi source terminal V. Therefore, by disconnecting only one of the switches S and ~Sn+x according to the shape of the mask pattern, the number of output buffers connected to one power supply terminal v1 can be arbitrarily selected from 0 to n. can. In FIG. 1, the power supply terminal v1 or V.

のどちらかがマイコンの通常の電源電圧（ＶＤＤ）の場
合もあシ得る。It is also possible if either of these is the normal power supply voltage (VDD) of the microcomputer.

第２図は本発明の第二の実施例を示す回路図である。第
２図においてＢ、〜Ｂｆｉは第１図と同様の出力バッフ
ァー、ｖｌは第１の電源端子１ｖ、は第２の電源端子、
Ｔ１〜Ｔ、　　は各々配線工程のマスクパターンにて電
源端子ｖ１またはＶ、がらの電源２インのどちらかに接
続する選択可能なスイッチである。第２図の如き選択方
法によシ各出力バッ７アー毎に供給電源の選択が自由に
でき、第１図の実施例よシもさらに柔軟性に富んだもの
になる。FIG. 2 is a circuit diagram showing a second embodiment of the present invention. In FIG. 2, B, ~Bfi are the same output buffers as in FIG. 1, vl is the first power supply terminal 1v,
T1 to T are selectable switches connected to either the power supply terminal V1 or V, or the power supply 2-in, respectively, using the mask pattern of the wiring process. The selection method shown in FIG. 2 allows the power supply to be freely selected for each output buffer 7, making the embodiment of FIG. 1 even more flexible.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本実施例によれば、集積化されたマ
イコンにおいて負荷抵抗を内蔵した出力バッ７アーへの
電源の供給を、マイコンの製造段階の配線工程における
マスクパターンの形状により接続または非接続を選択す
ることで、必要とする電圧レベルの出力バッファー数の
増減に対して柔軟に対処でき、出力端子の有効利用の観
点からもその効果は大である。As explained above, according to this embodiment, the power supply to the output buffer 7 with a built-in load resistor in an integrated microcontroller is connected or disconnected depending on the shape of the mask pattern in the wiring process during the manufacturing stage of the microcontroller. By selecting the connections, it is possible to flexibly deal with increases and decreases in the number of output buffers for the required voltage level, which is also very effective in terms of effective use of output terminals.

同、本実施例では電圧源として２種類の場合についての
み言及したが、特にそれに限定されるものではない。Similarly, in this embodiment, only two types of voltage sources are mentioned, but the present invention is not limited thereto.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の出力回路の第１の実施例を示す回路図
、第２図は本発明の第２の実施例を示す回路図、第３図
は従来の出力回路の回路図である。 ｖｌ・・・・・・第１の電源端子、■、・・・・・・第
２の電源端子、Ｂ　１　”　Ｂｎ　”−””出力バッフ
７−ｓ　８１　”　５ｎｏ１・・・・・・マスク・オプ
シ冒ンによるスイッチ、Ｔ、〜Ｔ。 ・・・・・・マスクΦオプシ１ンによるスイッチ、Ｒ１
−Ｒａ・・・・・・内戚負荷抵抗。 佑　１図 ｔ５ガ　　　　Ｂｆｌ−／　　　　　　　　りｔ　　　
　がｌ第　３　図　θを釆イ列）Fig. 1 is a circuit diagram showing a first embodiment of the output circuit of the present invention, Fig. 2 is a circuit diagram showing a second embodiment of the invention, and Fig. 3 is a circuit diagram of a conventional output circuit. . vl...First power supply terminal, ■,...Second power supply terminal, B1"Bn"-""Output buffer 7-s81"5no1...Mask・Switch by optical switch, T, ~T. ...Switch by mask Φ option, R1
-Ra...Internal load resistance. Yu 1 figure t5ga Bfl-/rit
(Fig. 3)

Claims (1)

【特許請求の範囲】[Claims] 複数の電源ラインを有する集積化されたマイクロコンピ
ュータに用いられ、ＭＯＳ型トランジスタと負荷抵抗と
を含む出力バッファーを有する出力回路において、前記
出力バッファーと前記複数の電源ラインのいずれかとを
前記マイクロコンピュータの製造工程におけるマスクパ
ターンの形状により選択して接続し、前記出力バッファ
ーに電源を供給することを特徴とする出力回路。In an output circuit that is used in an integrated microcomputer having a plurality of power supply lines and has an output buffer including a MOS transistor and a load resistor, the output buffer and one of the plurality of power supply lines are connected to the microcomputer. An output circuit characterized in that the output circuit is selected and connected according to the shape of a mask pattern in a manufacturing process, and supplies power to the output buffer.
JP61180545A 1986-07-30 1986-07-30 Output circuit Pending JPS6335014A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61180545A JPS6335014A (en) 1986-07-30 1986-07-30 Output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61180545A JPS6335014A (en) 1986-07-30 1986-07-30 Output circuit

Publications (1)

Publication Number Publication Date
JPS6335014A true JPS6335014A (en) 1988-02-15

Family

ID=16085150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61180545A Pending JPS6335014A (en) 1986-07-30 1986-07-30 Output circuit

Country Status (1)

Country Link
JP (1) JPS6335014A (en)

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