JPS6216693Y2 - - Google Patents
Info
- Publication number
- JPS6216693Y2 JPS6216693Y2 JP14126481U JP14126481U JPS6216693Y2 JP S6216693 Y2 JPS6216693 Y2 JP S6216693Y2 JP 14126481 U JP14126481 U JP 14126481U JP 14126481 U JP14126481 U JP 14126481U JP S6216693 Y2 JPS6216693 Y2 JP S6216693Y2
- Authority
- JP
- Japan
- Prior art keywords
- logic
- circuit
- terminal
- connector
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000011156 evaluation Methods 0.000 claims description 22
- 238000007689 inspection Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000012937 correction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
【考案の詳細な説明】 本考案は評価補助パツケージに関する。[Detailed explanation of the idea] The present invention relates to an evaluation aid package.
一般に、コンピユータなどの大規模な論理回路
を含む装置においては、設計の段階における論理
の誤りや、製作の段階で生じた接続の誤りなどは
或る程度は避けられないものである。検査および
評価の段階で上記の誤りが或る部分で発見された
場合には、その部分が正常に動作することが条件
となる他の部分の検査および評価を続行すること
ができない。従つて従来は誤りが発見された部分
については部分的な修正を行なつてから検査およ
び評価を続けているが、これは非常に能率が悪
く、特に近年の論理パツケージのように実装密度
の高い基板の改造や、小形のコネクタに多数の電
線が接続されている部分の接続変更などには非常
に長時間を要しそのために検査および評価に長い
期間を要するという欠点がある。 In general, in devices including large-scale logic circuits such as computers, errors in logic at the design stage and connection errors at the manufacturing stage are unavoidable to some extent. If the above-mentioned error is found in a certain part during the inspection and evaluation stage, it is not possible to continue the inspection and evaluation of other parts, which requires that part to operate normally. Therefore, in the past, inspections and evaluations were continued after making partial corrections for parts where errors were discovered, but this was extremely inefficient, especially for logic packages with high packaging density such as recent logic packages. There is a drawback that it takes a very long time to modify the board or change the connection of a part where a large number of electric wires are connected to a small connector, and therefore a long period of time is required for inspection and evaluation.
本考案の目的は従来の欠点を除き検査および評
価の段階で発見された誤りをその場において短時
間で一時的に修正し次の段階の検査および評価を
支障なく続行することによつて検査および評価に
必要な期間を短縮させ得る評価補助パツケージを
提供することにある。 The purpose of this invention is to eliminate the defects found in the conventional inspection and evaluation stage, temporarily correct errors found during the inspection and evaluation stage on the spot in a short time, and continue the next stage of inspection and evaluation without any problems. The object of the present invention is to provide an evaluation support package that can shorten the period required for evaluation.
本考案のパツケージは論理パツケージを含む装
置の本体側に設けられたバツクボードに接続可能
なフロント側コネクタと、基板と、前記論理パツ
ケージに接続可能なリア側コネクタとを含んで前
記バツクボードと前記論理パツケージとの間に挿
入可能な構造を有し、論理“1”又は“0”のい
ずれか一方を選択し出力する切換え回路と、第1
の入力端子を前記フロント側コネクタの論理入力
端子に接続し第2の入力端子を前記切換え回路の
出力に接続し出力端子を前記リア側コネクタに接
続した排他的論理和回路とからなる少くとも1組
の入力論理反転手段と、複数個の端子からなるフ
ロント側端子群と前記フロント側端子群と同数の
端子からなるリア側端子群との間をジヤンパ線に
よつて任意の組合せで接続するジヤンパ接続回路
を前記基板上に設けて前記排他的論理和回路の出
力端子と前記リア側コネクタの間若しくは前記フ
ロント側コネクタと前記排他的論理和回路の第1
の入力端子との間に接続した入力論理交換手段と
を含んでいる。 The package of the present invention includes a front side connector connectable to a backboard provided on the main body side of a device including a logic package, a board, and a rear side connector connectable to the logic package. a switching circuit having a structure that can be inserted between the first and second switching circuits and selecting and outputting either logic "1" or "0";
an exclusive OR circuit, the input terminal of which is connected to the logic input terminal of the front connector, the second input terminal of which is connected to the output of the switching circuit, and the output terminal of which is connected to the rear connector. A jumper that connects a set of input logic inverting means, a front side terminal group consisting of a plurality of terminals, and a rear side terminal group consisting of the same number of terminals as the front side terminal group in any combination by jumper wires. A connection circuit is provided on the board, and a connection circuit is provided between the output terminal of the exclusive OR circuit and the rear connector, or between the front connector and the first of the exclusive OR circuit.
and input logic switching means connected between the input terminals of the input terminal.
次に本考案を図面を用いて詳細に説明する。 Next, the present invention will be explained in detail using the drawings.
第1図は本考案の一実施例の回路図である。こ
の例の評価補助パツケージは、m(mは正の整
数)個の論理入力に対応するm個の論理入力端子
1−1〜1−i〜1−mを含むフロント側コネク
タ1と、m個の論理出力端子3−1〜3−i〜3
−mを含むリア側コネクタ3と、m個の排他的論
理和回路(以下EX−OR回路と称する)4−1〜
4−i〜4−mと、m個の切換スイツチで構成さ
れたm個の切換回路5−1〜5−i〜5−mと、
m個のフロント側端子6−1a〜6−ia〜6−ma
及びm個のリア側端子6−1b〜6−ib〜6mbか
ら成るフロント側端子群及びリア側端子群を含む
ジヤンパ接続回路6と、インバータ7と論理
“1”の入力端子8とから構成され、論理入力端
子1−1〜1−i〜1−mはEX−OR回路4−1
〜4−i〜4−mの第1の入力端子に接続され、
EX−OR回路4−1〜4−i〜4−mの第2の入
力端子は切換回路5−1〜5−i〜5−mに結線
されて、論理“1”の入力端子から入力される
“1”若しくはインバータ7の出力“0”のいず
れかを選択するように切換回路5−1〜5−i〜
5−mに接続され、EX−OR回路4−1〜4−i
〜4−mの出力はフロント側端子6−1a〜6−ia
〜6−maに接続されており、リア側端子6−1b
〜6−ib〜6−mbはリア側コネクタ3に含まれ
る論理出力端子3−1〜3−i〜3−mに接続さ
れている。 FIG. 1 is a circuit diagram of an embodiment of the present invention. The evaluation support package in this example includes a front connector 1 including m logic input terminals 1-1 to 1-i to 1-m corresponding to m logic inputs (m is a positive integer), and m logic input terminals 1-1 to 1-i to 1-m. Logic output terminals 3-1 to 3-i to 3
-m rear side connector 3 and m exclusive OR circuits (hereinafter referred to as EX-OR circuits) 4-1 to
4-i to 4-m, m switching circuits 5-1 to 5-i to 5-m each composed of m switching switches,
m front side terminals 6-1a ~ 6-ia ~ 6-ma
and a jumper connection circuit 6 including a front side terminal group and a rear side terminal group consisting of m rear side terminals 6-1b to 6-ib to 6mb, an inverter 7, and an input terminal 8 of logic "1". , logic input terminals 1-1 to 1-i to 1-m are EX-OR circuit 4-1
~4-i ~ connected to the first input terminal of 4-m,
The second input terminals of the EX-OR circuits 4-1 to 4-i to 4-m are connected to the switching circuits 5-1 to 5-i to 5-m, and input from the logic "1" input terminal. switching circuits 5-1 to 5-i to select either “1” output from the inverter 7 or “0” output from the inverter 7
Connected to 5-m, EX-OR circuit 4-1 to 4-i
~4-m output is from front side terminal 6-1a ~ 6-ia
~ Connected to 6-ma, rear terminal 6-1b
6-ib to 6-mb are connected to logic output terminals 3-1 to 3-i to 3-m included in the rear connector 3.
次に本実施例の動作について説明する。 Next, the operation of this embodiment will be explained.
先ず、論理又は入力論理間の接続の誤りが発見
されていない状態では第1図に示しているように
切換回路5−1〜5−i〜5−mはすべて“0”
側に接続されEX−OR回路4−1〜4−i〜4−
mの入力の第2の入力端子に“0”なる論理を入
力しているので論理入力端子1−1〜1−i〜1
−mに与えられた論理“1”又は“0”はそのま
まEX−OR回路4−1〜4−i〜4−mの出力と
なり、ジヤンパ接続回路6においてはフロント側
端子6−1a〜6−ia〜6−maとリア側端子6−
1b〜6−ib〜6−mbはそれぞれ対応する端子の
間が第1図に示しているようにジヤンパ線6−1c
〜6−ic〜6−mcによつて接続されているので
EX−OR回路4−1〜4−i〜4−mの出力はそ
のまま論理出力端子3−1〜3−i〜3−mの出
力となる。したがつて論理出力端子3−1〜3−
i〜3−mには論理入力端子1−1〜1−i〜1
−mに入力された論理と等しい論理が出力される
ことになり、この評価補助パツケージを前記バツ
クボードと前記論理パツケージとの間に挿入して
も前記論理パツケージに出力される論理には全く
変化を与えない。 First, in a state where no error in logic or connection between input logics is found, all switching circuits 5-1 to 5-i to 5-m are set to "0" as shown in FIG.
EX-OR circuit connected to the side 4-1 ~ 4-i ~ 4-
Since the logic “0” is input to the second input terminal of the input of m, the logic input terminals 1-1 to 1-i to 1
The logic "1" or "0" given to -m becomes the output of the EX-OR circuits 4-1 to 4-i to 4-m as is, and in the jumper connection circuit 6, the front side terminals 6-1a to 6- ia~6-ma and rear side terminal 6-
1b to 6-ib to 6-mb have jumper wires 6-1c between the corresponding terminals as shown in Figure 1.
Since they are connected by ~6-ic ~6-mc
The outputs of the EX-OR circuits 4-1 to 4-i to 4-m directly become the outputs of the logic output terminals 3-1 to 3-i to 3-m. Therefore, the logic output terminals 3-1 to 3-
i to 3-m have logic input terminals 1-1 to 1-i to 1
A logic equal to the logic input to -m will be output, and even if this evaluation auxiliary package is inserted between the backboard and the logic package, there will be no change in the logic output to the logic package. I won't give it.
次に論理“1”又は“0”の誤りが論理入力端
子1−iにおいて発見された場合には、切換回路
5−iを論理“1”側に切り換えることにより
EX−OR回路4−iは周知の動作原理によりイン
バータとして動作し論理入力端子1−iに入力さ
れた論理“1”または“0”を反転した論理
“0”または“1”が出力され、その出力はフロ
ント側端子6−ia、ジヤンパ線6−ic、リア側端
子6−ibを通して論理出力端子3−iに与えられ
る。したがつて入力端子1−iにおける論理の誤
りは一時的に修正された状態となり、次の段階の
検査および評価を続行することが可能となる。 Next, when a logic "1" or "0" error is found at the logic input terminal 1-i, the switching circuit 5-i is switched to the logic "1" side.
The EX-OR circuit 4-i operates as an inverter according to a well-known operating principle, and outputs a logic "0" or "1" which is the inversion of the logic "1" or "0" input to the logic input terminal 1-i. The output is given to the logic output terminal 3-i through the front terminal 6-ia, the jumper wire 6-ic, and the rear terminal 6-ib. Therefore, the logic error at the input terminal 1-i is temporarily corrected, and it becomes possible to continue the next stage of inspection and evaluation.
次に入力論理間の接続についての誤りによる入
力論理の入れ違いが論理入力端子1−1と1−i
との間で発見された場合には、ジヤンパ接続回路
6においてフロント側端子6−1aとリア側端子6
−1bおよびフロント側端子6−iaとリア側端子6
−ibとを接続しているジヤンパ線6−1cと6−ic
とを取外し、その代りにフロント側端子6−1aと
リア側端子6−ib及びフロント側端子6−iaとリ
ア側端子6−1bとをジヤンパ線で接続すること
により入力論理間の接続の誤りは一時的に修正さ
れた状態となり、次の段階の検査、評価を続行す
ることが可能となる。第2図は第1図に示す一実
施例の回路を基板上に搭載した状態を示す平面図
である。 Next, the input logic may be swapped due to an error in the connection between the input logics, and the logic input terminals 1-1 and 1-i
If it is found between the front terminal 6-1a and the rear terminal 6 in the jumper connection circuit 6.
-1b and front terminal 6-ia and rear terminal 6
Jumper wires 6-1c and 6-ic connecting -ib
, and instead connect the front side terminal 6-1a and the rear side terminal 6-ib and the front side terminal 6-ia and the rear side terminal 6-1b with jumper wires to correct the connection error between the input logics. will be in a temporarily corrected state, allowing the next stage of inspection and evaluation to continue. FIG. 2 is a plan view showing the circuit of the embodiment shown in FIG. 1 mounted on a board.
この評価補助パツケージは論理パツケージを含
む装置の本体側に設けられたバツクボードに接続
可能なフロント側コネクタ1と、基板2と、前記
論理パツケージに接続可能なフロント側コネクタ
3とを含んで構成され前記バツクボードと前記論
理パツケージとの間に挿入可能な構造を有してい
る。 This evaluation auxiliary package includes a front connector 1 connectable to a backboard provided on the main body side of the device including the logic package, a board 2, and a front connector 3 connectable to the logic package. It has a structure that can be inserted between the backboard and the logic package.
以上本考案の一実施例としてジヤンパ接続回路
をEX−OR回路と論理出力端子との間に設けた場
合について述べたが、ジヤンパ接続回路を論理入
力端子とEX−OR回路との間に設けた場合にも本
考案の評価補助パツケージの機能が全く等しいこ
とは明らかであり、更に細部の変形については第
1図に示した切換回路を構成する切換スイツチの
代りに接続変更用のピンを設けジヤンパ線によつ
て接続換えを行つて実装密度を上げることも可能
であり、又第1図に示した論理“0”を得るため
のインバータを使用せずに論理“0”の入力端子
を設けて外部の回路から論理“0”を得るように
構成しても良い。 The case where the jumper connection circuit is provided between the EX-OR circuit and the logic output terminal has been described as an embodiment of the present invention, but it is also possible to provide the jumper connection circuit between the logic input terminal and the EX-OR circuit. It is clear that the functions of the evaluation support package of the present invention are exactly the same in both cases, and further details can be modified by providing a jumper with a pin for changing the connection in place of the changeover switch composing the changeover circuit shown in Figure 1. It is also possible to increase the packaging density by changing connections using wires, and by providing an input terminal for logic "0" without using an inverter to obtain logic "0" as shown in Figure 1. The configuration may be such that logic "0" is obtained from an external circuit.
以上に詳細に説明したように本考案の評価補助
パツケージはコンピユータなどの大規模な論理回
路を含む装置の検査、評価の段階で発見された部
分的な論理の誤りや論理入力間の接続の誤りを簡
単な方法で一時的に修正し、次に続く検査、評価
を続行することにより検査、評価に必要な期間を
短縮させ得るという効果がある。 As explained in detail above, the evaluation support package of the present invention is used to test and evaluate devices including large-scale logic circuits such as computers, and to detect partial logic errors and connection errors between logic inputs that are discovered during the evaluation stage. This has the effect of shortening the period required for inspection and evaluation by temporarily correcting the problem using a simple method and continuing with the subsequent inspection and evaluation.
第1図は本考案の一実施例の回路図および第2
図は第1図に示す一実施例の回路を基板上に搭載
した状態を示す平面図である。
図において、1……フロント側コネクタ、1−
1〜1−i〜1−m……論理入力端子、2……基
板、3……リア側コネクタ、3−1〜3−i〜3
−m……論理出力端子、4−1〜4−i〜4−m
……EX−OR回路、5−1〜5−i〜5−m……
切換回路、6……ジヤンパ接続回路、6−1a〜6
−ia〜6−ma……フロント側端子、6−1b〜6
−ib〜6−mb……リア側端子、6−1c〜6−ic
〜6−mc……ジヤンパ線、7……インバータ、
8……論理“1”の入力端子。
Figure 1 is a circuit diagram of one embodiment of the present invention and a circuit diagram of an embodiment of the invention.
This figure is a plan view showing a state in which the circuit according to the embodiment shown in FIG. 1 is mounted on a substrate. In the figure, 1...Front side connector, 1-
1~1-i~1-m...logic input terminal, 2...board, 3...rear side connector, 3-1~3-i~3
-m...Logic output terminal, 4-1 to 4-i to 4-m
...EX-OR circuit, 5-1~5-i~5-m...
Switching circuit, 6...Jumper connection circuit, 6-1a~6
-ia~6-ma...Front side terminal, 6-1b~6
-ib ~ 6-mb...Rear side terminal, 6-1c ~ 6-ic
~6-mc... jumper wire, 7... inverter,
8...Logic "1" input terminal.
Claims (1)
れたバツクボードに接続可能なフロント側コネ
クタと、前記論理パツケージに接続可能なリア
側コネクタと、論理“1”または“0”のいず
れか一方を選択し出力する切換え回路と第1の
入力端子が前記フロント側コネクタの論理入力
端子のうちの1つに接続され第2の入力端子が
前記切換え回路の出力に接続され出力端子が前
記リア側コネクタの出力端子のうちの1つに接
続された排他的論理和回路とからなる少くとも
1組の入力論理反転手段を有する基板とを備
え、前記バツクボードと前記論理パツケージと
の間に挿入可能な構造を有することを特徴とす
る評価補助パツケージ。 (2) 前記フロント側コネクタの複数の論理入力端
子と前記排他的論理和回路の第1の入力端子と
の間または前記排他的論理和回路の出力端子と
前記リア側コネクタの複数の出力端子との間を
接続変更可能なジヤンパ線を介して接続したこ
とを特徴とする実用新案登録請求の範囲第(1)項
記載の評価補助パツケージ。[Claims for Utility Model Registration] (1) A front side connector that can be connected to a back board provided on the main body side of the device including a logic package, a rear side connector that can be connected to the logic package, and a logic “1” or A switching circuit that selects and outputs either "0" and a first input terminal are connected to one of the logic input terminals of the front connector, and a second input terminal is connected to the output of the switching circuit. and an exclusive OR circuit whose output terminal is connected to one of the output terminals of the rear connector. An evaluation aid package characterized by having a structure that can be inserted between. (2) between the plurality of logic input terminals of the front connector and the first input terminal of the exclusive OR circuit, or between the output terminal of the exclusive OR circuit and the plurality of output terminals of the rear connector; The evaluation assistance package according to claim (1) of the utility model registration, characterized in that the two are connected via jumper wires that can be changed in connection.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14126481U JPS5846178U (en) | 1981-09-22 | 1981-09-22 | Evaluation support package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14126481U JPS5846178U (en) | 1981-09-22 | 1981-09-22 | Evaluation support package |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5846178U JPS5846178U (en) | 1983-03-28 |
JPS6216693Y2 true JPS6216693Y2 (en) | 1987-04-27 |
Family
ID=29934376
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14126481U Granted JPS5846178U (en) | 1981-09-22 | 1981-09-22 | Evaluation support package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5846178U (en) |
-
1981
- 1981-09-22 JP JP14126481U patent/JPS5846178U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5846178U (en) | 1983-03-28 |
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