JP2661364B2 - Test circuit method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit system for a large-scale ASIC or the like, and more particularly, to a test circuit system capable of improving the evaluation efficiency of a chip constituting a test circuit. It is related to.

2. Description of the Related Art An outline of a conventional test circuit of this type is shown in FIGS.
FIG. 5 and FIG.

Here, FIG. 3 is a schematic block diagram showing the configuration of a conventional test circuit and the arrangement of peripheral circuit sections. FIGS. 4 and 5 are output test circuit sections and input test circuit sections of the same test circuit. It is a circuit connection diagram which shows each detailed structure respectively.

In each of these conventional examples, reference numeral 21 denotes an output test circuit unit constituting one of the test circuits, reference numeral 22 denotes an internal circuit output signal from the internal circuit which is input to the output test circuit unit 21, and reference numeral 23 denotes Reference numeral 24 denotes an output test mode signal to the output test circuit unit 21, and reference numeral 24 denotes a terminal output signal from the output test circuit unit 21, which is an input / output terminal 31 through the I / O pad 30.
Is output to

Reference numeral 27 denotes an input test circuit unit constituting the other side of the test circuit; 25, a terminal input signal input to the input test circuit unit 27 from the input / output terminal 31 via the I / O pad 30; Is the input test circuit section from the internal circuit side.
A return input signal input to 27, and 28 indicates an input test mode signal to the input test circuit unit 27,
Denotes an internal circuit input signal from the input test circuit unit 27 to the internal circuit side.

Next, the operation of the conventional circuit having the above configuration will be described.

First, as shown in FIG. 3, the internal circuit output signal 22 from the internal circuit side is input to the output test circuit section 21 and is switched by the output test mode signal 23 in the output test circuit section 21. The terminal output signal 24 is input to the input / output terminal 31 via the I / O pad 30.
Is output to Further, a signal input from the input / output terminal 31 is converted into a terminal input signal 25 via the I / O pad 30, and the terminal input signal 25
These signals and the fixed level signal of “L” or “H” are switched by the input test mode signal 28 in the input test circuit unit 27. As the internal circuit input signal 29, the internal circuit input signal 29 is input to the internal circuit.

That is, in the case of the conventional test circuit, the output to the input / output terminal side, the input from the input / output terminal side, and the return to the internal circuit side separated from the signal path on the input / output terminal side are thus performed. Has three functions.

SUMMARY OF THE INVENTION However, in the case of a conventional test circuit having the above configuration, since each circuit is completely separated into an output test circuit section and an input test circuit section, each of such test circuits is not required. All input / output terminals having circuit parts have two signal lines, a terminal output signal line and a terminal input signal line. As a result, the wiring area in the chip is increased, There is an undesired problem that the evaluation efficiency of the chip is reduced.

The present invention is intended to solve such a conventional problem. For the internal circuit signal, as in the conventional case, the output to the input / output terminal side, the input from the input / output terminal side,
This type of test circuit is designed to provide three functions for each return to the internal circuit side separated from the signal path on the input / output terminal side and to reduce the number of wires to the input / output terminal side. The purpose is to provide.

Means for Solving the Problems In order to achieve the above object, the present invention provides an input / output of an internal circuit input / output signal on an internal circuit side, and an input / output test mode signal, An input / output test circuit unit provided with signal path switching means, an I / O pad for performing input / output control by a control signal synchronized with an input / output test mode signal, and
An input / output terminal for inputting / outputting a terminal input / output signal via an / O pad, wherein the input / output test circuit switches the path switching means according to an input / output test mode signal and outputs the signal to the input / output terminal. A test circuit system that performs three functions of input from the input / output terminal side and folding back to the internal circuit side separated from the input / output terminal side, and has a single wiring to the input / output terminal side. .

Operation Therefore, according to the present invention, the following operation is obtained by configuring as described above.

That is, the input test circuit and the output test circuit are integrated into an input / output test circuit section, and input / output control of the I / O pad is performed by input / output test mode signals to the input / output test circuit section. Since each function is provided, the wiring on the input / output terminal side can be unified.

Embodiment Hereinafter, an embodiment of a test circuit according to the present invention will be described in detail with reference to FIG. 1 and FIG.

Here, FIG. 1 is a schematic block diagram showing a configuration of a test circuit to which the present embodiment is applied, and FIG. 2 is a circuit connection diagram showing a detailed configuration of an input / output test circuit unit in the test circuit.

In the test circuit of the present embodiment shown in FIG. 1, reference numeral 1 denotes an input / output test circuit unit constituting the test circuit, and 2 denotes an internal circuit input / output to / from the input / output test circuit unit 1. 3a and 3b indicate an output to the input / output test circuit unit 1 and an input test mode signal, and 4 indicates a terminal input / output signal from the input / output test circuit unit 1 , I / O pads 5 to input / output terminals 6.

In the detailed configuration of the input / output test circuit unit 1 shown in FIG.
The respective internal circuit output signals input to the input / output test circuit unit 1 from the internal circuit side corresponding to the internal circuit input / output signals 8, 9 and 11 similarly correspond to the internal circuit input / output signal 2 from the input / output test circuit unit 1. Internal circuit input signals input to the internal circuit side, 12 and 13 are output test mode signals respectively corresponding to the output test mode signal 3a, and 14, 15 and 16 are the input test mode signals 3b. The input / output test circuit section 1 includes a path switching circuit for each of these input / output signals.

Next, the operation of the circuit of this embodiment having the above configuration will be described.

In the circuit configuration of FIG. 2, the input / output test circuit section 1 operates as follows.

That is, as for the internal circuit output signal 7 from the internal circuit side, the output test mode signal 12 is set to “H” level, and this is output as the terminal output signal 4 and the input / output terminal 6 is output.
Output.

For the terminal input signal 4 from the input / output terminal 6, the input test mode signal 14 is set to “H” level so that the input test mode signal 14 is input to the internal circuit as the internal circuit input signal 8. When the signal 14 is at "L" level, it is fixed at "L" level.

Similarly, for the terminal input signal 4 from the input / output terminal 6, the input test mode signal 15 is set to “H” level so that it is input to the internal circuit as the internal circuit input signal 9, and When the mode signal 15 is at "L" level, it is fixed at "H" level.

The internal circuit output signal 10 from the internal circuit side is input and output as the terminal output signal 4 by setting the output test mode signal 13 to “H” level and the input test mode signal 16 to “L” level. Output to terminal 6.

Further, with respect to the terminal input signal 4 from the input / output terminal 6, the input test mode signal 16 is set to "H" level so that it is input to the internal circuit as the internal circuit input signal 11, and the input test mode When the signal 16 is at the "L" level, the internal circuit output signal 10 from the internal circuit side is fed back to the internal circuit side as the internal circuit input signal 11.

That is, in the test circuit system according to the present embodiment shown in FIG. 1, the input / output control of the I / O pad 5 is adjusted to the output and input test mode signals 3a and 3b, so that the terminal input / output signal 4 is input / output. The signal is input from the terminal 6 and output to the input / output terminal 6, and at the same time, the signal can be turned back to the internal circuit side separated from the signal path to the input / output terminal 6. It is possible to unify the wiring to the output terminal side.

In the above embodiment, the case where five internal circuit input / output signals are handled has been described. However, the present invention is not limited to the number of internal circuit input / output signals. Although the signal polarity with the output signal is matched, it is a matter of course that the signal polarity may be inverted.

As is clear from the description of the above embodiment, the present invention makes it possible to input / output internal circuit input / output signals and terminal input / output signals via I / O pads, and to internally input / output these input / output signals. And an input / output test circuit unit integrating an input test circuit and an output test circuit. The input / output test circuit unit is connected to the input / output test circuit unit. Because output control is performed to provide the required functions, output to the input / output terminals, input from the input / output terminals, and internal circuits separated from the input / output terminals As a result, the wiring on the input / output terminal side can be reduced to one and the wiring area in the same chip can be reduced, and the evaluation efficiency of the chip can be improved. That There are excellent features.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing a configuration of a test circuit to which one embodiment of the present invention is applied, and FIG. 2 is a circuit connection diagram showing a detailed configuration of an input / output test circuit unit in the test circuit. FIG. 3 is a schematic block diagram showing the configuration of a conventional test circuit and the arrangement of peripheral circuit units. FIGS. 4 and 5 show detailed configurations of an output test circuit unit and an input test circuit unit of the test circuit, respectively. It is a circuit connection diagram. 1 ... I / O test circuit section, 2 ... Internal circuit I / O signal, 3a ... Output test mode signal, 3b ... Input test mode signal, 4 ... Terminal input / output signal, 5 ... I / O pad , 6 ... I / O terminal, 7,10 ... Internal circuit output signal, 8,
9, 11 ... internal circuit input signal, 12, 13 ... output test mode signal, 14, 15, 16 ... input test mode signal.

Claims (1)

(57) [Claims] An input / output test circuit section for inputting / outputting an internal circuit input / output signal on an internal circuit side, inputting / outputting an input / output test mode signal, and having means for switching a path of the internal circuit input / output signal; An I / O pad whose input / output is controlled by a control signal synchronized with an input / output test mode signal; and an input / output terminal for inputting / outputting a terminal input / output signal from the input / output test circuit unit via the I / O pad. The input / output test circuit unit switches the path switching unit according to an input / output test mode signal, and outputs the signal to the input / output terminal.
A test characterized by performing three functions of input from the input / output terminal side and folding back to the internal circuit side separated from the input / output terminal side, and reducing the number of wires to the input / output terminal side to one. Circuit method.