JPH0480676A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0480676A JPH0480676A JP2194466A JP19446690A JPH0480676A JP H0480676 A JPH0480676 A JP H0480676A JP 2194466 A JP2194466 A JP 2194466A JP 19446690 A JP19446690 A JP 19446690A JP H0480676 A JPH0480676 A JP H0480676A
- Authority
- JP
- Japan
- Prior art keywords
- input
- integrated circuit
- output buffer
- test
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000000872 buffer Substances 0.000 claims abstract description 23
- 238000011990 functional testing Methods 0.000 claims description 5
- 238000007689 inspection Methods 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 230000004913 activation Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit.
従来、この種の半導体集積回路は、外部回路素子と内部
集積回路とを接続する人出力バッファを内部集積回路か
ら切離して機能検査できる機構を有していなかった。Conventionally, this type of semiconductor integrated circuit has not had a mechanism for separating a human output buffer that connects an external circuit element and an internal integrated circuit from the internal integrated circuit to perform a functional test.
上述した従来の半導体集積回路は、入出力バッファを内
部集積回路から切離して機能検査てきる機構を有してい
ないので以下の欠点がある。The conventional semiconductor integrated circuit described above has the following drawbacks because it does not have a mechanism for separating the input/output buffer from the internal integrated circuit to perform a functional test.
１、入出力バッファの機能検査をするのに内部集積回路
の活性化が必要である。1. Activation of the internal integrated circuit is required to test the function of the input/output buffer.
２、人出力バッファの不良を内部集積回路の不良と切分
ける事が困難である。2. It is difficult to separate defects in the human output buffer from defects in the internal integrated circuit.
３、半導体集積回路を基板に実装した後の接続検査が困
難である。3. It is difficult to inspect the connections after the semiconductor integrated circuit is mounted on the board.
本発明の半導体集積回路は、外部回路素子と内部集積回
路とを接続する入出力バッファを内部集積回路から切離
して機能検査するためのセレクタ回路を含んで構成され
る。The semiconductor integrated circuit of the present invention is configured to include a selector circuit for separating an input/output buffer connecting an external circuit element and an internal integrated circuit from the internal integrated circuit to perform a functional test.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の一実施例の論理回路図である。FIG. 1 is a logic circuit diagram of one embodiment of the present invention.
外部回路素子と内部集積回路とを接続する入出力バッフ
ァ１の入力側にテスト信号と通常信号を切換える為にセ
レクタ回路２が付加される。A selector circuit 2 is added to the input side of an input/output buffer 1 that connects an external circuit element and an internal integrated circuit to switch between a test signal and a normal signal.
テスト信号端子２０に入力されるテスト信号と通常信号
端子１０に入力される通常信号との切換えは、テストモ
ード切換端子３０に入力されるテストモード切換え信号
により行なわれる。Switching between the test signal input to the test signal terminal 20 and the normal signal input to the normal signal terminal 10 is performed by a test mode switching signal input to the test mode switching terminal 30.
第２図は、第１図に示した回路の一使用例を示すブロッ
ク図である。FIG. 2 is a block diagram showing an example of the use of the circuit shown in FIG. 1.
テストモード切換え信号によりテストモードになると各
人出力バッファ１の入力には、セレクタ２によりテスト
信号が接続され、各入出力バッファは、直列に接続され
る。When the test mode is set by the test mode switching signal, the test signal is connected to the input of each output buffer 1 by the selector 2, and each input/output buffer is connected in series.
従ってテスト信号端子２０に入力されるテスト信号は、
各人出力バッファを通り、最終段の入出力バッファから
出力される。Therefore, the test signal input to the test signal terminal 20 is
It passes through each individual's output buffer and is output from the input/output buffer at the final stage.
なお、各人出力バッファごとにテストモード切換信号を
制御すれば、半導体集積回路を基板に実装した後の接続
検査をする事も可能である。Note that by controlling the test mode switching signal for each output buffer, it is also possible to perform a connection test after the semiconductor integrated circuit is mounted on the board.
以上説明したように本発明は、外部回路素子と内部集積
回路とを接続する入出力バッファを内部集積回路から切
離して機能検査できる機構を半導体集積回路に持たせる
事により、以下の効果かある。As explained above, the present invention has the following effects by providing a semiconductor integrated circuit with a mechanism that can disconnect the input/output buffer that connects the external circuit element and the internal integrated circuit from the internal integrated circuit and perform a functional test.
１、人出力バッファの機能検査をするのに内部集積回路
の活性化が必要ない。1. There is no need to activate the internal integrated circuit to test the function of the human output buffer.
２、人出力バッファの不良を内部集積回路の不良と切分
ける事が容易である。2. It is easy to separate defects in the human output buffer from defects in the internal integrated circuit.
３、半導体集積回路を基板に実装した後の接続検査が容
易である。3. Connection inspection after the semiconductor integrated circuit is mounted on the board is easy.
第１図は本発明の一実施例の論理回路図、第２図は第１
図に示した半導体集積回路の一使用例を示すブロック図
である。
１・・・人出力バッファ、２・・・２−１セレクタ回路
、１０・・・通常信号端子、２０・・・テスト信号端子
、３０・・・テストモード切換端子。FIG. 1 is a logic circuit diagram of an embodiment of the present invention, and FIG. 2 is a logic circuit diagram of an embodiment of the present invention.
FIG. 2 is a block diagram showing an example of use of the semiconductor integrated circuit shown in the figure. DESCRIPTION OF SYMBOLS 1... Human output buffer, 2... 2-1 selector circuit, 10... Normal signal terminal, 20... Test signal terminal, 30... Test mode switching terminal.
Claims (1)
ァを内部集積回路から切離して機能検査するためのセレ
クタ回路を含むことを特徴とする半導体集積回路。A semiconductor integrated circuit comprising a selector circuit for separating an input/output buffer connecting an external circuit element and an internal integrated circuit from the internal integrated circuit to perform a functional test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2194466A JPH0480676A (en) | 1990-07-23 | 1990-07-23 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2194466A JPH0480676A (en) | 1990-07-23 | 1990-07-23 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0480676A true JPH0480676A (en) | 1992-03-13 |
Family
ID=16325028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2194466A Pending JPH0480676A (en) | 1990-07-23 | 1990-07-23 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0480676A (en) |
-
1990
- 1990-07-23 JP JP2194466A patent/JPH0480676A/en active Pending
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