JP2000150557A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法

Info

Publication number
JP2000150557A
JP2000150557A JP10324125A JP32412598A JP2000150557A JP 2000150557 A JP2000150557 A JP 2000150557A JP 10324125 A JP10324125 A JP 10324125A JP 32412598 A JP32412598 A JP 32412598A JP 2000150557 A JP2000150557 A JP 2000150557A
Authority
JP
Japan
Prior art keywords
film
resin sealing
external terminal
sealing film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10324125A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000150557A5 (enExample
Inventor
Fujio Ito
富士夫 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Priority to JP10324125A priority Critical patent/JP2000150557A/ja
Publication of JP2000150557A publication Critical patent/JP2000150557A/ja
Publication of JP2000150557A5 publication Critical patent/JP2000150557A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP10324125A 1998-11-13 1998-11-13 半導体装置およびその製造方法 Pending JP2000150557A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10324125A JP2000150557A (ja) 1998-11-13 1998-11-13 半導体装置およびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10324125A JP2000150557A (ja) 1998-11-13 1998-11-13 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
JP2000150557A true JP2000150557A (ja) 2000-05-30
JP2000150557A5 JP2000150557A5 (enExample) 2004-10-28

Family

ID=18162437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10324125A Pending JP2000150557A (ja) 1998-11-13 1998-11-13 半導体装置およびその製造方法

Country Status (1)

Country Link
JP (1) JP2000150557A (enExample)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004273591A (ja) * 2003-03-06 2004-09-30 Seiko Epson Corp 半導体装置及びその製造方法
JP2006140525A (ja) * 2006-01-10 2006-06-01 Dainippon Printing Co Ltd 半導体装置の実装体、半導体装置実装体の製造方法
KR100881389B1 (ko) 2002-12-26 2009-02-05 주식회사 하이닉스반도체 반도체소자의 패키지 구현방법
US7935573B2 (en) 2005-01-31 2011-05-03 Fujitsu Limited Electronic device and method for fabricating the same
JP2013530523A (ja) * 2010-05-20 2013-07-25 クアルコム，インコーポレイテッド 裏面モールド構成（ｂｓｍｃ）の使用によるパッケージの反りおよび接続の信頼性を向上させるためのプロセス
US8841168B2 (en) 2011-09-09 2014-09-23 Qualcomm Incorporated Soldering relief method and semiconductor device employing same
US9673159B2 (en) 2014-11-10 2017-06-06 Rohm Co., Ltd. Semiconductor device and manufacturing method for the same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100881389B1 (ko) 2002-12-26 2009-02-05 주식회사 하이닉스반도체 반도체소자의 패키지 구현방법
JP2004273591A (ja) * 2003-03-06 2004-09-30 Seiko Epson Corp 半導体装置及びその製造方法
US7935573B2 (en) 2005-01-31 2011-05-03 Fujitsu Limited Electronic device and method for fabricating the same
JP2006140525A (ja) * 2006-01-10 2006-06-01 Dainippon Printing Co Ltd 半導体装置の実装体、半導体装置実装体の製造方法
JP2013530523A (ja) * 2010-05-20 2013-07-25 クアルコム，インコーポレイテッド 裏面モールド構成（ｂｓｍｃ）の使用によるパッケージの反りおよび接続の信頼性を向上させるためのプロセス
US8742603B2 (en) 2010-05-20 2014-06-03 Qualcomm Incorporated Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC)
US8841168B2 (en) 2011-09-09 2014-09-23 Qualcomm Incorporated Soldering relief method and semiconductor device employing same
US9673159B2 (en) 2014-11-10 2017-06-06 Rohm Co., Ltd. Semiconductor device and manufacturing method for the same
US9905518B2 (en) 2014-11-10 2018-02-27 Rohm Co., Ltd. Method of manufacturing a semiconductor device

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