JP2000059351A - Serial data monitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the serial data monitor that monitors a data error without addition of an excess signal line and without the need of increasing a signal transmission rate of transmission data and reproduces a frame pulse FP for a downstream even in the case of detecting an error in a transmission line. SOLUTION: A transmission block exclusively Ors transmission data 26 and a synchronization FP 32 to generate a transmission FP 24, and a receiver side exclusively Ors received data and the transmission FP 24 to detect matching of a prescribed frame period. Thus, an error in a transmission line caused on the way of transmission can be detected. Furthermore, even in the case that nonmatching of a frame period is detected due to occurrence of the error in the transmission line in this way, an FP phase error on the occurrence of a bit error is absorbed and a normal FP is supplied to the downstream by transmitting a self-oscillated FP to the downstream as a reproduced FP 50 in matching with a phase of a frame synchronization protect signal 48 that is a matching detection signal with a period of a frame having been received so far after n-stage of protection.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a serial data monitoring device, and more particularly, to a serial data monitoring device for monitoring an error in serial transmission data synchronized on a transmission / reception side.

[0002]

2. Description of the Related Art Conventionally, in digital transmission, a high-order group digital signal created by dividing and multiplexing a plurality of low-order group digital signals on a time axis on a transmitting side is transmitted and separated on a receiving side. To obtain the original low-order group digital signal. In such digital transmission, signals need to be synchronized with each other in order to properly multiplex (separate) low (high) order digital signals on both the transmitting and receiving sides.
One of the synchronization techniques is frame synchronization. In frame synchronization, a time-division multiplexed higher-order group digital signal is used as a signal group called a "frame", which is used as a serial data transmission unit, and a pulse group having a specific pattern called a frame synchronization pulse pattern is inserted. Is used as a frame boundary. On the receiving side, the low-order group digital signal can be correctly separated from the received frame by identifying the frame synchronization pulse pattern from the received frame. In such frame-synchronous digital transmission, it is desired to avoid loss of synchronization on the transmitting / receiving side or to recover early. One of them is a synchronization clock signal and a frame pulse (Frame Pulse:
Hereinafter, it is abbreviated as FP. ) Is used to transmit serial data to detect a failure during transmission.

FIG. 7 shows the outline of the configuration of a serial data monitoring device for frame synchronous transmission proposed in the prior art. In this device, a transmission block 10 and a reception block 11 are connected via a transmission line 12. The transmission path 12 includes signal lines for transmitting the serial data 13, the FP 14, the synchronous clock signal 15, and the parity signal 16, respectively. The parity signal 16 is parity information of the transmission data generated by the transmission block 10 and is intended to detect a failure when a data error occurs during transmission between the transmission side and the reception side. By comparing the parity information with the parity generated from the reception data in the reception block 11, an error in the reception data can be detected. As the parity information, there is an even parity or an odd parity depending on whether the number of data bits "1" is an even number or an odd number. When an error in the received data is detected by the parity signal 16, the reception side requests the retransmission from the transmission side to prevent erroneous synchronization detection.

Japanese Patent Application Laid-Open No. H5-219044 discloses that
A frame synchronization circuit that uses a 0, 1 alternation pattern as a frame synchronization pattern at the beginning of a data block stores at least one frame of serial data in a shift register, and outputs the shift data of one frame before from the shift register. By always logically determining the 0, 1 alternating relationship between the bits at the same position in each frame of the output shift data and the received data,
There is disclosed a technique in which the backward protection operation time from the out-of-synchronization state to the synchronization establishment state is reduced.

[0005]

The conventional serial data monitoring device shown in FIG. 7 has a data signal line, a synchronous clock signal line, and an FP for transmitting the parity generated on the transmission side to the reception side. It is necessary to add a parity signal line in addition to the signal line. Therefore, in the case of long-distance transmission, an additional signal line and a relay device are required, resulting in a problem that the cost becomes extremely high. As a measure for avoiding the addition of such a parity signal line, means for increasing the transmission speed and multiplexing the parity of the transmission side data with the transmission data can be used. Voltage Controll
An ed Oscillator (VCO) or the like must be used, resulting in an increase in circuit scale. In addition, when the signal speed increases, the transmission characteristics are affected by the frequency characteristics of the transmission / reception device or the transmission path. When transmitting the same distance as the original signal speed, deterioration during transmission cannot be avoided, and the transmission distance becomes shorter. turn into. As a result, a relay device or the like is required, which increases the cost.

A frame synchronization pattern as disclosed in Japanese Patent Application Laid-Open No. H5-219044 is applied to data blocks 0, 1
If the boundary of the frame is identified by the alternating pattern, the length of the data to be transmitted becomes longer when trying to transmit the same information as the information transmitted by the system of FIG. Focusing on the properties of serial data, the shorter the transmission time is, the higher the transmission speed is at the same transmission speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a serial data monitoring apparatus for monitoring a data error without adding an extra signal line and without increasing the signal speed of transmission data.

Another object of the present invention is to provide a serial data monitoring apparatus capable of reproducing an FP downstream even if an error in a transmission line is detected on the receiving side by monitoring data errors as described above. Is to provide.

[0009]

According to the first aspect of the present invention, (a) pulse transmission for generating a pulse transmission signal from first frame pulses indicating the boundaries of these frames based on framed transmission data. Signal generating means, (b) transmitting means for transmitting the transmission data and the pulse transmission signal generated by the pulse transmission signal generating means to separate transmission paths, respectively, and (c) the transmitting means via the transmission path by the transmitting means. Receiving means for receiving the transmitted transmission data and the pulse transmission signal; and (d) the same period as the first frame pulse from the pulse transmission signal received by the receiving means based on the transmission data received by the reception means. A frame pulse generating means for generating a second frame pulse of (e), and a second frame pulse generated by the frame generating means. An identical period determining means for determining whether the frame pulse has the same period as the first frame pulse; and (f) when the first and second frame pulses are determined not to be the same period by the same period determining device. The serial data monitoring device is provided with transmission line error occurrence notifying means for notifying the occurrence of an error in the transmission line.

That is, according to the first aspect of the present invention, the transmission data framed and the first data indicating the frame boundaries.
, A pulse transmission signal is generated from the frame pulse and transmitted to the transmission line together with the transmission data. Then, when these are received via a transmission path, a second frame pulse having the same cycle as the first frame pulse is generated from the pulse transmission signal based on the transmission data received by the frame pulse generating means. The same-period determining means determines whether or not the cycle of the second frame pulse is the same as the first frame pulse. In the above, it is determined that an error has occurred in the transmission path during transmission.

According to the second aspect of the present invention, (a) pulse transmission for generating a pulse transmission signal from first frame pulses indicating boundaries of these frames based on transmission data framed in synchronization with a reference clock. Signal generating means, (b) transmitting means for transmitting the transmission data and the pulse transmission signal generated by the pulse transmission signal generating means to separate transmission paths, respectively, and (c) the transmitting means via the transmission path by the transmitting means. (D) receiving means for receiving the transmitted transmission data and the pulse transmission signal; and (d) generating, from the pulse transmission signal received by the reception means based on the transmission data received by the reception means, the same period as the first frame pulse. A frame pulse generating means for generating a second frame pulse, and (e) a second frame pulse generated by the frame generating means. The same-period determination means for determining whether or not the frame pulse has the same period as the first frame pulse; and (f) the first and second frame pulses are determined not to be the same period by the same-period determination means. A transmission path error notifying means for notifying the occurrence of a transmission path error and stopping the output of the second frame pulse; and (g) a self-running frame pulse having the same cycle as the first frame pulse based on the reference clock. And (h) outputting the self-propelled frame pulse generated by the self-propelled frame pulse generating means in accordance with the phase of the second frame pulse generated by the frame pulse generating means. The serial data monitoring device includes the frame pulse phase adjusting means.

That is, according to the second aspect of the present invention, a pulse transmission signal is generated from transmission data framed in synchronization with the reference clock and the first frame pulse indicating these frame boundaries, and transmitted to the transmission line together with the transmission data. I am trying to do it. Then, when these are received via a transmission path, a second frame pulse having the same cycle as the first frame pulse is generated from the pulse transmission signal based on the transmission data received by the frame pulse generating means. The same-period determining means determines whether or not the cycle of the second frame pulse is the same as the first frame pulse. Determines that an error has occurred in the transmission path during transmission, and stops outputting the second frame pulse. Further, the self-running frame pulse generating means generates a self-running frame pulse having the same cycle as the first frame pulse based on the reference clock,
This self-running frame pulse is generated in accordance with the phase of the frame pulse. Accordingly, even when the transmission path error occurrence notifying unit detects the occurrence of an error during transmission, the first frame pulse and the first frame pulse are synchronized with the phase of the second frame pulse when no transmission path error occurs. The same period of the frame pulse can be supplied to the downstream device.

According to a third aspect of the present invention, in the serial data monitoring device according to the first or second aspect, the frame generation means determines the first frame pulse having the same period as the first frame pulse from the pulse transmission signal based on the transmission data. The third frame pulse is generated, and the second frame pulse is generated by protecting the synchronization of the third frame pulse.

That is, according to the third aspect of the present invention, after generating a third frame pulse having the same period as the first frame pulse from the pulse transmission signal based on the transmission data,
A frame pulse with synchronization protection is output as a second frame pulse. As a result, frame synchronization protection conventionally used for preventing erroneous synchronization can be performed, and reliability can be further improved.

According to a fourth aspect of the present invention, in the serial data monitoring device according to the second aspect, the frame pulse phase adjusting means is configured to generate the second frame pulse generated by the frame pulse generating means.
When the frame pulse is not input within a predetermined period, the output of the free-running frame pulse is stopped.

That is, when the second frame pulse generated by the frame pulse generating means is not input within a predetermined period,
In a system in which it is determined that a transmission path error occurs frequently and it is not preferable to transmit a frame pulse to a downstream device in such a case, transmission of the free-running frame pulse can be stopped.

According to a fifth aspect of the present invention, in the serial data monitoring device according to the first or second aspect, the pulse transmission signal performs an exclusive OR operation on the transmission data and the first frame pulse in bit units. The second frame pulse is generated by performing an exclusive OR operation on the transmission data and the pulse transmission signal received by the receiving unit in bit units.

That is, in the pulse transmission signal according to the fifth aspect of the present invention, the first frame pulse and the transmission data are exclusive-ORed in bit units in the pulse transmission signal, and the second frame pulse is pulse-transmitted with the received transmission data. The signal and the signal are generated by taking the exclusive OR in bit units.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows an outline of a configuration of a serial data monitoring device according to an embodiment of the present invention. In this serial data monitoring device, a transmission block 20 and a reception block 21 are connected via a transmission line 22. On the transmission line 22, a serial data signal 23, a transmission FP 24 and a synchronous clock signal 25 are separately transmitted. As described above, in the serial data monitoring device according to the present embodiment, the clock synchronized with the transmission block 20 and the reception block 21 is supplied as the synchronization clock signal 25, and the frame synchronous transmission for transmitting the serial data using the FP is performed. ing. The feature of the serial data monitoring device in the present embodiment is that the transmission side generates exclusive OR of the FP and the transmission data to generate information for detecting a signal error on the transmission path, and the reception side generates the information. The first feature is that an exclusive OR of information for detecting the signal error and received data is used to detect occurrence of an error in the transmission path. Further, the received serial data signal 23, error detection signal 24 and synchronous clock signal 2
The second feature is that the FP is reproduced from 5.

In the transmission block 20 of such a serial data monitoring device, the transmission data 26 whose data to be transmitted is serial data is converted by the signal splitter 27 into the first data.
The second branch transmission data 29 and the second branch transmission data 29 are divided into two. The second branch transmission data 29 is input to the flip-flop 30 and is retimed by the synchronization clock 25 synchronized on the transmission and reception sides. The transmission data retimed by the flip-flop 30 is sent to the reception block 21 as a serial data signal 23. On the other hand, the second branch transmission data 29 is input to one input terminal of an exclusive OR (EXOR) circuit 31. The synchronous FP 32 is input to the other input terminal of the EXOR circuit 31. The exclusive OR of the second branch transmission data 29, which is serial data, and the synchronous FP 32 is calculated in bit units.
It is sent out as an EXOR operation signal 33. This EXOR
The operation signal 33 is input to the flip-flop 34 and is retimed by the synchronous clock 25. The EXOR operation signal retimed by the flip-flop 34 is sent to the reception block 21 as the transmission FP 24.

Reception block 2 of serial data monitoring device
At 0, the serial data signal 23 is input to the signal splitter 35. The transmission data signal input to the signal splitter 35 is split into two pieces, a first split received data 36 and a second split received data 37. The first branch received data 36 is
The signal is input to the flip-flop 38 and is retimed by the synchronous clock 25 synchronized on the transmitting and receiving sides. The branch reception data retimed by the flip-flop 38 becomes reception data 39 which is serial data to be received by the reception block 21. On the other hand, the second branch reception data 37 is input to one input terminal of the EXOR circuit 40. The transmission FP 24 is input to the other input terminal of the EXOR circuit 40, and the EXOR circuit 3
The exclusive-OR operation is performed on the transmission FP and the reception data, for which the exclusive-OR operation has been performed between the synchronous FP 32 and the transmission serial data in step 1, and the exclusive-OR operation is performed again in bit units, and the EXOR operation signal
Is sent as The EXOR operation signal 41 is formed by combining the serial data signal 23 received by the signal splitter 35 with the EXOR signal.
The transmission FP 24 and the synchronous clock 25 received by the circuit 40
If there is no transmission error in any of them, the same signal as that of the synchronous FP 32 is obtained. The EXOR operation signal 41 is input to the flip-flop 42 and is retimed by the synchronous clock 25. The EXOR operation signal retimed by the flip-flop 42 is input to the frame period counter 44 as the reception FP 43.

The frame cycle counter 44 can detect whether or not the reception FP 43 is input at the same predetermined frame cycle F as when transmitting. When it is detected that the receiving FP 43 is input at a predetermined frame period F, a frame period matching signal 45 having the same period as this frame period can be output. On the other hand, if it is detected that the receiving FP 43 has not been input for the predetermined frame period, it is determined that an error has occurred during signal transmission, and the alarm signal 46 can be output as a data error alarm. ing. The warning signal 46 can be used to request the retransmission of the transmission side, or to improve the reliability of the transmission data by discarding the reception data.

The frame cycle match signal 45 output from the frame cycle counter 44 is input to the frame protection circuit 47 at the same cycle as the synchronous FP 32. The frame protection circuit 47 performs n-stage frame synchronization protection to prevent erroneous synchronization, and outputs a frame synchronization protection signal 48 when n stages match. This frame synchronization protection signal 48 is input to the FP generation circuit 49 as a trigger signal. The FP generation circuit 49 can output the reproduction FP 50 in accordance with the input phase of the frame synchronization protection signal 48. Also, even when the frame synchronization protection signal 48 is not input due to a transmission error, the FP phase error due to the signal error during transmission is absorbed by performing self-running at the frame period, and the FP at the normal timing is output as the reproduction FP 50. You can do it. As a result, the synchronization F
Even when the phase of P32 changes, it is possible to output an FP at a normal timing after the n-stage synchronization protection.

Next, a description will be given of a main part of a receiving block enabling reproduction of such an FP. First, an example of the configuration of the frame period counter 44 will be described.

FIG. 2 shows a main configuration of the frame period counter 44 shown in FIG. The frame cycle counter 44 includes a counter 55. The counter 55 includes the synchronous clock 25 and the reception FP4
3 are input. The counter 55 counts using the synchronous clock 25 as a reference clock, and
The count value is reset by P43. After the counter 55 finishes counting for the same frame period as that of the synchronous FP 32 of the transmission block 20, the counter 55 sends the frame period coincidence signal 45, but does not start counting unless the receiving FP 43 is input. I have.
Therefore, as long as the appropriate receiving FP 43 is input in advance corresponding to the same frame period as the synchronous FP 32 of the transmission block 20, the counter 55 can output the frame period matching signal 45 every frame period. Has become. Also, this frame period counter 44
Is provided with an EXOR circuit 56, which receives the receiving FP 43 and the frame period matching signal 45, and outputs an exclusive OR of them as an alarm signal 46. That is, when the appropriate receiving FP 43 is input to the counter 55 and the frame cycle matching signal 45 is not output at the same timing as the receiving FP 43 using the synchronous clock 25 as a reference clock, this error is output as a warning signal 46 as a pulse. Will be. At this time, a plurality of 46 alarm signal pulses are output in one frame.

FIG. 3 shows an operation waveform of each signal when the reception FP 43 is erroneously inserted in the frame period counter 44 shown in FIG. 3A shows the outline of the operation waveform of the reception FP 43, FIG. 3B shows the outline of the operation clock of the synchronous clock 25, FIG. 3C shows the outline of the operation waveform of the frame period coincidence signal 45, and FIG. .

When no error occurs during transmission as in the frames 57 and 58 and the receiving FP 43 is input to the frame period counter 44 at the same frame period F as the synchronous FP 32 as shown by the waveform 59, the counter 55 Is reception F
Each time P43 is input, counting is performed using the synchronous clock 25 shown in the waveform 60 as a reference clock, and a frame cycle coincidence signal 45 is output every frame cycle identical to the synchronous FP 32 of the transmission block 20 (waveform 61 in FIG. 3). .
At this time, since the reception FP 43 and the frame cycle coincidence signal 45 are output at the same timing, the pulse of the alarm signal 46 is not output (waveform 62 in FIG. 3).

However, when an error occurs during transmission and the error pulse 64 of the frame 63 is inserted into the receiving FP 43, the counter 55 sets the first receiving FP 43
When the pulse 65 is input, counting is started. However, the counter 55 includes the synchronous FP 32 of the transmission block 20.
Since the error pulse 64 is input before the count for the same frame period is completed, the count value is reset again at this point. Therefore, counter 5
5 indicates that the predetermined frame period coincidence signal 45 of the frame 66 is not output (pulse 67 in FIG. 3). EXOR
Since the circuit 56 outputs an exclusive OR of the reception FP 43 and the frame period coincidence signal 45 output from the counter 55, the timing of the error pulse 64 inserted into the reception FP 43 of the frame 63 and the frame period of the frame 66 At the timing of the pulse 67 that should be output as the coincidence signal 45, two pulses are output as the alarm signal 46 (pulses 68 ₁ and 68 _{2 in} FIG. 3). Further, even if an error occurs during transmission of the synchronous clock signal 25, it can be similarly detected.

FIG. 4 shows an operation waveform of each signal when the reception FP 43 is not erroneously inserted in the frame period counter 44 shown in FIG. FIG. 4 (a)
3B shows the outline of the operation waveform of the reception FP 43, FIG. 3B shows the outline of the synchronous clock 25, FIG. 3C shows the outline of the operation waveform of the frame period coincidence signal 45, and FIG.

When no error occurs during transmission as in the frames 57 and 58 and the receiving FP 43 is input to the frame period counter 44 at the same frame period F as the synchronous FP 32 as shown by the waveform 59, the counter 55 Is reception F
Each time P43 is input, counting is performed using the synchronous clock 25 shown in the waveform 60 as a reference clock, and a frame cycle match signal 45 is output every frame cycle identical to the synchronous FP 32 of the transmission block 20 (waveform 61 in FIG. 4). .
At this time, since the receiving FP 43 and the frame cycle matching signal 45 are output at the same timing, the pulse of the alarm signal 46 is not output (waveform 62 in FIG. 4).

However, when an error occurs during transmission,
Pal that should have been inserted into the receiving FP 43 of the
When there is no contact (69 in FIG. 4)₁), Counter 55 is free
Counting is started by the input of the receiving FP 43 of the system 66
Therefore, in this frame, the count of the counter 55 is
Not started. Therefore, the next frame of the frame 66
Of the frame period match signal 45, which should be output first,
Not output (69 in FIG. 4)_Two). The EXOR circuit 56
Frame period which is the output of reception FP 43 and counter 55
Since an exclusive OR with the coincidence signal 45 is output,
Pulse 6 that is supposed to be inserted into the receiving FP 43 of the
9₁And the beginning of the frame following frame 66
To be output to the frame period coincidence signal 45.
Luz 69 _TwoAt the timing of
Two pulses are output (pulse 68 in FIG. 4).₁, 6
8_Two). Also, an error occurs during the transmission of the synchronous clock signal 25.
Even if it occurs, it can be detected similarly.

As described above, the frame period counter 44
The count value is reset by the input of the receiving FP 43, and the counter 55 is provided so that after the counting is completed, the counting is not started unless the receiving FP 43 is input. Then, the count value is output as a frame cycle coincidence signal 45 based on the synchronous clock 25,
By taking the exclusive OR of the frame cycle matching signal 45 and the receiving FP 43, an error during the transmission of the receiving FP 43 or the synchronous clock 25 is detected, and this is output as the frame cycle matching signal 45 and the alarm signal 46. Is available.

The frame protection circuit 47 is a well-known frame synchronization protection circuit having n front stages and one rear stage, and is not shown. The frame cycle matching signal 45 input to the frame protection circuit 47 should be input at the same cycle F as the synchronous FP 32 if there is no transmission error. Therefore, a frame position pulse output at a period F is generated, and whether or not this is output at the same timing as the frame period coincidence signal 45 is detected for each frame. When it is detected that synchronization has been achieved, it is determined that synchronization has been achieved, and protection of the rear n stages is performed. In this manner, when it is detected that output is performed n times at the same timing, the frame synchronization protection signal 48 is output to the FP generation circuit 49 as a trigger signal. Of course, it is desirable to select the optimal number of front protection steps and the number of rear protection steps according to the system to be applied.

Next, the FP generation circuit 49 will be described.

FIG. 5 shows an outline of the configuration of the FP generation circuit 49. The frame synchronization protection signal 48 input to the FP generation circuit 49 is input to the phase detection circuit 70. The phase detection circuit 70 can detect a phase shift of the frame synchronization protection signal 48 from the synchronization clock 25, and sends the phase shift to the free-running FP generation circuit 71. The self-running FP generation circuit 71 self-runs based on the synchronization clock 25, generates a self-running FP 75 having the same frame period F as the synchronization FP 32 of the transmission block 20, and outputs the phase shift notified from the phase detection circuit 70. This can be output as the reproduction FP 50 in accordance with the setting.

As described above, the FP generation circuit 49 outputs the reproduced FP 50 whose phase has been adjusted according to the input phase of the frame synchronization protection signal 48, and even if the frame synchronization protection signal 48 is not input due to a transmission path error. By outputting the free-running FP in the frame period F, it is possible to absorb an FP phase error at the time of a bit error and output a normal FP downstream.

Next, the operation of the serial data monitoring device having the essential configuration described above with reference to FIGS. 1 and 6 will be described.

FIG. 6 shows the outline of the signal operation waveform of each part of the serial data monitoring device in this embodiment. Here, the frame protection circuit 47 is two steps forward and one step backward.
It is assumed that the stage is a frame synchronization protection circuit. 6A shows a synchronous clock signal 25, FIG. 6B shows transmission data 26, and FIG.
FIG. 3C shows the signal operation waveform of the synchronous FP 32, and FIG. 3D shows the signal operation waveform of the EXOR operation signal 33. The signal operation waveform of each unit in the reception block 21 is as follows.
6E shows the synchronous clock signal 25, FIG. 6F shows the serial data signal 23, FIG. 6G shows the transmission FP 24, FIG. 6H shows the EXOR operation signal 41, and FIG. The coincidence signal 45, FIG. 3 (j) shows the signal synchronization waveform of the frame synchronization protection signal 48, and FIG. 3 (k) shows the signal operation waveform of the reproduction FP 50.

In the transmission block 20, the synchronous clock signal 25 and the transmission data 26 are respectively shown in FIG.
It is assumed that the input is made as shown in (b) (waveforms 80 and 81 in FIG. 6). The synchronization clock signal 25 is synchronized in the transmission block 20 and the reception block 21 (waveforms 80 and 82 in FIG. 6). The synchronous FP 32 is input every predetermined frame period F in synchronization with the synchronous clock 25 (waveform 83 in FIG. 6). The transmission data 26 is bifurcated into first and second branch transmission data 28 and 29 by a signal branching device 27, and an exclusive OR of the synchronous FP 32 and the second branch transmission data 28 is calculated in an EXOR circuit 31. . That is, “1” is set only when the transmission data 26 and the synchronous FP 32 at the same timing have mutually opposite bit values of 1 or 0 in bit units.
As a result, the EXOR operation signal 33 is output (waveform 84 in FIG. 6). The EXOR operation signal 33 and the first branch transmission data 28 are both retimed by the flip-flops 34 and 30 with the synchronous clock 25. As described above, the transmission block 20 transmits the synchronous clock signal 25 and the transmission FP 24 and the serial data signal 23 retimed by this signal, thereby preventing an increase in the number of monitoring signals and the like for detecting transmission errors. I have.

In the receiving block 21, the serial data signal (waveform 85 in FIG. 6) transmitted by the transmitting block 20 via the transmission line 22 is converted by the signal branching unit 35 into first and second branched received data 36, 37. Is branched into two. Here, the serial data signal 23 shown in FIG.
It is assumed that a transmission path error as shown in FIG. As described above, the transmission FP 24 merely retimes the EXOR operation signal 33 with the flip-flop, and thus the waveform in each frame is transmitted with the same waveform as the EXOR operation signal 33 shown in FIG. Waveform 8 of 6
7). Therefore, the EXOR circuit 41 of the receiving block 21
When an exclusive logical operation is performed on the second branch reception data 33 obtained by branching the serial data signal into two and the transmission FP 24, the value becomes “1” only when the bit values are mutually inconsistent 1 or 0 in bit units. Therefore, if there is no transmission path error, the same waveform as that of the synchronous FP 32 is output as the EXOR operation signal 41. However, when there is a transmission line error as indicated by a broken line portion 86, the erroneous detection pulse 88 is detected at the same timing as the transmission line error position by the exclusive OR operation in the EXOR circuit 41 (FIG. 6). Waveform 8 of
9).

When the EXOR operation signal 41 is retimed by the flip-flop 42 and then input to the frame period counter 44, the counter 55 shown in FIG.
Does not output the frame period coincidence signal 45 counted in accordance with the input of the reception FP 43 for each frame period F (waveform 90 in FIG. 6), and simultaneously judges that a transmission line data error has occurred and An alarm signal 46 will be output. However, except for the transmission path error indicated by the broken line 86, the frame cycle coincidence signal 45
Is output every time (waveform 91 in FIG. 6).

The frame protection circuit 47 protects the pulse of the frame period coincidence signal 45 so that data may be erroneous at the frame period and the frame period coincidence signal 45
In order to prevent the transmission of an erroneous frame pulse downstream even if the pulse of
We take step protection. As a result, the frame synchronization protection signal 48 is output only after the frame period coincidence signal 45 is input twice in succession at the predetermined frame period F (waveform 92 in FIG. 6). When the frame synchronization protection signal 48 is input, the FP generation circuit 49 generates the reproduction FP 50 by itself in accordance with the cycle. Even if the frame synchronization protection signal 48 shown in FIG. 6 (j) is lost in the frame protection circuit 47, the reproduction FP is normally transmitted downstream at the frame period F (waveform 93 in FIG. 6).

As described above, the serial data monitoring apparatus according to the present embodiment performs an exclusive OR operation of the transmission data 26 and the synchronous FP 32 in the transmission block 10 to perform transmission F.
P24 is generated, and on the reception side, the reception data and transmission FP24
To detect the coincidence with a predetermined frame period F. This makes it possible to detect a transmission path error occurring during transmission. Further, when an error occurs in the transmission path and a mismatch with the frame period F is detected in this way, the frame synchronization signal which is the match detection signal with the frame period F input up to then after protection of n stages is detected. Play the self-running FP in accordance with the phase of the protection signal 48.
By transmitting the FP to the downstream as P50, an FP phase error at the time of a bit error is absorbed, and a normal FP is supplied to the downstream side.

Modification

In the serial data monitoring apparatus according to the present embodiment, the frame cycle counter 44, the frame protection circuit 47 and the FP generation circuit 49 allow the FP generation circuit 4 to operate even when a data error occurs in the frame cycle counter 44.
The playback FP is sent downstream by the self-propelled FP generated in step 9. However, depending on the system, if data errors frequently occur, there is a case where it is no longer necessary to send the FP downstream. Therefore, in the FP generation circuit of the serial data monitoring device in the present embodiment, the frame protection circuit 4
8 to monitor the frame synchronization protection signal 48,
If the input of this signal is not detected due to the absence of an arbitrary plurality of N frames during a certain period, the transmission of the reproduction FP 50 is stopped to prevent unnecessary FPs from being transmitted downstream. be able to.

In the serial data monitoring apparatus according to the present embodiment and the modified example, the transmission side generates an exclusive logical sum of the transmission data and the FP, and the reception side generates the exclusive FP of the reception data and the transmission FP. Although the FP is reproduced by the logical sum and the transmission path error during the transmission is detected, the calculation on the transmitting side and the receiving side is not limited to the exclusive OR calculation. The calculation method is not limited to this calculation method as long as the transmission data and the FP on the transmission side and the transmission FP and the reception data on the reception side can be calculated and the transmission path error can be detected and the FP can be reproduced on the reception side.

It should be understood that the present invention is not limited to the configuration of the main part of the frame cycle counter 44 or the FP generation circuit 49 in the present embodiment and the present modification.

The transmission block 20 and the reception block 21
Is not limited to the signal form of the transmission path. For example, the signal transmitted via the transmission path may be an optical signal or an electric signal.

[0051]

As described above, according to the first aspect of the present invention, it is possible to detect the occurrence of a transmission path error occurring during transmission without newly adding a signal line between transmission / reception blocks, and , The frame pulse can be reproduced. Furthermore, since it is not necessary to use a technique of increasing the transmission speed and multiplexing the signal, the size of the apparatus can be reduced. Further, since only the data signal line, the FP, and the clock signal line need be connected between the transmission / reception blocks, it is not necessary to change the transmission path even if the transmission / reception side needs to change the transmission / reception block. ing.

According to the second aspect of the present invention, in addition to the effect of the first aspect, even if the transmission path error occurrence notifying means detects the occurrence of an error during transmission, a transmission path error occurs. In accordance with the input phase of the second frame pulse when not performed, a frame pulse having the same cycle as the first frame pulse can be supplied to the downstream device.

Further, according to the third aspect of the present invention, it is possible to perform frame synchronization protection which has been conventionally used for preventing erroneous synchronization, and it is possible to further improve reliability.

According to the fourth aspect of the present invention,
Even in a system where it is not preferable to transmit the frame pulse to the downstream device, the present invention can be applied only by stopping the transmission of the free-running frame pulse.

Further, according to the fifth aspect of the present invention, since the exclusive OR can be realized with a very simple configuration, the cost of the apparatus can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an outline of a configuration of a frame data monitoring device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an outline of a main configuration of a frame period counter according to the embodiment.

FIG. 3 is a timing chart showing an operation waveform of each unit when a pulse due to a transmission error of the frame period counter is inserted in the embodiment.

FIG. 4 is a timing chart showing operation waveforms of the respective units when there is no pulse to be originally inserted due to a transmission error of the frame period counter in the embodiment.

FIG. 5 is a block diagram illustrating an outline of a main configuration of an FP generation circuit according to the embodiment.

FIG. 6 is a timing chart showing operation waveforms of each unit of the frame data monitoring device in the embodiment.

FIG. 7 is a block diagram showing an outline of a configuration of a conventionally proposed frame synchronous transmission system.

[Explanation of symbols]

 Reference Signs List 20 transmission block 21 reception block 22 transmission path 23 serial data signal 24 transmission FP 25 synchronous clock signal 26 transmission data 27, 35 signal splitter 28 first branch transmission data 29 second branch transmission data 30, 34, 38, 42 Flip-flop 31, 40 EXOR circuit 32 Synchronous FP 33, 41 EXOR operation signal 36 First branch received data 37 Second branch received data 39 Received data 43 Receive FP 44 Frame cycle counter 45 Frame cycle match signal 46 Alarm signal 47 Frame Protection circuit 48 Frame synchronization protection signal 49 FP generation circuit 50 Playback FP

Claims (5)

[Claims] 1. A pulse transmission signal generating means for generating a pulse transmission signal from a first frame pulse indicating a boundary of each of these frames based on framed transmission data, and said transmission data and said pulse transmission signal generating means. Transmitting means for transmitting each of the pulse transmission signals generated by the transmitting means to a separate transmission path; receiving means for receiving the transmission data and the pulse transmission signal transmitted through the transmission path by the transmitting means; Frame pulse generating means for generating a second frame pulse having the same cycle as the first frame pulse from the pulse transmission signal received by the receiving means based on the transmission data received by the receiving means; The second frame pulse generated by the frame generating means is the first frame pulse. The same period discriminating means for discriminating whether or not the first and second frame pulses are not in the same cycle. A serial data monitoring device comprising: a transmission path error occurrence notifying means for notifying. 2. A pulse transmission signal generating means for generating a pulse transmission signal from first frame pulses indicating boundaries of respective frames based on transmission data framed in synchronization with a reference clock; Sending means for sending each of the pulse transmission signals generated by the pulse transmission signal generating means to a separate transmission path; and transmitting the transmission data and the pulse transmission signal transmitted via the transmission path by the transmission means. Receiving means for receiving, and a frame for generating a second frame pulse having the same cycle as the first frame pulse from the pulse transmission signal received by the receiving means based on the transmission data received by the receiving means Pulse generating means, and a second frame pulse generated by the frame generating means The same period discriminating means for judging whether or not the first frame pulse has the same cycle as the first frame pulse; and a transmission path when the same cycle discriminating means judges that the first and second frame pulses are not the same cycle. A transmission path error notifying unit for notifying the occurrence of an error and stopping the output of the second frame pulse; and a self-producing frame pulse having the same cycle as the first frame pulse based on the reference clock. Running frame pulse generating means; and frame pulse phase adjusting means for outputting the free running frame pulse generated by the free running frame pulse generating means in accordance with the phase of the second frame pulse generated by the frame pulse generating means. A serial data monitoring device comprising: 3. The frame generation means generates a third frame pulse having the same cycle as the first frame pulse from the pulse transmission signal based on the transmission data,
3. The serial data monitoring device according to claim 1, wherein the second frame pulse is generated by securing synchronization of the third frame pulse. 4. The frame pulse phase adjusting means, when the second frame pulse generated by the frame pulse generating means is not input within a predetermined period, stop outputting the self-running frame pulse. 3. The serial data monitoring device according to claim 2, wherein: 5. The pulse transmission signal is generated by performing an exclusive OR operation on the transmission data and the first frame pulse in bit units, and the second frame pulse is received by the receiving unit. 3. The serial data monitoring device according to claim 1, wherein the transmission data and the pulse transmission signal are generated by performing an exclusive OR operation on a bit-by-bit basis.