JP2624120B2 - Monitoring data replacement circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monitoring data replacement circuit capable of replacing monitoring data when new data is inserted into a main signal.

[0002]

2. Description of the Related Art In a synchronous terminal device, as shown in FIG.
One frame of the main signal is composed of N pieces of data. At this time, each data position in one frame is called a time slot. However, it is rare that all the time slots are used as a data area, and an empty time slot is set to transmit and receive additional information and line monitoring information. That is common. TS is a time slot (Time Slot).
t), and the subscript of TS indicates the number from the beginning of the frame.

As one of the line monitoring methods when the main signal takes two values of "0" or "1", one time slot for monitoring data is set in one frame, and one time slot is set on the transmission side. There is a method of calculating the sum of data of all time slots in a frame, inserting the parity bit into a monitoring data time slot of the next frame, and performing a parity check on the receiving side. Whether the parity is set to an even number or an odd number is determined in advance between transmission and reception.

Here, data is inserted into a specific time slot of the main signal between the time when the monitoring data is inserted at the transmission side, ie, the start point of the line monitoring section, and the time when the parity check is performed at the receiving side, ie, the end point of the line monitoring section. Consider a circuit that inserts and thereby replaces monitoring data. FIG. 2 shows an example of the configuration of the main signal in such a case. In this example,
The data insertion position is TS ₂ , and the monitoring data position is T
Is S _4, d _n is TS ₂ before insertion data, D _n is TS
₂ , f _n is monitoring data before inserting data into TS ₂ , and F _n is monitoring data replaced by inserting data into TS ₂ .

A conventional monitoring data replacement circuit is used for inserting data and replacing monitoring data when new data is inserted into a main signal in a line monitoring section.

FIG. 7 is a block diagram of a conventional monitoring data replacement circuit. For simplicity, the operation will be described for the case of the configuration of the main signal as shown in FIG.
The detection circuit 41 detects the monitoring data 31 of the TS ₄ from the input main signal 11 and supplies the same to the comparison circuit 43. The parity calculation circuit 42 calculates the sum of the data of all the time slots in one frame of the input main signal 11, obtains the parity bit, and supplies the parity calculation result 32 to the comparison circuit 43. The comparison circuit 43 outputs a comparison result 33 obtained by comparing the monitoring data 31 detected from the current frame with the parity calculation result 32 of the previous frame. The comparison result 33 is line monitoring information from the start point of the line monitoring section to the conventional monitoring data replacement circuit.

The parity calculation circuit 44 outputs the output main signal 21
, The sum of the data of all the time slots in one frame is calculated to obtain the parity bit, and the parity calculation result 3
4 to the insertion circuit 3. The insertion circuit 3 inserts the insertion data 2
0 is inserted into TS ₂ of the input main signal 11, and the parity calculation result 34 of the previous frame is inserted into TS ₄ of the input main signal 11 and output to 21. At this time, the TS ₂ of the main signal D _n is inserted in place of d _n, the TS ₄ F instead of f _n
n has been inserted, the data has been inserted, and the monitoring data has been replaced.

[0008]

In this conventional monitoring data replacement circuit, a parity bit is calculated by calculating the sum of data of all time slots in one frame for a main signal after data is inserted into a specific time slot. And insert it into the main signal as new monitoring data. In other words, the monitoring data is replaced in the same way as the start point of the line monitoring section even though it is in the middle of the line monitoring section, so the monitoring data is replaced without holding the line monitoring information from the start point to this data insertion point. I have.

For this reason, means for extracting line monitoring information from the start point to the insertion point at the data insertion point, such as the detection circuit 41, parity calculation circuit 42, and comparison circuit 4 in FIG.
3 is required. In addition, means for transmitting the extracted line monitoring information to the end point of the line monitoring section, for example, means for using an empty time slot of the main signal is required. At the end point, the line monitoring information from the data insertion point to the end point extracted by performing a parity check using the monitoring data of the main signal, and the line monitoring information from the start point to the data insertion point transmitted from the data insertion point. It is necessary to provide a means for determining the monitoring information of all the line monitoring sections in combination with the above. These three means are extra means unrelated to the original purpose of inserting new data and replacing monitoring data when new data is inserted into the main signal in the line monitoring section.

[0010] Accordingly, an object of the present invention is to provide a monitoring data replacement circuit capable of eliminating unnecessary means and reducing the circuit size in the entire line monitoring section.

[0011]

[0012]

According to the present invention, in order to solve the problems] In order to monitor the line, the sum of all the data in one frame is calculated, as with the next frame the parity bit as monitoring data In the line monitoring section for transmitting and receiving the main signal of the configuration, in the monitoring data replacement circuit for inserting data into the main signal and replacing the monitoring data, the main signal before data insertion is input and the monitoring data and the position where the data is to be inserted. A detection circuit that detects and outputs data before insertion, which is data, and a first exclusive OR circuit that inputs the insertion data and data before insertion, which is an output from the detection circuit, and outputs a difference between the data and A first delay circuit for receiving an output of the first exclusive-OR circuit and outputting the delayed output at a timing suitable for replacement of monitoring data of the next frame; and a fourth output circuit. A second exclusive-OR circuit that inputs the post-replacement monitoring data output from the logical OR circuit and the monitoring data output from the detection circuit and outputs the difference therebetween, and the second exclusive OR circuit A second delay circuit which receives an output of the circuit, sends the output at a timing suitable for replacement of monitoring data of the next frame, and outputs the second delay circuit; monitoring data which is an output from the detection circuit; and an output of the second delay circuit. And a third exclusive-OR circuit that outputs the sum and outputs the sum, and the output of the third exclusive-OR circuit and the output of the first delay circuit, and inputs the sum as post-replacement monitoring data. A fourth exclusive OR circuit to be output, a main signal and data before data insertion, and post-replacement monitoring data output from the fourth exclusive OR circuit are input and the inserted data is inserted at the data insertion position. Monitoring data position Monitoring data replacement circuit is obtained, characterized in that it comprises an insertion circuit for outputting after monitoring data by inserting replacement.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings.

First, a method of obtaining post-replacement monitoring data in the present invention will be described.

FIG. 2 shows an example of the configuration of a main signal using the present invention. As described above, TS is an abbreviation of Time Slot, and the subscript of TS indicates the number from the beginning of the frame. In this example, the position where data is inserted is TS ₂ , the position of monitoring data is TS ₄ ,
d _n is data before inserting TS ₂ , D _n is data inserted into TS ₂ , f _n is monitoring data before inserting data into TS ₂ , and F _n is replaced by inserting data into TS _2. Monitoring data. Now, I think to ask for F _2, to focus only on changes in the data of the previous frame. Cause replace the f ₂ in F ₂ is, d ₁ in the previous frame to D _1, only that f ₁ is replaced to F _1. Since the main signal is continuous, it causes the f ₁ is alternative to F _1, similar to replace with a f ₂ in F _2, is due to changes in the data of the previous frame. Since f ₂ is a parity bit sum may be determined by calculating the data of all the time slots of the previous frame, the seek F ₂ from f _2, what is removed from the data prior to insertion of the front frame What is necessary is just to find what is added to the previous frame after data insertion. Accordingly, it is found that the value obtained by subtracting d ₁ and f ₁ from f ₂ and adding D ₁ and F ₁ is F ₂ . That is, ΔF ₂ = f ₂ −
F ₂ can be obtained as d ₁ −f ₁ + D ₁ + F ₁ }. This When shown in the general formula with n F _n can be expressed by the following equation 1.

[0016]

[Number 1] _{F n = fn-d (n} -1) + D (n-1) -F (n-1)

By providing a circuit equivalent to the above equation (1), when new data is inserted into a main signal in a line monitoring section, a circuit which can replace monitoring data while retaining line monitoring information up to the insertion point is maintained. Will be provided.

Next, the operation of each section in the embodiment of the present invention will be described. FIG. 3 is a block diagram showing an embodiment of the present invention. For simplification of the drawing, the case where the data of one time slot of the main signal is one bit is shown. In general, the sum and difference of signals having two values of “0” or “1” can be obtained by an exclusive OR circuit. FIGS. 4, 5, and 6 are examples of waveform diagrams showing the operation of each unit in the embodiment of FIG. 3, and are waveform diagrams within the same time. In the waveform diagram, the portions other than the main signals TS ₂ and TS ₄ are not particularly relevant and are omitted, and the crosses of the other signals indicate data during the transition period and have no significance to the present invention. . Hereinafter, the description will be given assuming that the suffix of the currently focused frame is n.

In FIG. 3, the detection circuit 1 detects the monitoring data f _n from the input main signal 11 and outputs it to the output terminal 12, detects the pre-insertion data d _n and outputs it to the output terminal 13. Exclusive OR circuit 8 outputs the difference between the pre-insertion data d _n from the insertion data D _n and the output terminal 13 from the input terminal 20 (D _n -d _n) to an output terminal 18. Delay circuit 4
Outputs the data from the output terminal 18 to the output terminal 19 at a timing suitable for replacement of the monitoring data of the next frame.

The exclusive OR circuit 5 outputs the difference between the monitored data f _n from the replacement after the monitoring data D _n and the output terminal 12 from the output terminal 17 (F _n -f _n) to the output terminal 14. The delay circuit 2 outputs the data (F _n) from the output terminal 14.
−f _n ) is output to the output terminal 15 after being delayed to a timing suitable for replacement of monitoring data of the next frame. The exclusive OR circuit 6 calculates the sum ｛F _(n) of the difference between the monitoring data after the replacement of the previous frame from the output terminal 15 and the monitoring data of the previous frame and the monitoring data f _n of the current frame from the output terminal 12. _-1) -f _(n-1) + f _n } is output to the output terminal 16.

The exclusive OR circuit 7 calculates the sum ΔF _(n−1) of the data from the output terminal 16 and the difference between the data inserted from the output terminal 19 in the previous frame and the data before the previous frame.
−f _(n−1) + f _n + D _(n−1) −d _(n−1) ｝ is output terminal 1
7 is output. Insertion circuit 3 outputs to the output terminal 21 after monitoring data by inserting a replacement from inserting the insert data from the input terminal 20 to the TS ₂ TS ₄ to the output terminal 17. At this time, as can be seen from the waveform diagram, the output terminal 17
The monitoring data after the replacement satisfies the above equation (1).

Therefore, according to the present invention, in order to monitor a line, a main signal having a configuration in which the sum of all data in one frame is calculated and the parity bit is provided as monitoring data in the next frame is transmitted and received. In a case where new data is inserted into a main signal in a line monitoring section, a means for replacing monitoring data while retaining line monitoring information up to the data insertion point is provided.

[0023] In this embodiment, one frame of the number of time slots and the insertion position of the data TS ₂ and 10 T
Although S ₄ are the position of the monitoring data, even the number of time slots one frame in a number, clear that also an insertion position and which time slot position of the monitoring data of the data present invention is effective It is. In this embodiment, the data of one time slot is one bit. However, even if the main signal is serial data or parallel data, the circuits of the present invention are provided by the number of parity bits used as the monitoring data. Thus, it is clear that the present invention is effective.

[0024]

As described above, the monitoring data replacement circuit of the present invention can replace monitoring data while retaining line monitoring information up to the insertion point when inserting new data into a main signal. There are three extra means, which are necessary when using the conventional circuit, which are irrelevant to the original purpose, that is, means for extracting the line monitoring information from the starting point to the insertion point at the data insertion point, and the extracted line monitoring. Means for transmitting information to the end point of the line monitoring section, together with the line monitoring information from the data insertion point to the end point at the end point and the line monitoring information from the start point to the data insertion point transmitted from the data insertion point Since the means for judging as monitoring information of all the line monitoring sections can be unnecessary means, the circuit scale can be reduced in the entire line monitoring section. It can be.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of one frame of a main signal using the present invention.

FIG. 2 is a diagram showing a configuration example of a main signal using the present invention.

FIG. 3 is a block diagram showing an embodiment of the present invention.

FIG. 4 is an example of a waveform diagram for explaining the operation of each section in the embodiment of FIG. 3;

FIG. 5 is an example of a waveform diagram for explaining the operation of each unit in the embodiment of FIG. 3;

FIG. 6 is an example of a waveform diagram for explaining the operation of each section in the embodiment of FIG. 3;

FIG. 7 is a block diagram showing a conventional monitoring system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Detection circuit 2 Delay circuit 3 Insertion circuit 4 Delay circuit 5-8 Exclusive OR circuit 41 Detection circuit 42 Parity calculation circuit 43 Comparison circuit 44 Parity calculation circuit

Continuation of the front page (56) References JP-A-63-232721 (JP, A) JP-A-7-177132 (JP, A) JP-A-2-126743 (JP, A) JP-A-5-54698 (JP) JP-A-60-179849 (JP, A) JP-T-56-500549 (JP, A) IBM Technical DISCLOSURE BULLETIN, VOL. 34, NO. 10A, (MARCH 1992), PP. 34-38 IBM JOURNAL OF RESEARCH AND DEVELOP MENT, VOL. 33, NO. 6 (NO VEMBER 1989), PP. 618-626

Claims (1)

(57) [Claims] 1. A line monitoring section for calculating a sum of all data in one frame to monitor a line and transmitting / receiving a main signal having a parity bit as monitoring data in a next frame. In the monitoring data change circuit that inserts data into the main signal and changes the monitoring data, the main signal before data insertion is input and monitored
The data and the data where the data will be inserted
A detection circuit for detecting and outputting data before insertion, and
Data before insertion, which is the output from the detection circuit.
A first exclusive OR circuit that inputs and outputs the difference,
The output of the first exclusive OR circuit is input and the next frame is input.
The timing suitable for replacing monitoring data
Delay circuit and fourth exclusive OR circuit
From the monitoring data after replacement, which is the output of
Of monitoring data, which is the output of
Two exclusive OR circuits, and the second exclusive OR circuit
Input to output the monitoring data of the next frame
Second delay circuit for sending and outputting at an appropriate timing
Monitoring data which is an output from the detection circuit;
And outputs the sum of the outputs of the second and third delay circuits.
An exclusive-OR circuit and an output of the third exclusive-OR circuit.
And input the output of the first delay circuit and sum the
Fourth exclusive-OR output as monitoring data after replacement
Path, the main signal before data insertion, the inserted data, and the fourth
Monitor data after replacement, which is the output of the exclusive OR circuit
Input and insert insertion data at data insertion position and monitor data
Insertion times for inserting and outputting monitoring data after repositioning
Monitoring data replacement circuit, characterized in that it comprises a road.