ITVA20020067A1 - Dispositivo di memoria composto da piu' memorie in un unico package. - Google Patents
Dispositivo di memoria composto da piu' memorie in un unico package.Info
- Publication number
- ITVA20020067A1 ITVA20020067A1 IT000067A ITVA20020067A ITVA20020067A1 IT VA20020067 A1 ITVA20020067 A1 IT VA20020067A1 IT 000067 A IT000067 A IT 000067A IT VA20020067 A ITVA20020067 A IT VA20020067A IT VA20020067 A1 ITVA20020067 A1 IT VA20020067A1
- Authority
- IT
- Italy
- Prior art keywords
- memory device
- single package
- device composed
- multiple memories
- memories
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/105—Aspects related to pads, pins or terminals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT000067A ITVA20020067A1 (it) | 2002-12-04 | 2002-12-04 | Dispositivo di memoria composto da piu' memorie in un unico package. |
| US10/727,150 US6950324B2 (en) | 2002-12-04 | 2003-12-03 | Memory device composed of a plurality of memory chips in a single package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT000067A ITVA20020067A1 (it) | 2002-12-04 | 2002-12-04 | Dispositivo di memoria composto da piu' memorie in un unico package. |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| ITVA20020067A0 ITVA20020067A0 (it) | 2002-12-04 |
| ITVA20020067A1 true ITVA20020067A1 (it) | 2004-06-05 |
Family
ID=27621276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT000067A ITVA20020067A1 (it) | 2002-12-04 | 2002-12-04 | Dispositivo di memoria composto da piu' memorie in un unico package. |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6950324B2 (it) |
| IT (1) | ITVA20020067A1 (it) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100697270B1 (ko) * | 2004-12-10 | 2007-03-21 | 삼성전자주식회사 | 저전력 멀티칩 반도체 메모리 장치 및 그것의 칩 인에이블방법 |
| US7190604B2 (en) * | 2005-06-27 | 2007-03-13 | Lyontek Inc. | Capacity dividable memory IC |
| US8400870B2 (en) | 2011-01-04 | 2013-03-19 | Winbond Electronics Corp. | Memory devices and accessing methods thereof |
| EP2482284A1 (en) * | 2011-01-27 | 2012-08-01 | Winbond Electronics Corp. | Memory devices and accessing methods thereof |
| TWI489477B (zh) * | 2011-03-07 | 2015-06-21 | Winbond Electronics Corp | 記憶體裝置以及其存取方法 |
| CN102681943B (zh) * | 2011-03-16 | 2015-07-08 | 华邦电子股份有限公司 | 内存装置以及其存取方法 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5524231A (en) * | 1993-06-30 | 1996-06-04 | Intel Corporation | Nonvolatile memory card with an address table and an address translation logic for mapping out defective blocks within the memory card |
| KR100355032B1 (ko) * | 2001-01-08 | 2002-10-05 | 삼성전자 주식회사 | 고집적 패키지 메모리 장치, 이 장치를 이용한 메모리 모듈, 및 이 모듈의 제어방법 |
-
2002
- 2002-12-04 IT IT000067A patent/ITVA20020067A1/it unknown
-
2003
- 2003-12-03 US US10/727,150 patent/US6950324B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| ITVA20020067A0 (it) | 2002-12-04 |
| US6950324B2 (en) | 2005-09-27 |
| US20040136218A1 (en) | 2004-07-15 |
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