ITRM910621A0 - Procedimento per la fabbricazione di transistori con struttura gate -isolante -semiconduttore. - Google Patents

Procedimento per la fabbricazione di transistori con struttura gate -isolante -semiconduttore.

Info

Publication number
ITRM910621A0
ITRM910621A0 IT91RM621A ITRM910621A ITRM910621A0 IT RM910621 A0 ITRM910621 A0 IT RM910621A0 IT 91RM621 A IT91RM621 A IT 91RM621A IT RM910621 A ITRM910621 A IT RM910621A IT RM910621 A0 ITRM910621 A0 IT RM910621A0
Authority
IT
Italy
Prior art keywords
insulator
transistors
gate
procedure
manufacture
Prior art date
Application number
IT91RM621A
Other languages
English (en)
Inventor
Kyoung-Tae Kim
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITRM910621A0 publication Critical patent/ITRM910621A0/it
Publication of ITRM910621A1 publication Critical patent/ITRM910621A1/it
Application granted granted Critical
Publication of IT1250463B publication Critical patent/IT1250463B/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
ITRM910621A 1990-08-20 1991-08-19 Procedimento per la fabbricazione di transistori con struttura gate -isolante -semiconduttore. IT1250463B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900012815A KR920005242A (ko) 1990-08-20 1990-08-20 게이트-절연체-반도체의 구조를 가지는 트랜지스터의 제조방법

Publications (3)

Publication Number Publication Date
ITRM910621A0 true ITRM910621A0 (it) 1991-08-19
ITRM910621A1 ITRM910621A1 (it) 1993-02-19
IT1250463B IT1250463B (it) 1995-04-07

Family

ID=19302524

Family Applications (1)

Application Number Title Priority Date Filing Date
ITRM910621A IT1250463B (it) 1990-08-20 1991-08-19 Procedimento per la fabbricazione di transistori con struttura gate -isolante -semiconduttore.

Country Status (5)

Country Link
KR (1) KR920005242A (it)
DE (1) DE4114166A1 (it)
FR (1) FR2665980A1 (it)
GB (1) GB2247349A (it)
IT (1) IT1250463B (it)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0614226A1 (en) * 1992-10-05 1994-09-07 Texas Instruments Incorporated Gate electrode using stacked layers of TiN and polysilicon
US6084279A (en) * 1997-03-31 2000-07-04 Motorola Inc. Semiconductor device having a metal containing layer overlying a gate dielectric
KR100345364B1 (ko) * 1998-12-28 2002-09-18 주식회사 하이닉스반도체 반도체 소자의 게이트전극 형성방법
JP3287403B2 (ja) * 1999-02-19 2002-06-04 日本電気株式会社 Mis型電界効果トランジスタ及びその製造方法
AU6918300A (en) * 1999-09-24 2001-04-30 Intel Corporation A nonvolatile memory device with a high work function floating-gate and method of fabrication
US6518618B1 (en) 1999-12-03 2003-02-11 Intel Corporation Integrated memory cell and method of fabrication
US6388327B1 (en) 2001-01-09 2002-05-14 International Business Machines Corporation Capping layer for improved silicide formation in narrow semiconductor structures
CN1296971C (zh) * 2004-09-29 2007-01-24 中国科学院微电子研究所 一种适用于纳米器件制造的硅化物工艺

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3879746A (en) * 1972-05-30 1975-04-22 Bell Telephone Labor Inc Gate metallization structure
JPS57155775A (en) * 1981-03-23 1982-09-25 Hitachi Ltd Semiconductor device
JPS5925273A (ja) * 1982-08-03 1984-02-09 Toshiba Corp 半導体装置及びその製造方法
US4605947A (en) * 1983-03-07 1986-08-12 Motorola Inc. Titanium nitride MOS device gate electrode and method of producing
US4570328A (en) * 1983-03-07 1986-02-18 Motorola, Inc. Method of producing titanium nitride MOS device gate electrode
JPH065733B2 (ja) * 1984-08-27 1994-01-19 アメリカン テレフオン アンド テレグラフ カムパニ− 集積回路デバイスおよびその製造方法
GB2164491B (en) * 1984-09-14 1988-04-07 Stc Plc Semiconductor devices
JPS61208869A (ja) * 1985-03-14 1986-09-17 Nec Corp 半導体装置及びその製造方法
DE3650170T2 (de) * 1985-05-13 1995-05-18 Toshiba Kawasaki Kk Halbleiteranordnung mit Verbindungselektroden.
JPS6254960A (ja) * 1985-09-04 1987-03-10 Nec Corp Mis形電界効果トランジスタ
US4707721A (en) * 1986-02-20 1987-11-17 Texas Instruments Incorporated Passivated dual dielectric gate system and method for fabricating same
JPS62219966A (ja) * 1986-03-22 1987-09-28 Toshiba Corp 半導体装置
JPS63174371A (ja) * 1987-01-13 1988-07-18 Nec Corp 電界効果トランジスタ
JPH07109824B2 (ja) * 1987-07-22 1995-11-22 松下電子工業株式会社 半導体装置の製造方法
US4990997A (en) * 1988-04-20 1991-02-05 Fujitsu Limited Crystal grain diffusion barrier structure for a semiconductor device
JPH0228377A (ja) * 1988-06-09 1990-01-30 Fujitsu Ltd 半導体装置、電界効果トランジスタ、および、キャパシタの製造方法
JPH0687501B2 (ja) * 1988-09-29 1994-11-02 シャープ株式会社 半導体装置のゲート電極の製造方法

Also Published As

Publication number Publication date
FR2665980A1 (fr) 1992-02-21
GB9117195D0 (en) 1991-09-25
ITRM910621A1 (it) 1993-02-19
DE4114166A1 (de) 1992-02-27
KR920005242A (ko) 1992-03-28
IT1250463B (it) 1995-04-07
GB2247349A (en) 1992-02-26

Similar Documents

Publication Publication Date Title
IT8723134A0 (it) Procedimento per la fabbricazione di dispositivi integrati cmos con lunghezze di porta ridotte.
FI891767A0 (fi) Foerfarande foer framstaellning av en ljusvaogledare.
FI871789A (fi) Anordning foer uppspaerrning av saor.
DE69110480D1 (de) Verbesserter halbleiter-microanemometer.
FI913048A (fi) Bicykliska heterocykliska foereningar.
NO912346D0 (no) Fremgangsmaate for fremstilling av aminobenzodiazepiner.
DE3887716T2 (de) Transistor.
ITMI912655A1 (it) Combinazione di estrusore-calandra.
ITTO910643A1 (it) Procedimento di galvanostegia.
FI900688A0 (fi) Anordning foer luftning av liggunderlag i sjuksaeng.
ITRM910621A0 (it) Procedimento per la fabbricazione di transistori con struttura gate -isolante -semiconduttore.
FI904676A0 (fi) Anordning foer loesgoerande av manteln i en haeftapparat.
ITRM930758A1 (it) Procedimento per la produzione di policarbonati.
IT9012441A0 (it) Procedimento per la fabbricazione di strutture sandwich
ITRM930141A0 (it) Procedimento per la produzione di perfluoroalchilsolfonilfloruri.
IT1238301B (it) Procedimento per la realizzazione di calzature e calzatura ottenuta con tale procedimento.
ITRM930808A1 (it) Procedimento per la produzione di policarbonati.
FI913285A0 (fi) Svavelsubstituerade mevinsyraderivat.
ITRM930445A0 (it) Procedimento per la produzione di policarbonati.
IT1241025B (it) Procedimento per la purificazione di bagni di nichelatura.
FI880733A (fi) Anordning foer uppbaerning av solv- eller rittgarn i en vaevstol.
TR24863A (tr) ALKALIFOSFAT CÖZELTILERININ üRETILMESINE MAHSUS USUL.
FI901382A0 (fi) Anordning foer foerminskande av antalet parallella roekspjaellmodeller.
IT9020275A0 (it) Procedimento per la fabbricazione di 7-dimetilamino-6-demetil-6- deossitetraciclina
FI894354A (fi) Formanordning foer bildande av ett vattenavledningsspaor i asfaltkanten.

Legal Events

Date Code Title Description
0001 Granted