ITMI20031932A1 - Circuiti e procedimenti per fornire operazione di modalita' di pagina in dispositivo di memoria a semicondutture avente architettura ad attivazione parziale - Google Patents
Circuiti e procedimenti per fornire operazione di modalita' di pagina in dispositivo di memoria a semicondutture avente architettura ad attivazione parzialeInfo
- Publication number
- ITMI20031932A1 ITMI20031932A1 IT001932A ITMI20031932A ITMI20031932A1 IT MI20031932 A1 ITMI20031932 A1 IT MI20031932A1 IT 001932 A IT001932 A IT 001932A IT MI20031932 A ITMI20031932 A IT MI20031932A IT MI20031932 A1 ITMI20031932 A1 IT MI20031932A1
- Authority
- IT
- Italy
- Prior art keywords
- semiconducture
- architecture
- procedures
- circuits
- memory device
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
- G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0061042A KR100510491B1 (ko) | 2002-10-07 | 2002-10-07 | 부분 활성화 구조를 가지고 페이지 모드 동작이 가능한반도체 메모리 장치 및 그 동작 방법 |
| US10/640,146 US6826115B2 (en) | 2002-10-07 | 2003-08-13 | Circuits and methods for providing page mode operation in semiconductor memory device having partial activation architecture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ITMI20031932A1 true ITMI20031932A1 (it) | 2004-04-08 |
Family
ID=32040988
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT001932A ITMI20031932A1 (it) | 2002-10-07 | 2003-10-07 | Circuiti e procedimenti per fornire operazione di modalita' di pagina in dispositivo di memoria a semicondutture avente architettura ad attivazione parziale |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6826115B2 (it) |
| KR (1) | KR100510491B1 (it) |
| IT (1) | ITMI20031932A1 (it) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10339665B3 (de) * | 2003-08-28 | 2005-01-13 | Infineon Technologies Ag | Halbleiter-Speicherbauelement, mit Steuereinrichtung zum Aktivieren von Speicherzellen und Verfahren zum Betrieb eines Halbleiter-Speicherbauelements |
| JP5044153B2 (ja) * | 2005-09-29 | 2012-10-10 | エスケーハイニックス株式会社 | 同期式半導体メモリ素子のカラムアドレスイネーブル信号生成器及びその生成方法 |
| US7408832B2 (en) * | 2006-03-21 | 2008-08-05 | Mediatek Inc. | Memory control method and apparatuses |
| KR20110040538A (ko) * | 2009-10-14 | 2011-04-20 | 삼성전자주식회사 | 레이턴시 회로 및 이를 포함하는 반도체 장치 |
| KR20160074920A (ko) * | 2014-12-19 | 2016-06-29 | 에스케이하이닉스 주식회사 | 메모리 장치 |
| KR102573131B1 (ko) * | 2016-07-04 | 2023-09-01 | 에스케이하이닉스 주식회사 | 고속 데이터 전송을 위한 메모리 장치 |
| US10162406B1 (en) * | 2017-08-31 | 2018-12-25 | Micron Technology, Inc. | Systems and methods for frequency mode detection and implementation |
| KR102549540B1 (ko) * | 2017-09-22 | 2023-06-29 | 삼성전자주식회사 | 스토리지 장치 및 그 동작 방법 |
| US10332586B1 (en) * | 2017-12-19 | 2019-06-25 | Micron Technology, Inc. | Apparatuses and methods for subrow addressing |
| KR102653529B1 (ko) * | 2018-10-22 | 2024-04-02 | 에스케이하이닉스 주식회사 | 반도체장치 및 반도체시스템 |
| US10817420B2 (en) * | 2018-10-30 | 2020-10-27 | Arm Limited | Apparatus and method to access a memory location |
| US11670349B2 (en) | 2021-03-31 | 2023-06-06 | Changxin Memory Technologies, Inc. | Memory circuit, memory precharge control method and device |
| US11705167B2 (en) * | 2021-03-31 | 2023-07-18 | Changxin Memory Technologies, Inc. | Memory circuit, method and device for controlling pre-charging of memory |
| CN117153215B (zh) * | 2023-10-26 | 2024-01-23 | 长鑫存储技术有限公司 | 一种控制电路和存储器 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5159676A (en) * | 1988-12-05 | 1992-10-27 | Micron Technology, Inc. | Semi-smart DRAM controller IC to provide a pseudo-cache mode of operation using standard page mode draws |
| JPH07248963A (ja) * | 1994-03-08 | 1995-09-26 | Nec Corp | Ｄｒａｍ制御装置 |
| US5640364A (en) | 1994-12-23 | 1997-06-17 | Micron Technology, Inc. | Self-enabling pulse trapping circuit |
| US5729504A (en) | 1995-12-14 | 1998-03-17 | Micron Technology, Inc. | Continuous burst edo memory device |
| US5966724A (en) | 1996-01-11 | 1999-10-12 | Micron Technology, Inc. | Synchronous memory device with dual page and burst mode operations |
| US6094398A (en) * | 1996-09-30 | 2000-07-25 | Siemens Aktiengesellschaft | DRAM including an address space divided into individual blocks having memory cells activated by row address signals |
| US6044429A (en) * | 1997-07-10 | 2000-03-28 | Micron Technology, Inc. | Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths |
| US6128716A (en) * | 1998-01-23 | 2000-10-03 | Motorola Inc. | Memory controller with continuous page mode and method therefor |
| JP2000067582A (ja) * | 1998-08-14 | 2000-03-03 | Texas Instr Inc <Ti> | メモリシステムおよび電子装置の動作方法 |
| JP4043151B2 (ja) | 1998-08-26 | 2008-02-06 | 富士通株式会社 | 高速ランダムアクセス可能なメモリデバイス |
| KR100523180B1 (ko) * | 1998-08-26 | 2005-10-24 | 후지쯔 가부시끼가이샤 | 고속 랜덤 액세스 가능한 메모리 장치 |
-
2002
- 2002-10-07 KR KR10-2002-0061042A patent/KR100510491B1/ko active IP Right Grant
-
2003
- 2003-08-13 US US10/640,146 patent/US6826115B2/en not_active Expired - Lifetime
- 2003-10-07 IT IT001932A patent/ITMI20031932A1/it unknown
Also Published As
| Publication number | Publication date |
|---|---|
| KR100510491B1 (ko) | 2005-08-26 |
| US20040066700A1 (en) | 2004-04-08 |
| US6826115B2 (en) | 2004-11-30 |
| KR20040031903A (ko) | 2004-04-14 |
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