ITMI20011311A0 - Memoria con sistema di lettura differenziale perfezionato - Google Patents

Memoria con sistema di lettura differenziale perfezionato

Info

Publication number
ITMI20011311A0
ITMI20011311A0 IT2001MI001311A ITMI20011311A ITMI20011311A0 IT MI20011311 A0 ITMI20011311 A0 IT MI20011311A0 IT 2001MI001311 A IT2001MI001311 A IT 2001MI001311A IT MI20011311 A ITMI20011311 A IT MI20011311A IT MI20011311 A0 ITMI20011311 A0 IT MI20011311A0
Authority
IT
Italy
Prior art keywords
memory
reading system
improved differential
differential reading
improved
Prior art date
Application number
IT2001MI001311A
Other languages
English (en)
Inventor
Luigi Pascucci
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT2001MI001311A priority Critical patent/ITMI20011311A1/it
Publication of ITMI20011311A0 publication Critical patent/ITMI20011311A0/it
Priority to US10/176,954 priority patent/US6700819B2/en
Publication of ITMI20011311A1 publication Critical patent/ITMI20011311A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
IT2001MI001311A 2001-06-21 2001-06-21 Memoria con sistema di lettura differenziale perfezionato ITMI20011311A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT2001MI001311A ITMI20011311A1 (it) 2001-06-21 2001-06-21 Memoria con sistema di lettura differenziale perfezionato
US10/176,954 US6700819B2 (en) 2001-06-21 2002-06-20 Memory with improved differential reading system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2001MI001311A ITMI20011311A1 (it) 2001-06-21 2001-06-21 Memoria con sistema di lettura differenziale perfezionato

Publications (2)

Publication Number Publication Date
ITMI20011311A0 true ITMI20011311A0 (it) 2001-06-21
ITMI20011311A1 ITMI20011311A1 (it) 2002-12-21

Family

ID=11447914

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2001MI001311A ITMI20011311A1 (it) 2001-06-21 2001-06-21 Memoria con sistema di lettura differenziale perfezionato

Country Status (2)

Country Link
US (1) US6700819B2 (it)
IT (1) ITMI20011311A1 (it)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6967876B2 (en) * 2003-08-28 2005-11-22 Stmicroelectronics S.R.L. Method for controlling programming voltage levels of non-volatile memory cells, the method tracking the cell features, and corresponding voltage regulator
DE602004003465D1 (de) * 2004-02-19 2007-01-11 St Microelectronics Sa Abfühlschaltung mit regulierter Referenzspannung
JP4554613B2 (ja) * 2004-07-30 2010-09-29 Ｓｐａｎｓｉｏｎ Ｊａｐａｎ株式会社 半導体装置および半導体装置にデータを書き込む方法
EP1699054A1 (en) * 2005-03-03 2006-09-06 STMicroelectronics S.r.l. A memory device with a ramp-like voltage biasing structure and reduced number of reference cells
US7379365B2 (en) * 2006-07-26 2008-05-27 Micron Technology, Inc. Method and apparatus for charging large capacitances
ITMI20062211A1 (it) * 2006-11-17 2008-05-18 St Microelectronics Srl Circuito e metodo per generare una tensione di riferimento in dispositivi di memoria a matrice di celle non volatili
US9543017B2 (en) * 2012-03-18 2017-01-10 Cypress Semiconductors Ltd. End-of-life reliability for non-volatile memory cells
DE102015205944B4 (de) * 2015-03-30 2021-02-18 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Anordnung elektrochemischer Zellen mit Dichtungslagen sowie deren Verwendung
US10726895B1 (en) 2019-01-07 2020-07-28 International Business Machines Corporation Circuit methodology for differential weight reading in resistive processing unit devices
US11823739B2 (en) * 2020-04-06 2023-11-21 Crossbar, Inc. Physically unclonable function (PUF) generation involving high side programming of bits
US11727986B2 (en) * 2020-04-06 2023-08-15 Crossbar, Inc. Physically unclonable function (PUF) generation involving programming of marginal bits
US11423984B2 (en) 2020-04-06 2022-08-23 Crossbar, Inc. Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1221780B (it) * 1988-01-29 1990-07-12 Sgs Thomson Microelectronics Circuito di rilevamento dello stato di celle di matrice in memorie eprom in tecnologia mos
IT1246241B (it) * 1990-02-23 1994-11-17 Sgs Thomson Microelectronics Circuito per la lettura dell'informazione contenuta in celle di memoria non volatili
JP3454520B2 (ja) * 1990-11-30 2003-10-06 インテル・コーポレーション フラッシュ記憶装置の書込み状態を確認する回路及びその方法
IT1246754B (it) * 1990-12-28 1994-11-26 Sgs Thomson Microelectronics Circuito di lettura di celle eprom

Also Published As

Publication number Publication date
US6700819B2 (en) 2004-03-02
ITMI20011311A1 (it) 2002-12-21
US20030016572A1 (en) 2003-01-23

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