DE60133021D1 - Speicheranordnung - Google Patents

Speicheranordnung

Info

Publication number
DE60133021D1
DE60133021D1 DE60133021T DE60133021T DE60133021D1 DE 60133021 D1 DE60133021 D1 DE 60133021D1 DE 60133021 T DE60133021 T DE 60133021T DE 60133021 T DE60133021 T DE 60133021T DE 60133021 D1 DE60133021 D1 DE 60133021D1
Authority
DE
Germany
Prior art keywords
memory array
array
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60133021T
Other languages
English (en)
Inventor
Salvatore Polizzi
Maurizio Perroni
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE60133021D1 publication Critical patent/DE60133021D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation
DE60133021T 2001-12-20 2001-12-20 Speicheranordnung Expired - Lifetime DE60133021D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP01830782A EP1324346B1 (de) 2001-12-20 2001-12-20 Speicheranordnung

Publications (1)

Publication Number Publication Date
DE60133021D1 true DE60133021D1 (de) 2008-04-10

Family

ID=8184822

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60133021T Expired - Lifetime DE60133021D1 (de) 2001-12-20 2001-12-20 Speicheranordnung

Country Status (3)

Country Link
US (1) US6990596B2 (de)
EP (1) EP1324346B1 (de)
DE (1) DE60133021D1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7173469B1 (en) * 2002-01-24 2007-02-06 Cypress Semiconductor Corp. Clocking system and method for a memory
KR100948069B1 (ko) * 2008-09-10 2010-03-16 주식회사 하이닉스반도체 데이터 출력 회로
US9582441B2 (en) * 2014-02-27 2017-02-28 Infineon Technologies Ag Clockless serial slave device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2519580B2 (ja) * 1990-06-19 1996-07-31 三菱電機株式会社 半導体集積回路
US5991841A (en) * 1997-09-24 1999-11-23 Intel Corporation Memory transactions on a low pin count bus
KR100265599B1 (ko) * 1997-12-31 2000-10-02 김영환 데이터 윈도우 제어장치 및 그 방법
JP3349943B2 (ja) * 1998-03-03 2002-11-25 日本電気株式会社 半導体装置
JP2000057771A (ja) * 1998-08-05 2000-02-25 Mitsubishi Electric Corp 半導体記憶装置
JP2002230972A (ja) * 2001-02-06 2002-08-16 Mitsubishi Electric Corp 同期型半導体記憶装置
US6763444B2 (en) * 2001-05-08 2004-07-13 Micron Technology, Inc. Read/write timing calibration of a memory array using a row or a redundant row

Also Published As

Publication number Publication date
US6990596B2 (en) 2006-01-24
EP1324346B1 (de) 2008-02-27
US20030123306A1 (en) 2003-07-03
EP1324346A1 (de) 2003-07-02

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Legal Events

Date Code Title Description
8332 No legal effect for de