IT1316025B1 - Sistema di integrazione di dispositivi di memoria e logici. - Google Patents

Sistema di integrazione di dispositivi di memoria e logici.

Info

Publication number
IT1316025B1
IT1316025B1 IT2000RM000671A ITRM20000671A IT1316025B1 IT 1316025 B1 IT1316025 B1 IT 1316025B1 IT 2000RM000671 A IT2000RM000671 A IT 2000RM000671A IT RM20000671 A ITRM20000671 A IT RM20000671A IT 1316025 B1 IT1316025 B1 IT 1316025B1
Authority
IT
Italy
Prior art keywords
memory
logic devices
integration system
integration
logic
Prior art date
Application number
IT2000RM000671A
Other languages
English (en)
Inventor
Mario Fazio
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to IT2000RM000671A priority Critical patent/IT1316025B1/it
Publication of ITRM20000671A0 publication Critical patent/ITRM20000671A0/it
Priority to US09/940,259 priority patent/US7102906B2/en
Publication of ITRM20000671A1 publication Critical patent/ITRM20000671A1/it
Application granted granted Critical
Publication of IT1316025B1 publication Critical patent/IT1316025B1/it
Priority to US11/487,670 priority patent/US20060259647A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
IT2000RM000671A 2000-12-15 2000-12-15 Sistema di integrazione di dispositivi di memoria e logici. IT1316025B1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT2000RM000671A IT1316025B1 (it) 2000-12-15 2000-12-15 Sistema di integrazione di dispositivi di memoria e logici.
US09/940,259 US7102906B2 (en) 2000-12-15 2001-08-27 Logic and memory device integration
US11/487,670 US20060259647A1 (en) 2000-12-15 2006-07-17 Logic and memory device integration

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2000RM000671A IT1316025B1 (it) 2000-12-15 2000-12-15 Sistema di integrazione di dispositivi di memoria e logici.

Publications (3)

Publication Number Publication Date
ITRM20000671A0 ITRM20000671A0 (it) 2000-12-15
ITRM20000671A1 ITRM20000671A1 (it) 2002-06-15
IT1316025B1 true IT1316025B1 (it) 2003-03-26

Family

ID=11455059

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2000RM000671A IT1316025B1 (it) 2000-12-15 2000-12-15 Sistema di integrazione di dispositivi di memoria e logici.

Country Status (2)

Country Link
US (2) US7102906B2 (it)
IT (1) IT1316025B1 (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3123616B1 (en) * 2014-03-24 2018-08-22 Telefonaktiebolaget LM Ericsson (publ) Receiver front end arrangement, multi-band receiver and base station
CN107112049A (zh) * 2014-12-23 2017-08-29 3B技术公司 采用薄膜晶体管的三维集成电路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993006549A1 (en) * 1991-09-19 1993-04-01 Chips And Technologies, Inc. A system for performing input and output operations to and from a processor
US5649162A (en) * 1993-05-24 1997-07-15 Micron Electronics, Inc. Local bus interface
GB9419246D0 (en) * 1994-09-23 1994-11-09 Cambridge Consultants Data processing circuits and interfaces
US5611075A (en) * 1994-10-04 1997-03-11 Analog Devices, Inc. Bus architecture for digital signal processor allowing time multiplexed access to memory banks
US6128700A (en) * 1995-05-17 2000-10-03 Monolithic System Technology, Inc. System utilizing a DRAM array as a next level cache memory and method for operating same
US5664140A (en) * 1995-05-19 1997-09-02 Micron Electronics, Inc. Processor to memory interface logic for use in a computer system using a multiplexed memory address
US6112019A (en) * 1995-06-12 2000-08-29 Georgia Tech Research Corp. Distributed instruction queue
US5930185A (en) * 1997-09-26 1999-07-27 Advanced Micro Devices, Inc. Data retention test for static memory cell
US6298426B1 (en) * 1997-12-31 2001-10-02 Intel Corporation Controller configurable for use with multiple memory organizations

Also Published As

Publication number Publication date
US7102906B2 (en) 2006-09-05
US20060259647A1 (en) 2006-11-16
ITRM20000671A0 (it) 2000-12-15
US20020078278A1 (en) 2002-06-20
ITRM20000671A1 (it) 2002-06-15

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