IT987426B - Procedimento perfezionato per la fabbricazione di dispositivi semi conduttori - Google Patents
Procedimento perfezionato per la fabbricazione di dispositivi semi conduttoriInfo
- Publication number
- IT987426B IT987426B IT24074/73A IT2407473A IT987426B IT 987426 B IT987426 B IT 987426B IT 24074/73 A IT24074/73 A IT 24074/73A IT 2407473 A IT2407473 A IT 2407473A IT 987426 B IT987426 B IT 987426B
- Authority
- IT
- Italy
- Prior art keywords
- semi
- manufacture
- conductive devices
- perfected procedure
- perfected
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US26777172A | 1972-06-30 | 1972-06-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
IT987426B true IT987426B (it) | 1975-02-20 |
Family
ID=23020055
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT24074/73A IT987426B (it) | 1972-06-30 | 1973-05-15 | Procedimento perfezionato per la fabbricazione di dispositivi semi conduttori |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPS528229B2 (en。) |
CA (1) | CA1005925A (en。) |
DE (1) | DE2318912A1 (en。) |
FR (1) | FR2191270B1 (en。) |
GB (1) | GB1422586A (en。) |
IT (1) | IT987426B (en。) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2554450A1 (de) * | 1975-12-03 | 1977-06-16 | Siemens Ag | Verfahren zur herstellung einer integrierten schaltung |
DE2720533A1 (de) * | 1977-05-06 | 1978-11-09 | Siemens Ag | Monolithisch integrierte schaltungsanordnung mit ein-transistor- speicherelementen |
CA1186808A (en) * | 1981-11-06 | 1985-05-07 | Sidney I. Soclof | Method of fabrication of dielectrically isolated cmos device with an isolated slot |
JPS58100441A (ja) * | 1981-12-10 | 1983-06-15 | Toshiba Corp | 半導体装置の製造方法 |
JPS58212165A (ja) * | 1983-05-23 | 1983-12-09 | Nec Corp | 半導体装置 |
JPH0616549B2 (ja) * | 1984-04-17 | 1994-03-02 | 三菱電機株式会社 | 半導体集積回路装置 |
JP2003124514A (ja) * | 2001-10-17 | 2003-04-25 | Sony Corp | 半導体発光素子及びその製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL153374B (nl) * | 1966-10-05 | 1977-05-16 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze. |
FR2080849A6 (en。) * | 1970-02-06 | 1971-11-26 | Radiotechnique Compelec | |
US3698966A (en) * | 1970-02-26 | 1972-10-17 | North American Rockwell | Processes using a masking layer for producing field effect devices having oxide isolation |
US3859717A (en) * | 1970-12-21 | 1975-01-14 | Rockwell International Corp | Method of manufacturing control electrodes for charge coupled circuits and the like |
US3751722A (en) * | 1971-04-30 | 1973-08-07 | Standard Microsyst Smc | Mos integrated circuit with substrate containing selectively formed resistivity regions |
-
1973
- 1973-04-14 DE DE2318912A patent/DE2318912A1/de not_active Ceased
- 1973-05-15 IT IT24074/73A patent/IT987426B/it active
- 1973-05-18 JP JP48054847A patent/JPS528229B2/ja not_active Expired
- 1973-06-01 GB GB2620873A patent/GB1422586A/en not_active Expired
- 1973-06-04 CA CA173,051A patent/CA1005925A/en not_active Expired
- 1973-06-06 FR FR7321783A patent/FR2191270B1/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
GB1422586A (en) | 1976-01-28 |
FR2191270B1 (en。) | 1977-07-29 |
JPS4945688A (en。) | 1974-05-01 |
CA1005925A (en) | 1977-02-22 |
JPS528229B2 (en。) | 1977-03-08 |
FR2191270A1 (en。) | 1974-02-01 |
DE2318912A1 (de) | 1974-01-17 |
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