IT983948B - Metodo per la fabbricazione di strutture a circuito integrato e struttura risultante - Google Patents

Metodo per la fabbricazione di strutture a circuito integrato e struttura risultante

Info

Publication number
IT983948B
IT983948B IT23102/73A IT2310273A IT983948B IT 983948 B IT983948 B IT 983948B IT 23102/73 A IT23102/73 A IT 23102/73A IT 2310273 A IT2310273 A IT 2310273A IT 983948 B IT983948 B IT 983948B
Authority
IT
Italy
Prior art keywords
manufacture
integrated circuit
resulting structure
circuit structures
structures
Prior art date
Application number
IT23102/73A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT983948B publication Critical patent/IT983948B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
    • H01L27/0826—Combination of vertical complementary transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/037—Diffusion-deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
IT23102/73A 1972-06-19 1973-04-17 Metodo per la fabbricazione di strutture a circuito integrato e struttura risultante IT983948B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US263881A US3861968A (en) 1972-06-19 1972-06-19 Method of fabricating integrated circuit device structure with complementary elements utilizing selective thermal oxidation and selective epitaxial deposition

Publications (1)

Publication Number Publication Date
IT983948B true IT983948B (it) 1974-11-11

Family

ID=23003639

Family Applications (1)

Application Number Title Priority Date Filing Date
IT23102/73A IT983948B (it) 1972-06-19 1973-04-17 Metodo per la fabbricazione di strutture a circuito integrato e struttura risultante

Country Status (7)

Country Link
US (1) US3861968A (it)
JP (1) JPS5148956B2 (it)
CA (1) CA992219A (it)
DE (1) DE2317577C2 (it)
FR (1) FR2189871B1 (it)
GB (1) GB1360188A (it)
IT (1) IT983948B (it)

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* Cited by examiner, † Cited by third party
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US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
JPS50147682A (it) * 1974-05-15 1975-11-26
US3998673A (en) * 1974-08-16 1976-12-21 Pel Chow Method for forming electrically-isolated regions in integrated circuits utilizing selective epitaxial growth
JPS5146083A (en) * 1974-10-18 1976-04-20 Hitachi Ltd Handotaisochino seizohoho
JPS51135385A (en) * 1975-03-06 1976-11-24 Texas Instruments Inc Method of producing semiconductor device
US4047285A (en) * 1975-05-08 1977-09-13 National Semiconductor Corporation Self-aligned CMOS for bulk silicon and insulating substrate device
US3972754A (en) * 1975-05-30 1976-08-03 Ibm Corporation Method for forming dielectric isolation in integrated circuits
US4005469A (en) * 1975-06-20 1977-01-25 International Business Machines Corporation P-type-epitaxial-base transistor with base-collector Schottky diode clamp
US4056415A (en) * 1975-08-04 1977-11-01 International Telephone And Telegraph Corporation Method for providing electrical isolating material in selected regions of a semiconductive material
US4069094A (en) * 1976-12-30 1978-01-17 Rca Corporation Method of manufacturing apertured aluminum oxide substrates
US4159915A (en) * 1977-10-25 1979-07-03 International Business Machines Corporation Method for fabrication vertical NPN and PNP structures utilizing ion-implantation
JPS54115084A (en) * 1978-02-28 1979-09-07 Cho Lsi Gijutsu Kenkyu Kumiai Method of fabricating semiconductor
JPS5565859U (it) * 1979-09-12 1980-05-07
JPS5570043A (en) * 1979-10-22 1980-05-27 Hitachi Ltd Fabricating method of semiconductor device having isolating oxide region
US4309716A (en) * 1979-10-22 1982-01-05 International Business Machines Corporation Bipolar dynamic memory cell
US4487639A (en) * 1980-09-26 1984-12-11 Texas Instruments Incorporated Localized epitaxy for VLSI devices
JPS57176746A (en) * 1981-04-21 1982-10-30 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit and manufacture thereof
US5134090A (en) * 1982-06-18 1992-07-28 At&T Bell Laboratories Method of fabricating patterned epitaxial silicon films utilizing molecular beam epitaxy
JPS59201440A (ja) * 1983-04-30 1984-11-15 Toshiba Corp 半導体装置及びその製造方法
GB2142185A (en) * 1983-06-22 1985-01-09 Rca Corp Mosfet fabrication method
EP0134504B1 (en) * 1983-07-15 1989-05-10 Kabushiki Kaisha Toshiba A c-mos device and process for manufacturing the same
US4633290A (en) * 1984-12-28 1986-12-30 Gte Laboratories Incorporated Monolithic CMOS integrated circuit structure with isolation grooves
US5135884A (en) * 1991-03-28 1992-08-04 Sgs-Thomson Microelectronics, Inc. Method of producing isoplanar isolated active regions
US5811865A (en) * 1993-12-22 1998-09-22 Stmicroelectronics, Inc. Dielectric in an integrated circuit
US5927992A (en) * 1993-12-22 1999-07-27 Stmicroelectronics, Inc. Method of forming a dielectric in an integrated circuit
US6171913B1 (en) * 1998-09-08 2001-01-09 Taiwan Semiconductor Manufacturing Company Process for manufacturing a single asymmetric pocket implant
US6624486B2 (en) * 2001-05-23 2003-09-23 International Business Machines Corporation Method for low topography semiconductor device formation
US6525340B2 (en) 2001-06-04 2003-02-25 International Business Machines Corporation Semiconductor device with junction isolation
US7250668B2 (en) * 2005-01-20 2007-07-31 Diodes, Inc. Integrated circuit including power diode
US20090087967A1 (en) * 2005-11-14 2009-04-02 Todd Michael A Precursors and processes for low temperature selective epitaxial growth
JP2008244105A (ja) * 2007-03-27 2008-10-09 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
KR101223417B1 (ko) * 2007-12-18 2013-01-17 삼성전자주식회사 반도체 소자 및 이의 제조방법
CN103943471B (zh) * 2014-05-06 2017-05-10 上海先进半导体制造股份有限公司 外延层形成方法及半导体结构

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3296040A (en) * 1962-08-17 1967-01-03 Fairchild Camera Instr Co Epitaxially growing layers of semiconductor through openings in oxide mask
US3206339A (en) * 1963-09-30 1965-09-14 Philco Corp Method of growing geometricallydefined epitaxial layer without formation of undesirable crystallites
US3340598A (en) * 1965-04-19 1967-09-12 Teledyne Inc Method of making field effect transistor device
US3386865A (en) * 1965-05-10 1968-06-04 Ibm Process of making planar semiconductor devices isolated by encapsulating oxide filled channels
US3442011A (en) * 1965-06-30 1969-05-06 Texas Instruments Inc Method for isolating individual devices in an integrated circuit monolithic bar
US3449643A (en) * 1966-09-09 1969-06-10 Hitachi Ltd Semiconductor integrated circuit device
US3534234A (en) * 1966-12-15 1970-10-13 Texas Instruments Inc Modified planar process for making semiconductor devices having ultrafine mesa type geometry
US3440503A (en) * 1967-05-31 1969-04-22 Westinghouse Electric Corp Integrated complementary mos-type transistor structure and method of making same
FR1601776A (fr) * 1967-12-05 1970-09-14 Sony Corp Procédé de fabrication de circuits semi-conducteurs intégrés et circuits ainsi obtenus
US3502951A (en) * 1968-01-02 1970-03-24 Singer Co Monolithic complementary semiconductor device
US3550292A (en) * 1968-08-23 1970-12-29 Nippon Electric Co Semiconductor device and method of manufacturing the same
NL7101307A (it) * 1970-02-03 1971-08-05
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure

Also Published As

Publication number Publication date
JPS5148956B2 (it) 1976-12-23
FR2189871B1 (it) 1977-07-29
JPS4952588A (it) 1974-05-22
DE2317577C2 (de) 1983-12-01
FR2189871A1 (it) 1974-01-25
CA992219A (en) 1976-06-29
DE2317577A1 (de) 1974-01-17
US3861968A (en) 1975-01-21
GB1360188A (en) 1974-07-17

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