IT9020157A0 - Stadio d'uscita dati, del tipo cosiddetto buffer,a ridotto rumore verso massa per circuiti logici di tipo cmos - Google Patents

Stadio d'uscita dati, del tipo cosiddetto buffer,a ridotto rumore verso massa per circuiti logici di tipo cmos

Info

Publication number
IT9020157A0
IT9020157A0 IT9020157A IT2015790A IT9020157A0 IT 9020157 A0 IT9020157 A0 IT 9020157A0 IT 9020157 A IT9020157 A IT 9020157A IT 2015790 A IT2015790 A IT 2015790A IT 9020157 A0 IT9020157 A0 IT 9020157A0
Authority
IT
Italy
Prior art keywords
ground
data output
output stage
logic circuits
reduced noise
Prior art date
Application number
IT9020157A
Other languages
English (en)
Other versions
IT9020157A1 (it
IT1240012B (it
Inventor
Marco Dallaroba
Paolo Rolandi
Marco Maccalli
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT20157A priority Critical patent/IT1240012B/it
Publication of IT9020157A0 publication Critical patent/IT9020157A0/it
Priority to EP91105323A priority patent/EP0455002B1/en
Priority to DE69128494T priority patent/DE69128494T2/de
Priority to JP3123019A priority patent/JPH05102825A/ja
Priority to US07/691,768 priority patent/US5179300A/en
Publication of IT9020157A1 publication Critical patent/IT9020157A1/it
Application granted granted Critical
Publication of IT1240012B publication Critical patent/IT1240012B/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
IT20157A 1990-04-27 1990-04-27 Stadio d'uscita dati, del tipo cosiddetto buffer,a ridotto rumore verso massa per circuiti logici di tipo cmos IT1240012B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT20157A IT1240012B (it) 1990-04-27 1990-04-27 Stadio d'uscita dati, del tipo cosiddetto buffer,a ridotto rumore verso massa per circuiti logici di tipo cmos
EP91105323A EP0455002B1 (en) 1990-04-27 1991-04-04 A data output stage of the buffer type, having reduced noise to ground, for logic circuits of the CMOS type
DE69128494T DE69128494T2 (de) 1990-04-27 1991-04-04 Datenausgabestufe des Puffertyps für CMOS-Logikschaltungen mit vermindertem Störgeräusch gegenüber Masse
JP3123019A JPH05102825A (ja) 1990-04-27 1991-04-26 バツフアー型データ出力段ｃｍｏｓ論理回路
US07/691,768 US5179300A (en) 1990-04-27 1991-04-26 Data output stage having feedback loops to precharge the output node

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT20157A IT1240012B (it) 1990-04-27 1990-04-27 Stadio d'uscita dati, del tipo cosiddetto buffer,a ridotto rumore verso massa per circuiti logici di tipo cmos

Publications (3)

Publication Number Publication Date
IT9020157A0 true IT9020157A0 (it) 1990-04-27
IT9020157A1 IT9020157A1 (it) 1991-10-27
IT1240012B IT1240012B (it) 1993-11-27

Family

ID=11164275

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20157A IT1240012B (it) 1990-04-27 1990-04-27 Stadio d'uscita dati, del tipo cosiddetto buffer,a ridotto rumore verso massa per circuiti logici di tipo cmos

Country Status (5)

Country Link
US (1) US5179300A (it)
EP (1) EP0455002B1 (it)
JP (1) JPH05102825A (it)
DE (1) DE69128494T2 (it)
IT (1) IT1240012B (it)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448181A (en) * 1992-11-06 1995-09-05 Xilinx, Inc. Output buffer circuit having reduced switching noise
US5500817A (en) * 1993-01-21 1996-03-19 Micron Technology, Inc. True tristate output buffer and a method for driving a potential of an output pad to three distinct conditions
JPH06244709A (ja) * 1993-02-19 1994-09-02 Toshiba Corp データ入出力制御回路
US5698994A (en) * 1994-07-29 1997-12-16 Nkk Corporation Data output circuit, intermediate potential setting circuit, and semiconductor integrated circuit
US5831908A (en) * 1994-07-29 1998-11-03 Nkk Corporation Data output circuit, intermediate potential setting circuit, and semiconductor integrated circuit
US5654648A (en) * 1995-03-06 1997-08-05 Alliance Semiconductor Corporation Output buffer circuit with low power pre-output drive
US5684410A (en) * 1995-07-03 1997-11-04 Guo; Frank Tzen-Wen Preconditioning of output buffers
US6239620B1 (en) * 1999-11-29 2001-05-29 International Business Machines Corporation Method and apparatus for generating true/complement signals
GB0003499D0 (en) * 2000-02-15 2000-04-05 Sgs Thomson Microelectronics Circuit for providing a control signal
KR100401493B1 (ko) * 2000-12-27 2003-10-11 주식회사 하이닉스반도체 피크전류 감쇠회로
US6798237B1 (en) 2001-08-29 2004-09-28 Altera Corporation On-chip impedance matching circuit
US6836144B1 (en) * 2001-12-10 2004-12-28 Altera Corporation Programmable series on-chip termination impedance and impedance matching
US7109744B1 (en) 2001-12-11 2006-09-19 Altera Corporation Programmable termination with DC voltage level control
US6812734B1 (en) 2001-12-11 2004-11-02 Altera Corporation Programmable termination with DC voltage level control
US6888369B1 (en) 2003-07-17 2005-05-03 Altera Corporation Programmable on-chip differential termination impedance
US6859064B1 (en) 2003-08-20 2005-02-22 Altera Corporation Techniques for reducing leakage current in on-chip impedance termination circuits
US6888370B1 (en) 2003-08-20 2005-05-03 Altera Corporation Dynamically adjustable termination impedance control techniques
US7221193B1 (en) 2005-01-20 2007-05-22 Altera Corporation On-chip termination with calibrated driver strength
US7218155B1 (en) 2005-01-20 2007-05-15 Altera Corporation Techniques for controlling on-chip termination resistance using voltage range detection
US7679397B1 (en) 2005-08-05 2010-03-16 Altera Corporation Techniques for precision biasing output driver for a calibrated on-chip termination circuit
JP4508222B2 (ja) * 2007-08-31 2010-07-21 ソニー株式会社 プリチャージ制御方法及び表示装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4490633A (en) * 1981-12-28 1984-12-25 Motorola, Inc. TTL to CMOS input buffer
JPS59181829A (ja) * 1983-03-31 1984-10-16 Toshiba Corp 半導体素子の出力バツフア回路
US4612466A (en) * 1984-08-31 1986-09-16 Rca Corporation High-speed output driver
JPS61294682A (ja) * 1985-06-21 1986-12-25 Hitachi Ltd 半導体集積回路装置
JP2548700B2 (ja) * 1986-01-08 1996-10-30 三菱電機株式会社 半導体集積回路
JPS62159911A (ja) * 1986-01-08 1987-07-15 Mitsubishi Electric Corp 半導体集積回路
JPS62248306A (ja) * 1986-04-21 1987-10-29 Mitsubishi Electric Corp 出力バツフア回路
JPS63112893A (ja) * 1986-10-28 1988-05-17 Mitsubishi Electric Corp 半導体集積回路
JPH01200819A (ja) * 1988-02-05 1989-08-14 Toshiba Corp メモリ集積回路
JPH01220819A (ja) * 1988-02-29 1989-09-04 Nippon Telegr & Teleph Corp <Ntt> 複合半導体基板の製法
US5051625B1 (en) * 1988-10-28 1993-11-16 Nissan Motor Co.,Ltd. Output buffer circuits for reducing noise
US4996671A (en) * 1989-02-18 1991-02-26 Sony Corporation Semiconductor memory device

Also Published As

Publication number Publication date
EP0455002A3 (en) 1991-11-21
EP0455002B1 (en) 1997-12-29
IT9020157A1 (it) 1991-10-27
IT1240012B (it) 1993-11-27
EP0455002A2 (en) 1991-11-06
DE69128494T2 (de) 1998-04-16
JPH05102825A (ja) 1993-04-23
DE69128494D1 (de) 1998-02-05
US5179300A (en) 1993-01-12

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970429