IT7827144A0 - Memoria a semiconduttori integrata in forma monolitica. - Google Patents
Memoria a semiconduttori integrata in forma monolitica.Info
- Publication number
- IT7827144A0 IT7827144A0 IT7827144A IT2714478A IT7827144A0 IT 7827144 A0 IT7827144 A0 IT 7827144A0 IT 7827144 A IT7827144 A IT 7827144A IT 2714478 A IT2714478 A IT 2714478A IT 7827144 A0 IT7827144 A0 IT 7827144A0
- Authority
- IT
- Italy
- Prior art keywords
- semiconductor memory
- memory integrated
- monolithic form
- monolithic
- integrated
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Solid State Image Pick-Up Elements (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19772740113 DE2740113A1 (de) | 1977-09-06 | 1977-09-06 | Monolithisch integrierter halbleiterspeicher |
Publications (2)
Publication Number | Publication Date |
---|---|
IT7827144A0 true IT7827144A0 (it) | 1978-08-30 |
IT1098717B IT1098717B (it) | 1985-09-07 |
Family
ID=6018247
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT27144/78A IT1098717B (it) | 1977-09-06 | 1978-08-30 | Memoria a semiconduttori integrata in forma monolitica |
Country Status (7)
Country | Link |
---|---|
US (1) | US4168538A (it) |
JP (1) | JPS5450281A (it) |
BE (1) | BE870261A (it) |
DE (1) | DE2740113A1 (it) |
FR (1) | FR2402277A1 (it) |
GB (1) | GB2004691B (it) |
IT (1) | IT1098717B (it) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4392210A (en) * | 1978-08-28 | 1983-07-05 | Mostek Corporation | One transistor-one capacitor memory cell |
JPS5634179A (en) * | 1979-08-24 | 1981-04-06 | Mitsubishi Electric Corp | Control circuit for memory unit |
JPS57198592A (en) * | 1981-05-29 | 1982-12-06 | Hitachi Ltd | Semiconductor memory device |
GB2135822B (en) * | 1983-02-11 | 1986-07-02 | Standard Telephones Cables Ltd | Memory decoder circuit |
GB8303886D0 (en) * | 1983-02-11 | 1983-03-16 | Itt Ind Ltd | Memory decoder circuit |
US4651183A (en) * | 1984-06-28 | 1987-03-17 | International Business Machines Corporation | High density one device memory cell arrays |
US4648073A (en) * | 1984-12-31 | 1987-03-03 | International Business Machines Corporation | Sequential shared access lines memory cells |
JPH0785356B2 (ja) * | 1986-04-24 | 1995-09-13 | ソニー株式会社 | メモリ装置 |
DE59814170D1 (de) * | 1997-12-17 | 2008-04-03 | Qimonda Ag | Speicherzellenanordnung und Verfahren zu deren Herstellung |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5522640Y2 (it) * | 1973-06-30 | 1980-05-29 | ||
US4041474A (en) * | 1973-10-11 | 1977-08-09 | U.S. Philips Corporation | Memory matrix controller |
DE2441385C3 (de) * | 1974-08-29 | 1981-05-07 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum Vergrößern des Lesesignals bei einem Ein- Transistor-Speicherelement |
JPS5539073B2 (it) * | 1974-12-25 | 1980-10-08 | ||
US4086662A (en) * | 1975-11-07 | 1978-04-25 | Hitachi, Ltd. | Memory system with read/write control lines |
US4056811A (en) * | 1976-02-13 | 1977-11-01 | Baker Roger T | Circuit for the improvement of semiconductor memories |
US4103342A (en) * | 1976-06-17 | 1978-07-25 | International Business Machines Corporation | Two-device memory cell with single floating capacitor |
US4125854A (en) * | 1976-12-02 | 1978-11-14 | Mostek Corporation | Symmetrical cell layout for static RAM |
-
1977
- 1977-09-06 DE DE19772740113 patent/DE2740113A1/de not_active Withdrawn
-
1978
- 1978-08-10 US US05/932,499 patent/US4168538A/en not_active Expired - Lifetime
- 1978-08-28 FR FR7824788A patent/FR2402277A1/fr not_active Withdrawn
- 1978-08-30 IT IT27144/78A patent/IT1098717B/it active
- 1978-09-05 GB GB7835648A patent/GB2004691B/en not_active Expired
- 1978-09-06 BE BE190303A patent/BE870261A/xx unknown
- 1978-09-06 JP JP10951878A patent/JPS5450281A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
FR2402277A1 (fr) | 1979-03-30 |
GB2004691B (en) | 1982-01-20 |
GB2004691A (en) | 1979-04-04 |
JPS5450281A (en) | 1979-04-20 |
US4168538A (en) | 1979-09-18 |
DE2740113A1 (de) | 1979-03-15 |
IT1098717B (it) | 1985-09-07 |
BE870261A (fr) | 1979-01-02 |
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