IT201900024135A1 - Dispositivo di memoria non volatile includente un decodificatore di riga con stadio di pull-up perfezionato - Google Patents

Dispositivo di memoria non volatile includente un decodificatore di riga con stadio di pull-up perfezionato

Info

Publication number
IT201900024135A1
IT201900024135A1 IT102019000024135A IT201900024135A IT201900024135A1 IT 201900024135 A1 IT201900024135 A1 IT 201900024135A1 IT 102019000024135 A IT102019000024135 A IT 102019000024135A IT 201900024135 A IT201900024135 A IT 201900024135A IT 201900024135 A1 IT201900024135 A1 IT 201900024135A1
Authority
IT
Italy
Prior art keywords
stage
memory device
volatile memory
device including
line decoder
Prior art date
Application number
IT102019000024135A
Other languages
English (en)
Inventor
Fabio Enrico Carlo Disegni
Maurizio Francesco Perroni
Cesare Torti
Davide Manfre'
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT102019000024135A priority Critical patent/IT201900024135A1/it
Priority to EP20213992.9A priority patent/EP3839956B1/en
Priority to CN202011490378.6A priority patent/CN112992227A/zh
Priority to US17/123,518 priority patent/US11289158B2/en
Publication of IT201900024135A1 publication Critical patent/IT201900024135A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor
IT102019000024135A 2019-12-16 2019-12-16 Dispositivo di memoria non volatile includente un decodificatore di riga con stadio di pull-up perfezionato IT201900024135A1 (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT102019000024135A IT201900024135A1 (it) 2019-12-16 2019-12-16 Dispositivo di memoria non volatile includente un decodificatore di riga con stadio di pull-up perfezionato
EP20213992.9A EP3839956B1 (en) 2019-12-16 2020-12-15 A non-volatile memory device including a row decoder with an improved pull-up stage
CN202011490378.6A CN112992227A (zh) 2019-12-16 2020-12-16 包括具有上拉级的行解码器的非易失性存储器装置
US17/123,518 US11289158B2 (en) 2019-12-16 2020-12-16 Non-volatile memory device including a row decoder with a pull-up stage controlled by a current mirror

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT102019000024135A IT201900024135A1 (it) 2019-12-16 2019-12-16 Dispositivo di memoria non volatile includente un decodificatore di riga con stadio di pull-up perfezionato

Publications (1)

Publication Number Publication Date
IT201900024135A1 true IT201900024135A1 (it) 2021-06-16

Family

ID=69904107

Family Applications (1)

Application Number Title Priority Date Filing Date
IT102019000024135A IT201900024135A1 (it) 2019-12-16 2019-12-16 Dispositivo di memoria non volatile includente un decodificatore di riga con stadio di pull-up perfezionato

Country Status (4)

Country Link
US (1) US11289158B2 (it)
EP (1) EP3839956B1 (it)
CN (1) CN112992227A (it)
IT (1) IT201900024135A1 (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT202100004973A1 (it) * 2021-03-03 2022-09-03 St Microelectronics Srl Dispositivo di memoria non volatile a cambiamento di fase includente un decodificatore di riga distribuito con transistori mosfet a canale n e relativo metodo di decodifica di riga

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130286754A1 (en) * 2012-04-26 2013-10-31 SK Hynix Inc. Wordline Coupling Reduction Technique
US8737137B1 (en) * 2013-01-22 2014-05-27 Freescale Semiconductor, Inc. Flash memory with bias voltage for word line/row driver
US20190206488A1 (en) * 2018-01-04 2019-07-04 Stmicroelectronics S.R.I. Row Decoding Architecture for a Phase-Change Non-Volatile Memory Device and Corresponding Row Decoding Method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITVA20050028A1 (it) * 2005-05-03 2006-11-04 St Microelectronics Srl Generatore di rampa e relativa decodifica di riga per memoria flash
US7468906B2 (en) * 2005-09-13 2008-12-23 Northern Lights Semiconductor Corp. Word driver and decode design methodology in MRAM circuit
JP5197448B2 (ja) * 2009-03-13 2013-05-15 株式会社東芝 抵抗変化メモリ装置
US9466347B1 (en) * 2015-12-16 2016-10-11 Stmicroelectronics International N.V. Row decoder for non-volatile memory devices and related methods
IT201600121631A1 (it) * 2016-11-30 2018-05-30 St Microelectronics Srl Dispositivo di memoria a cambiamento di fase con un circuito di pilotaggio di linea di parola a elevata velocita'
IT201900021165A1 (it) * 2019-11-14 2021-05-14 St Microelectronics Srl Dispositivo di memoria non volatile con un decodificatore di riga asimmetrico e metodo di selezione di linee di parola

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130286754A1 (en) * 2012-04-26 2013-10-31 SK Hynix Inc. Wordline Coupling Reduction Technique
US8737137B1 (en) * 2013-01-22 2014-05-27 Freescale Semiconductor, Inc. Flash memory with bias voltage for word line/row driver
US20190206488A1 (en) * 2018-01-04 2019-07-04 Stmicroelectronics S.R.I. Row Decoding Architecture for a Phase-Change Non-Volatile Memory Device and Corresponding Row Decoding Method

Also Published As

Publication number Publication date
CN112992227A (zh) 2021-06-18
EP3839956A1 (en) 2021-06-23
US20210183442A1 (en) 2021-06-17
US11289158B2 (en) 2022-03-29
EP3839956B1 (en) 2023-07-26

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