IT1301799B1 - Processo di fabbricazione di una memoria non volatile con ridottaresistenza delle linee di source comune. - Google Patents

Processo di fabbricazione di una memoria non volatile con ridottaresistenza delle linee di source comune.

Info

Publication number
IT1301799B1
IT1301799B1 IT1998MI001449A ITMI981449A IT1301799B1 IT 1301799 B1 IT1301799 B1 IT 1301799B1 IT 1998MI001449 A IT1998MI001449 A IT 1998MI001449A IT MI981449 A ITMI981449 A IT MI981449A IT 1301799 B1 IT1301799 B1 IT 1301799B1
Authority
IT
Italy
Prior art keywords
manufacturing process
volatile memory
common source
source lines
reduced resistance
Prior art date
Application number
IT1998MI001449A
Other languages
English (en)
Inventor
Bruno Vajana
Federico Pio
Nicola Zatelli
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT1998MI001449A priority Critical patent/IT1301799B1/it
Priority to US09/337,051 priority patent/US6180460B1/en
Publication of ITMI981449A1 publication Critical patent/ITMI981449A1/it
Application granted granted Critical
Publication of IT1301799B1 publication Critical patent/IT1301799B1/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
IT1998MI001449A 1998-06-25 1998-06-25 Processo di fabbricazione di una memoria non volatile con ridottaresistenza delle linee di source comune. IT1301799B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT1998MI001449A IT1301799B1 (it) 1998-06-25 1998-06-25 Processo di fabbricazione di una memoria non volatile con ridottaresistenza delle linee di source comune.
US09/337,051 US6180460B1 (en) 1998-06-25 1999-06-21 Process for manufacturing of a non volatile memory with reduced resistance of the common source lines

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT1998MI001449A IT1301799B1 (it) 1998-06-25 1998-06-25 Processo di fabbricazione di una memoria non volatile con ridottaresistenza delle linee di source comune.

Publications (2)

Publication Number Publication Date
ITMI981449A1 ITMI981449A1 (it) 1999-12-25
IT1301799B1 true IT1301799B1 (it) 2000-07-07

Family

ID=11380314

Family Applications (1)

Application Number Title Priority Date Filing Date
IT1998MI001449A IT1301799B1 (it) 1998-06-25 1998-06-25 Processo di fabbricazione di una memoria non volatile con ridottaresistenza delle linee di source comune.

Country Status (2)

Country Link
US (1) US6180460B1 (it)
IT (1) IT1301799B1 (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1045440A1 (en) * 1999-04-14 2000-10-18 STMicroelectronics S.r.l. Process of manufacture of a non volatile memory with electric continuity of the common source lines
US6596584B1 (en) * 1999-12-15 2003-07-22 Texas Instruments Incorporated Method for fabricating a self-aligned source line flash memory device
TW523881B (en) * 2001-02-08 2003-03-11 Samsung Electronics Co Ltd Non-volatile memory device and method of manufacturing the same
JP4481557B2 (ja) * 2002-07-17 2010-06-16 Ｏｋｉセミコンダクタ株式会社 不揮発性半導体記憶装置の製造方法
JP2005116970A (ja) * 2003-10-10 2005-04-28 Toshiba Corp 不揮発性半導体記憶装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3065164B2 (ja) * 1992-03-18 2000-07-12 富士通株式会社 半導体装置及びその製造方法
US6013574A (en) * 1996-01-30 2000-01-11 Advanced Micro Devices, Inc. Method of forming low resistance contact structures in vias arranged between two levels of interconnect lines
JP3548834B2 (ja) * 1996-09-04 2004-07-28 沖電気工業株式会社 不揮発性半導体メモリの製造方法
US6013551A (en) * 1997-09-26 2000-01-11 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby
US6071779A (en) * 1998-01-13 2000-06-06 Texas Instruments Incorporated Source line fabrication process for flash memory
US5998262A (en) * 1998-04-23 1999-12-07 Worldwide Semiconductor Manufacturing Corp. Method for manufacturing ETOX cell having damage-free source region
TW401627B (en) * 1998-08-20 2000-08-11 United Microelectronics Corp Flash memory structure and the manufacture method thereof

Also Published As

Publication number Publication date
ITMI981449A1 (it) 1999-12-25
US6180460B1 (en) 2001-01-30

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