IT1200578B - Procedimento per la fabbricazione di dispositivi cmos con riduzione del numero di fasi di mascheratura - Google Patents

Procedimento per la fabbricazione di dispositivi cmos con riduzione del numero di fasi di mascheratura

Info

Publication number
IT1200578B
IT1200578B IT22853/86A IT2285386A IT1200578B IT 1200578 B IT1200578 B IT 1200578B IT 22853/86 A IT22853/86 A IT 22853/86A IT 2285386 A IT2285386 A IT 2285386A IT 1200578 B IT1200578 B IT 1200578B
Authority
IT
Italy
Prior art keywords
procedure
manufacture
reduction
cmos devices
masking
Prior art date
Application number
IT22853/86A
Other languages
English (en)
Other versions
IT8622853A0 (it
Inventor
Stefano Mazzali
Original Assignee
Sgs Microelettronica Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Microelettronica Spa filed Critical Sgs Microelettronica Spa
Priority to IT22853/86A priority Critical patent/IT1200578B/it
Publication of IT8622853A0 publication Critical patent/IT8622853A0/it
Priority to EP87118793A priority patent/EP0275508A1/en
Priority to JP62326641A priority patent/JPS63232457A/ja
Application granted granted Critical
Publication of IT1200578B publication Critical patent/IT1200578B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
IT22853/86A 1986-12-23 1986-12-23 Procedimento per la fabbricazione di dispositivi cmos con riduzione del numero di fasi di mascheratura IT1200578B (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT22853/86A IT1200578B (it) 1986-12-23 1986-12-23 Procedimento per la fabbricazione di dispositivi cmos con riduzione del numero di fasi di mascheratura
EP87118793A EP0275508A1 (en) 1986-12-23 1987-12-18 Method for making CMOS devices
JP62326641A JPS63232457A (ja) 1986-12-23 1987-12-22 相補形金属酸化膜半導体デバイスを製造するための方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT22853/86A IT1200578B (it) 1986-12-23 1986-12-23 Procedimento per la fabbricazione di dispositivi cmos con riduzione del numero di fasi di mascheratura

Publications (2)

Publication Number Publication Date
IT8622853A0 IT8622853A0 (it) 1986-12-23
IT1200578B true IT1200578B (it) 1989-01-27

Family

ID=11201192

Family Applications (1)

Application Number Title Priority Date Filing Date
IT22853/86A IT1200578B (it) 1986-12-23 1986-12-23 Procedimento per la fabbricazione di dispositivi cmos con riduzione del numero di fasi di mascheratura

Country Status (3)

Country Link
EP (1) EP0275508A1 (it)
JP (1) JPS63232457A (it)
IT (1) IT1200578B (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4925806A (en) * 1988-03-17 1990-05-15 Northern Telecom Limited Method for making a doped well in a semiconductor substrate
JPH05267604A (ja) * 1991-05-08 1993-10-15 Seiko Instr Inc 半導体装置の製造方法
EP0637074A3 (en) * 1993-07-30 1995-06-21 Sgs Thomson Microelectronics Process for the production of active and isolated areas by split imaging.
TW301027B (it) * 1994-11-28 1997-03-21 Advanced Micro Devices Inc

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5766659A (en) * 1980-10-09 1982-04-22 Toshiba Corp Manufacture of complementary mos semiconductor device
JPS6144456A (ja) * 1984-08-09 1986-03-04 Fujitsu Ltd 半導体装置の製造方法
JPS6165471A (ja) * 1984-09-07 1986-04-04 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0275508A1 (en) 1988-07-27
JPS63232457A (ja) 1988-09-28
IT8622853A0 (it) 1986-12-23

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19961227