DE3381730D1 - Herstellung von halbleiteranordnungen. - Google Patents

Herstellung von halbleiteranordnungen.

Info

Publication number
DE3381730D1
DE3381730D1 DE8383307193T DE3381730T DE3381730D1 DE 3381730 D1 DE3381730 D1 DE 3381730D1 DE 8383307193 T DE8383307193 T DE 8383307193T DE 3381730 T DE3381730 T DE 3381730T DE 3381730 D1 DE3381730 D1 DE 3381730D1
Authority
DE
Germany
Prior art keywords
production
semiconductor arrangements
arrangements
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8383307193T
Other languages
English (en)
Inventor
Ryoichi Mukai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3381730D1 publication Critical patent/DE3381730D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8383307193T 1982-11-30 1983-11-24 Herstellung von halbleiteranordnungen. Expired - Fee Related DE3381730D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57210133A JPS59100520A (ja) 1982-11-30 1982-11-30 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE3381730D1 true DE3381730D1 (de) 1990-08-16

Family

ID=16584327

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383307193T Expired - Fee Related DE3381730D1 (de) 1982-11-30 1983-11-24 Herstellung von halbleiteranordnungen.

Country Status (4)

Country Link
US (1) US4551907A (de)
EP (1) EP0113522B1 (de)
JP (1) JPS59100520A (de)
DE (1) DE3381730D1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4521952A (en) * 1982-12-02 1985-06-11 International Business Machines Corporation Method of making integrated circuits using metal silicide contacts
JPS6063926A (ja) * 1983-08-31 1985-04-12 Fujitsu Ltd 半導体装置の製造方法
DE3683679D1 (de) * 1985-04-26 1992-03-12 Fujitsu Ltd Verfahren zur herstellung einer kontaktanordnung fuer eine halbleiteranordnung.
JPH084078B2 (ja) * 1985-05-27 1996-01-17 富士通株式会社 半導体装置の製造方法
JP2757927B2 (ja) * 1990-06-28 1998-05-25 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体基板上の隔置されたシリコン領域の相互接続方法
JP2933429B2 (ja) * 1991-11-06 1999-08-16 キヤノン株式会社 液体噴射記録ヘッド用基板、液体噴射記録ヘッドおよび液体噴射記録装置
JP3297784B2 (ja) * 1994-09-29 2002-07-02 ソニー株式会社 拡散層抵抗の形成方法
DE19503641A1 (de) * 1995-02-06 1996-08-08 Forschungszentrum Juelich Gmbh Schichtstruktur mit einer Silicid-Schicht, sowie Verfahren zur Herstellung einer solchen Schichtstruktur
DE19600780B4 (de) * 1996-01-11 2006-04-13 Micronas Gmbh Verfahren zum Kontaktieren von Bereichen mit verschiedener Dotierung in einem Halbleiterbauelement und Halbleiterbauelement
US6143613A (en) * 1997-06-30 2000-11-07 Vlsi Technology, Inc. Selective exclusion of silicide formation to make polysilicon resistors
TW331033B (en) * 1997-08-16 1998-05-01 Winbond Electronics Corp Static random access memory self-aligned load structure and producing method
US6518176B2 (en) 1998-06-05 2003-02-11 Ted Guo Method of selective formation of a barrier layer for a contact level via
DE19919110C2 (de) 1999-04-27 2002-06-27 Infineon Technologies Ag Verfahren zum Strukturieren einer Metall- oder Metallsilizidschicht sowie ein mit diesem Verfahren hergestellter Kondensator
DE10207130B4 (de) 2002-02-20 2007-09-27 Infineon Technologies Ag Verfahren zur Herstellung eines Bauelements sowie Bauelement mit einer Edelmetallschicht, einer Edelmetallsilizidschicht und einer oxidierten Silizidschicht

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3777364A (en) * 1972-07-31 1973-12-11 Fairchild Camera Instr Co Methods for forming metal/metal silicide semiconductor device interconnect system
US4180596A (en) * 1977-06-30 1979-12-25 International Business Machines Corporation Method for providing a metal silicide layer on a substrate
US4332839A (en) * 1978-12-29 1982-06-01 Bell Telephone Laboratories, Incorporated Method for making integrated semiconductor circuit structure with formation of Ti or Ta silicide
GB2061615A (en) * 1979-10-25 1981-05-13 Gen Electric Composite conductors for integrated circuits
JPS56158454A (en) * 1980-05-12 1981-12-07 Mitsubishi Electric Corp Manufacture of semiconductor device
US4285761A (en) * 1980-06-30 1981-08-25 International Business Machines Corporation Process for selectively forming refractory metal silicide layers on semiconductor devices
JPS5745967A (en) * 1980-09-04 1982-03-16 Toshiba Corp Semiconductor device
IE52791B1 (en) * 1980-11-05 1988-03-02 Fujitsu Ltd Semiconductor devices

Also Published As

Publication number Publication date
JPS59100520A (ja) 1984-06-09
EP0113522A3 (en) 1987-01-28
US4551907A (en) 1985-11-12
EP0113522B1 (de) 1990-07-11
JPH024131B2 (de) 1990-01-26
EP0113522A2 (de) 1984-07-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee