IT1153915B - Dispositivo a circuito integrato a ram dinamica - Google Patents

Dispositivo a circuito integrato a ram dinamica

Info

Publication number
IT1153915B
IT1153915B IT24991/82A IT2499182A IT1153915B IT 1153915 B IT1153915 B IT 1153915B IT 24991/82 A IT24991/82 A IT 24991/82A IT 2499182 A IT2499182 A IT 2499182A IT 1153915 B IT1153915 B IT 1153915B
Authority
IT
Italy
Prior art keywords
integrated circuit
circuit device
dynamic ram
ram integrated
dynamic
Prior art date
Application number
IT24991/82A
Other languages
English (en)
Italian (it)
Other versions
IT8224991A0 (it
IT8224991A1 (it
Inventor
Matsuura Hiromi
Original Assignee
Hitachi Ltd
Hitachi Microcumputer Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcumputer Eng filed Critical Hitachi Ltd
Publication of IT8224991A0 publication Critical patent/IT8224991A0/it
Publication of IT8224991A1 publication Critical patent/IT8224991A1/it
Application granted granted Critical
Publication of IT1153915B publication Critical patent/IT1153915B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4099—Dummy cell treatment; Reference voltage generators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/853—Complementary IGFETs, e.g. CMOS comprising FinFETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
IT24991/82A 1981-12-25 1982-12-24 Dispositivo a circuito integrato a ram dinamica IT1153915B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56209397A JPS58111183A (ja) 1981-12-25 1981-12-25 ダイナミツクｒａｍ集積回路装置

Publications (3)

Publication Number Publication Date
IT8224991A0 IT8224991A0 (it) 1982-12-24
IT8224991A1 IT8224991A1 (it) 1984-06-24
IT1153915B true IT1153915B (it) 1987-01-21

Family

ID=16572215

Family Applications (1)

Application Number Title Priority Date Filing Date
IT24991/82A IT1153915B (it) 1981-12-25 1982-12-24 Dispositivo a circuito integrato a ram dinamica

Country Status (10)

Country Link
US (1) US4551820A (OSRAM)
JP (1) JPS58111183A (OSRAM)
KR (1) KR900007275B1 (OSRAM)
DE (1) DE3247538A1 (OSRAM)
FR (1) FR2519177B1 (OSRAM)
GB (2) GB2112568B (OSRAM)
HK (2) HK1788A (OSRAM)
IT (1) IT1153915B (OSRAM)
MY (1) MY8700799A (OSRAM)
SG (1) SG88187G (OSRAM)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6054471A (ja) * 1983-09-05 1985-03-28 Hitachi Ltd 半導体メモリ
JPS6085492A (ja) * 1983-10-17 1985-05-14 Hitachi Ltd ダイナミツクメモリ装置
US4961166A (en) * 1984-05-07 1990-10-02 Hitachi, Ltd. Dynamic RAM having a full size dummy cell
US4771404A (en) * 1984-09-05 1988-09-13 Nippon Telegraph And Telephone Corporation Memory device employing multilevel storage circuits
JPH0760858B2 (ja) * 1984-10-26 1995-06-28 三菱電機株式会社 半導体メモリ装置
JPS61110459A (ja) * 1984-11-02 1986-05-28 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリ
JPS61123168A (ja) * 1984-11-20 1986-06-11 Fujitsu Ltd 半導体記憶装置
JPS61126690A (ja) * 1984-11-26 1986-06-14 Hitachi Ltd 半導体メモリ
JPH0666442B2 (ja) * 1985-03-08 1994-08-24 三菱電機株式会社 半導体メモリ装置
JPS61230359A (ja) * 1985-04-05 1986-10-14 Nec Ic Microcomput Syst Ltd 半導体記憶装置
JPH0682802B2 (ja) * 1985-05-23 1994-10-19 三菱電機株式会社 半導体メモリ装置
JPS62117191A (ja) * 1985-11-15 1987-05-28 Mitsubishi Electric Corp 半導体記憶装置
JPS62197990A (ja) * 1986-02-25 1987-09-01 Mitsubishi Electric Corp 半導体記憶回路
CA1305255C (en) * 1986-08-25 1992-07-14 Joseph Lebowitz Marching interconnecting lines in semiconductor integrated circuits
JPH06101229B2 (ja) * 1986-09-09 1994-12-12 三菱電機株式会社 ダイナミツク・ランダム・アクセス・メモリ
KR890003372B1 (ko) * 1986-11-24 1989-09-19 삼성전자 주식회사 다이나믹 랜덤 액세스 메모리 어레이
JPH0632213B2 (ja) * 1987-02-26 1994-04-27 日本電気株式会社 半導体メモリ
JP2534700B2 (ja) * 1987-04-02 1996-09-18 日本電気株式会社 半導体記憶装置
US5249159A (en) * 1987-05-27 1993-09-28 Hitachi, Ltd. Semiconductor memory
JP3005223B2 (ja) * 1988-06-27 2000-01-31 日本電気アイシーマイコンシステム株式会社 半導体記憶装置
JPH0828467B2 (ja) * 1988-11-15 1996-03-21 株式会社東芝 半導体装置
JP2650377B2 (ja) * 1988-12-13 1997-09-03 富士通株式会社 半導体集積回路
US5307356A (en) * 1990-04-16 1994-04-26 International Business Machines Corporation Interlocked on-chip ECC system
EP0471535B1 (en) * 1990-08-13 1998-01-28 Nec Corporation Semiconductor memory device
US5278105A (en) * 1992-08-19 1994-01-11 Intel Corporation Semiconductor device with dummy features in active layers
US6490214B2 (en) * 2000-12-26 2002-12-03 Kabushiki Kaisha Toshiba Semiconductor memory device
US6788614B2 (en) 2001-06-14 2004-09-07 Micron Technology, Inc. Semiconductor memory with wordline timing
US9478556B2 (en) * 2014-09-11 2016-10-25 Kabushiki Kaisha Toshiba Semiconductor memory device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5539073B2 (OSRAM) * 1974-12-25 1980-10-08
US4045783A (en) * 1976-04-12 1977-08-30 Standard Microsystems Corporation Mos one transistor cell ram having divided and balanced bit lines, coupled by regenerative flip-flop sense amplifiers, and balanced access circuitry
SU928412A1 (ru) * 1976-09-30 1982-05-15 Предприятие П/Я Р-6429 Матричный накопитель дл интегрального запоминающего устройства
DE2647394C2 (de) * 1976-10-20 1978-11-16 Siemens Ag, 1000 Berlin Und 8000 Muenchen MOS-Halbleiterspeicherbaustein
JPS5693363A (en) * 1979-12-04 1981-07-28 Fujitsu Ltd Semiconductor memory
JPS57111061A (en) * 1980-12-26 1982-07-10 Fujitsu Ltd Semiconductor memory unit

Also Published As

Publication number Publication date
GB2155239B (en) 1986-02-26
JPH0381233B2 (OSRAM) 1991-12-27
MY8700799A (en) 1987-12-31
FR2519177A1 (fr) 1983-07-01
HK1888A (en) 1988-01-15
GB2155239A (en) 1985-09-18
US4551820A (en) 1985-11-05
SG88187G (en) 1988-06-03
DE3247538C2 (OSRAM) 1991-12-05
JPS58111183A (ja) 1983-07-02
GB2112568B (en) 1986-02-26
GB8505714D0 (en) 1985-04-11
KR900007275B1 (ko) 1990-10-06
KR840003146A (ko) 1984-08-13
FR2519177B1 (fr) 1987-12-18
DE3247538A1 (de) 1983-08-04
GB2112568A (en) 1983-07-20
IT8224991A0 (it) 1982-12-24
IT8224991A1 (it) 1984-06-24
HK1788A (en) 1988-01-15

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19961223