IT1064433B - Procedimento per fabbricare un transistore planare con un alto guadagno di corrente locale inverso - Google Patents

Procedimento per fabbricare un transistore planare con un alto guadagno di corrente locale inverso

Info

Publication number
IT1064433B
IT1064433B IT29752/76A IT2975276A IT1064433B IT 1064433 B IT1064433 B IT 1064433B IT 29752/76 A IT29752/76 A IT 29752/76A IT 2975276 A IT2975276 A IT 2975276A IT 1064433 B IT1064433 B IT 1064433B
Authority
IT
Italy
Prior art keywords
procedure
manufacturing
current gain
planar transistor
local current
Prior art date
Application number
IT29752/76A
Other languages
English (en)
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of IT1064433B publication Critical patent/IT1064433B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
IT29752/76A 1975-12-03 1976-11-25 Procedimento per fabbricare un transistore planare con un alto guadagno di corrente locale inverso IT1064433B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2554426A DE2554426C3 (de) 1975-12-03 1975-12-03 Verfahren zur Erzeugung einer lokal hohen inversen Stromverstärkung bei einem Planartransistor sowie nach diesem Verfahren hergestellter invers betriebener Transistor

Publications (1)

Publication Number Publication Date
IT1064433B true IT1064433B (it) 1985-02-18

Family

ID=5963381

Family Applications (1)

Application Number Title Priority Date Filing Date
IT29752/76A IT1064433B (it) 1975-12-03 1976-11-25 Procedimento per fabbricare un transistore planare con un alto guadagno di corrente locale inverso

Country Status (6)

Country Link
US (1) US4118251A (it)
JP (1) JPS5269277A (it)
DE (1) DE2554426C3 (it)
FR (1) FR2334198A1 (it)
GB (1) GB1502229A (it)
IT (1) IT1064433B (it)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4128439A (en) * 1977-08-01 1978-12-05 International Business Machines Corporation Method for forming self-aligned field effect device by ion implantation and outdiffusion
CA1116309A (en) * 1977-11-30 1982-01-12 David L. Bergeron Structure and process for optimizing the characteristics of i.sup.2l devices
US4258379A (en) * 1978-09-25 1981-03-24 Hitachi, Ltd. IIL With in and outdiffused emitter pocket
US4278475A (en) * 1979-01-04 1981-07-14 Westinghouse Electric Corp. Forming of contoured irradiated regions in materials such as semiconductor bodies by nuclear radiation
CA1188418A (en) * 1982-01-04 1985-06-04 Jay A. Shideler Oxide isolation process for standard ram/prom and lateral pnp cell ram
US4624046A (en) * 1982-01-04 1986-11-25 Fairchild Camera & Instrument Corp. Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM
JPS60251664A (ja) * 1984-05-28 1985-12-12 Sony Corp 半導体装置の製造方法
GB2188478B (en) * 1986-03-26 1989-11-22 Stc Plc Forming doped wells in sillicon subtstrates
FR2636474B1 (fr) * 1988-09-09 1990-11-30 Sgs Thomson Microelectronics Procede de fabrication d'une diode de regulation et de protection

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1050478A (it) * 1962-10-08
DE1614827C2 (de) * 1967-06-22 1979-06-21 Telefunken Patentverwertungsgesellschaft Mbh, 7900 Ulm Verfahren zum Herstellen eines Transistors
US3655457A (en) * 1968-08-06 1972-04-11 Ibm Method of making or modifying a pn-junction by ion implantation
BE758683A (fr) * 1969-11-10 1971-05-10 Ibm Procede de fabrication d'un dispositif monolithique auto-isolant et structure de transistor a socle
DE2021824C3 (de) * 1970-05-05 1980-08-14 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithische Halbleiterschaltung
DE2507038C3 (de) * 1975-02-19 1980-01-24 Siemens Ag, 1000 Berlin Und 8000 Muenchen Inverser Planartransistor und Verfahren zu seiner Herstellung
DE2507613C3 (de) * 1975-02-21 1979-07-05 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung eines invers betriebenen Transistors

Also Published As

Publication number Publication date
GB1502229A (en) 1978-02-22
FR2334198B1 (it) 1983-01-21
US4118251A (en) 1978-10-03
DE2554426B2 (de) 1978-10-26
FR2334198A1 (fr) 1977-07-01
DE2554426A1 (de) 1977-06-16
JPS5269277A (en) 1977-06-08
DE2554426C3 (de) 1979-06-21

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