IT1058695B - Procedimento per rimuovere sporgenze dalla superficie di uno strato semiconduttore - Google Patents
Procedimento per rimuovere sporgenze dalla superficie di uno strato semiconduttoreInfo
- Publication number
- IT1058695B IT1058695B IT21687/76A IT2168776A IT1058695B IT 1058695 B IT1058695 B IT 1058695B IT 21687/76 A IT21687/76 A IT 21687/76A IT 2168776 A IT2168776 A IT 2168776A IT 1058695 B IT1058695 B IT 1058695B
- Authority
- IT
- Italy
- Prior art keywords
- procedure
- semiconductive layer
- projects
- remove
- remove projects
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
- H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/017—Clean surfaces
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/051—Etching
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/106—Masks, special
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Weting (AREA)
- Formation Of Insulating Films (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/563,722 US3990925A (en) | 1975-03-31 | 1975-03-31 | Removal of projections on epitaxial layers |
Publications (1)
Publication Number | Publication Date |
---|---|
IT1058695B true IT1058695B (it) | 1982-05-10 |
Family
ID=24251640
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT21687/76A IT1058695B (it) | 1975-03-31 | 1976-03-29 | Procedimento per rimuovere sporgenze dalla superficie di uno strato semiconduttore |
Country Status (7)
Country | Link |
---|---|
US (1) | US3990925A (it) |
JP (1) | JPS51121266A (it) |
CA (1) | CA1042115A (it) |
DE (1) | DE2613490C3 (it) |
FR (1) | FR2306529A1 (it) |
GB (1) | GB1537306A (it) |
IT (1) | IT1058695B (it) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5244173A (en) * | 1975-10-06 | 1977-04-06 | Hitachi Ltd | Method of flat etching of silicon substrate |
JPS5527686A (en) * | 1978-08-21 | 1980-02-27 | Sony Corp | Projection eliminating device |
JPS5612723A (en) * | 1979-07-11 | 1981-02-07 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS56114315A (en) * | 1980-02-14 | 1981-09-08 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS57115824A (en) * | 1981-01-10 | 1982-07-19 | Nec Home Electronics Ltd | Removing epitaxial layer mound |
DE3524765A1 (de) * | 1985-07-11 | 1987-01-22 | Licentia Gmbh | Verfahren zum herstellen einer durchsichtphotokathode |
JPS62128516A (ja) * | 1985-11-29 | 1987-06-10 | Shin Etsu Handotai Co Ltd | 半導体ウエ−ハの突起物除去方法 |
DE3721940A1 (de) * | 1987-07-02 | 1989-01-12 | Ibm Deutschland | Entfernen von partikeln von oberflaechen fester koerper durch laserbeschuss |
JP3060714B2 (ja) * | 1992-04-15 | 2000-07-10 | 日本電気株式会社 | 半導体集積回路の製造方法 |
JP2011096935A (ja) * | 2009-10-30 | 2011-05-12 | Fujifilm Corp | エピタキシャルウエハ、エピタキシャルウエハの製造方法、発光素子ウエハ、発光素子ウエハの製造方法、及び発光素子 |
FR2994615A1 (fr) * | 2012-08-14 | 2014-02-21 | Commissariat Energie Atomique | Procede de planarisation d'une couche epitaxiee |
WO2019054292A1 (ja) | 2017-09-14 | 2019-03-21 | 信越化学工業株式会社 | 水中油型乳化組成物の製造方法及び化粧料 |
JP2019090956A (ja) * | 2017-11-16 | 2019-06-13 | 旭化成エレクトロニクス株式会社 | 光学素子の製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1652225A1 (de) * | 1967-08-21 | 1971-04-22 | Halbleiterwerk Frankfurt Oder | Verfahren zum Abtragen und Polieren von Halbleiterkoerpern,insbesondere Silizium-Einkristallscheiben |
US3656671A (en) * | 1970-03-16 | 1972-04-18 | Ibm | Frangible projection removal |
US3699644A (en) * | 1971-01-04 | 1972-10-24 | Sylvania Electric Prod | Method of dividing wafers |
US3783044A (en) * | 1971-04-09 | 1974-01-01 | Motorola Inc | Photoresist keys and depth indicator |
US3718514A (en) * | 1971-05-28 | 1973-02-27 | Bell Telephone Labor Inc | Removal of projections on epitaxial layers |
BE789090A (fr) * | 1971-09-22 | 1973-01-15 | Western Electric Co | Procede et solution d'attaque de semi-conducteurs |
US3838501A (en) * | 1973-02-09 | 1974-10-01 | Honeywell Inf Systems | Method in microcircuit package assembly providing nonabrasive, electrically passive edges on integrated circuit chips |
-
1975
- 1975-03-31 US US05/563,722 patent/US3990925A/en not_active Expired - Lifetime
-
1976
- 1976-02-23 CA CA246,348A patent/CA1042115A/en not_active Expired
- 1976-03-26 GB GB12359/76A patent/GB1537306A/en not_active Expired
- 1976-03-29 JP JP51033693A patent/JPS51121266A/ja active Granted
- 1976-03-29 IT IT21687/76A patent/IT1058695B/it active
- 1976-03-30 FR FR7609221A patent/FR2306529A1/fr active Granted
- 1976-03-30 DE DE2613490A patent/DE2613490C3/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5533176B2 (it) | 1980-08-29 |
JPS51121266A (en) | 1976-10-23 |
DE2613490B2 (de) | 1978-04-13 |
FR2306529B1 (it) | 1978-05-19 |
CA1042115A (en) | 1978-11-07 |
US3990925A (en) | 1976-11-09 |
GB1537306A (en) | 1978-12-29 |
DE2613490C3 (de) | 1981-10-08 |
FR2306529A1 (fr) | 1976-10-29 |
DE2613490A1 (de) | 1976-10-14 |
USB563722I5 (it) | 1976-01-13 |
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