IT1011152B - Procedimento per realizzare circui ti integrati con transistori ad ef fetto di campo con canali comple mentari - Google Patents

Procedimento per realizzare circui ti integrati con transistori ad ef fetto di campo con canali comple mentari

Info

Publication number
IT1011152B
IT1011152B IT49644/74A IT4964474A IT1011152B IT 1011152 B IT1011152 B IT 1011152B IT 49644/74 A IT49644/74 A IT 49644/74A IT 4964474 A IT4964474 A IT 4964474A IT 1011152 B IT1011152 B IT 1011152B
Authority
IT
Italy
Prior art keywords
transistors
channels
procedure
field effect
integrated circuits
Prior art date
Application number
IT49644/74A
Other languages
English (en)
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of IT1011152B publication Critical patent/IT1011152B/it

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • H10D86/03Manufacture or treatment wherein the substrate comprises sapphire, e.g. silicon-on-sapphire [SOS]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/141Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer comprising oxides only
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/053Field effect transistors fets
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/06Gettering
IT49644/74A 1973-03-30 1974-03-26 Procedimento per realizzare circui ti integrati con transistori ad ef fetto di campo con canali comple mentari IT1011152B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2316095A DE2316095A1 (de) 1973-03-30 1973-03-30 Verfahren zur herstellung integrierter schaltungen mit komplementaer-kanal-feldeffekttransistoren

Publications (1)

Publication Number Publication Date
IT1011152B true IT1011152B (it) 1977-01-20

Family

ID=5876571

Family Applications (1)

Application Number Title Priority Date Filing Date
IT49644/74A IT1011152B (it) 1973-03-30 1974-03-26 Procedimento per realizzare circui ti integrati con transistori ad ef fetto di campo con canali comple mentari

Country Status (13)

Country Link
US (1) US3919765A (it)
JP (1) JPS49131085A (it)
AT (1) AT339377B (it)
BE (1) BE813051A (it)
CA (1) CA1005175A (it)
CH (1) CH570042A5 (it)
DE (1) DE2316095A1 (it)
FR (1) FR2223838B1 (it)
GB (1) GB1443480A (it)
IT (1) IT1011152B (it)
LU (1) LU69729A1 (it)
NL (1) NL7404337A (it)
SE (1) SE386542B (it)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2450408A1 (de) * 1974-10-23 1976-04-29 Siemens Ag Schaltungsanordnung in einer komplementaer-chl-technik
US4043025A (en) * 1975-05-08 1977-08-23 National Semiconductor Corporation Self-aligned CMOS process for bulk silicon and insulating substrate device
AT380974B (de) * 1982-04-06 1986-08-11 Shell Austria Verfahren zum gettern von halbleiterbauelementen
JP3562588B2 (ja) * 1993-02-15 2004-09-08 株式会社半導体エネルギー研究所 半導体装置の製造方法
US6997985B1 (en) 1993-02-15 2006-02-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor, semiconductor device, and method for fabricating the same
JP3193803B2 (ja) * 1993-03-12 2001-07-30 株式会社半導体エネルギー研究所 半導体素子の作製方法
KR100226730B1 (ko) * 1997-04-24 1999-10-15 구본준 씨모스펫 및 그 제조방법
US6068685A (en) 1997-10-15 2000-05-30 Saes Pure Gas, Inc. Semiconductor manufacturing system with getter safety device
EP1028798B1 (en) 1997-10-15 2002-01-02 SAES PURE GAS, Inc. Gas purification system with safety device and method for purifying gases
US6236089B1 (en) 1998-01-07 2001-05-22 Lg Semicon Co., Ltd. CMOSFET and method for fabricating the same
US8481372B2 (en) * 2008-12-11 2013-07-09 Micron Technology, Inc. JFET device structures and methods for fabricating the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3673679A (en) * 1970-12-01 1972-07-04 Texas Instruments Inc Complementary insulated gate field effect devices
US3783052A (en) * 1972-11-10 1974-01-01 Motorola Inc Process for manufacturing integrated circuits on an alumina substrate
US3837071A (en) * 1973-01-16 1974-09-24 Rca Corp Method of simultaneously making a sigfet and a mosfet

Also Published As

Publication number Publication date
DE2316095A1 (de) 1974-10-10
FR2223838B1 (it) 1978-11-10
LU69729A1 (it) 1974-07-17
ATA217274A (de) 1977-02-15
JPS49131085A (it) 1974-12-16
CA1005175A (en) 1977-02-08
CH570042A5 (it) 1975-11-28
FR2223838A1 (it) 1974-10-25
NL7404337A (it) 1974-10-02
AT339377B (de) 1977-10-10
GB1443480A (en) 1976-07-21
SE386542B (sv) 1976-08-09
BE813051A (fr) 1974-07-15
US3919765A (en) 1975-11-18

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