IN2014KO00447A - - Google Patents

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Publication number
IN2014KO00447A
IN2014KO00447A IN447KO2014A IN2014KO00447A IN 2014KO00447 A IN2014KO00447 A IN 2014KO00447A IN 447KO2014 A IN447KO2014 A IN 447KO2014A IN 2014KO00447 A IN2014KO00447 A IN 2014KO00447A
Authority
IN
India
Prior art keywords
memory cell
cell array
bit line
read
memory cells
Prior art date
Application number
Other languages
English (en)
Inventor
Donald Albert Evans
Roy Rajiv
Veerabadra Chary Rasoju
Sahu Rahul
Original Assignee
Lsi Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Corp filed Critical Lsi Corp
Priority to IN447KO2014 priority Critical patent/IN2014KO00447A/en
Priority to US14/259,994 priority patent/US9177635B1/en
Publication of IN2014KO00447A publication Critical patent/IN2014KO00447A/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
IN447KO2014 2014-04-09 2014-04-09 IN2014KO00447A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IN447KO2014 IN2014KO00447A (ja) 2014-04-09 2014-04-09
US14/259,994 US9177635B1 (en) 2014-04-09 2014-04-23 Dual rail single-ended read data paths for static random access memories

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IN447KO2014 IN2014KO00447A (ja) 2014-04-09 2014-04-09

Publications (1)

Publication Number Publication Date
IN2014KO00447A true IN2014KO00447A (ja) 2015-10-16

Family

ID=54352786

Family Applications (1)

Application Number Title Priority Date Filing Date
IN447KO2014 IN2014KO00447A (ja) 2014-04-09 2014-04-09

Country Status (2)

Country Link
US (1) US9177635B1 (ja)
IN (1) IN2014KO00447A (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108564979B (zh) * 2018-04-28 2020-08-25 上海兆芯集成电路有限公司 单端读取电路
US11990179B2 (en) 2020-10-14 2024-05-21 Samsung Electronics Co., Ltd. Memory device using a plurality of supply voltages and operating method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2854305B2 (ja) * 1988-10-07 1999-02-03 株式会社日立製作所 半導体記憶装置と半導体記憶装置の動作方法
JP2005025863A (ja) * 2003-07-02 2005-01-27 Renesas Technology Corp 半導体記憶装置
US7508697B1 (en) * 2007-05-09 2009-03-24 Purdue Research Foundation Self-repairing technique in nano-scale SRAM to reduce parametric failures
US7830727B2 (en) 2008-06-09 2010-11-09 International Business Machines Corporation Apparatus and method for low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines
JP5278971B2 (ja) * 2010-03-30 2013-09-04 独立行政法人産業技術総合研究所 Ｓｒａｍ装置
US8279687B2 (en) * 2010-05-13 2012-10-02 International Business Machines Corporation Single supply sub VDD bit-line precharge SRAM and method for level shifting

Also Published As

Publication number Publication date
US9177635B1 (en) 2015-11-03

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