IL151958A0 - Housing assembly for an electronic component - Google Patents

Housing assembly for an electronic component

Info

Publication number
IL151958A0
IL151958A0 IL15195801A IL15195801A IL151958A0 IL 151958 A0 IL151958 A0 IL 151958A0 IL 15195801 A IL15195801 A IL 15195801A IL 15195801 A IL15195801 A IL 15195801A IL 151958 A0 IL151958 A0 IL 151958A0
Authority
IL
Israel
Prior art keywords
electronic component
housing assembly
housing
assembly
electronic
Prior art date
Application number
IL15195801A
Other languages
English (en)
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of IL151958A0 publication Critical patent/IL151958A0/xx

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01068Erbium [Er]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15151Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Packaging Frangible Articles (AREA)
IL15195801A 2000-03-31 2001-03-28 Housing assembly for an electronic component IL151958A0 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10016135A DE10016135A1 (de) 2000-03-31 2000-03-31 Gehäusebaugruppe für ein elektronisches Bauteil
PCT/DE2001/001165 WO2001075962A1 (de) 2000-03-31 2001-03-28 Gehäusebaugruppe für ein elektronisches bauteil

Publications (1)

Publication Number Publication Date
IL151958A0 true IL151958A0 (en) 2003-04-10

Family

ID=7637175

Family Applications (1)

Application Number Title Priority Date Filing Date
IL15195801A IL151958A0 (en) 2000-03-31 2001-03-28 Housing assembly for an electronic component

Country Status (13)

Country Link
US (1) US6713677B2 (xx)
EP (1) EP1269532A1 (xx)
JP (1) JP2003529933A (xx)
KR (1) KR20020086704A (xx)
CN (1) CN1199252C (xx)
AU (1) AU2001254609A1 (xx)
BR (1) BR0109645A (xx)
CA (1) CA2404032A1 (xx)
DE (2) DE10016135A1 (xx)
IL (1) IL151958A0 (xx)
MX (1) MXPA02009501A (xx)
TW (1) TW503535B (xx)
WO (1) WO2001075962A1 (xx)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6924496B2 (en) * 2002-05-31 2005-08-02 Fujitsu Limited Fingerprint sensor and interconnect
JP2004235324A (ja) * 2003-01-29 2004-08-19 Mitsubishi Electric Corp 表面実装型光部品
DE502004000545D1 (de) * 2003-02-13 2006-06-14 Infineon Technologies Ag Elektronisches bauteil mit halbleiterchip und verfahren zur herstellung desselben
DE102004006440B4 (de) * 2004-02-09 2009-05-28 Infineon Technologies Ag Sensorbauteil mit einem frei zugänglichen Sensorbereich und Verfahren zur Herstellung desselben
US7336500B1 (en) * 2004-09-03 2008-02-26 Altera Corporation Method and apparatus for encapsulating a printed circuit board
DE102005048396A1 (de) * 2005-10-10 2007-04-19 Siemens Ag Sensorbaugruppe
US8358816B2 (en) 2005-10-18 2013-01-22 Authentec, Inc. Thinned finger sensor and associated methods
CA2626526C (en) * 2005-10-18 2013-03-19 Authentec, Inc. Finger sensor including flexible circuit and associated methods
DE102007005630B4 (de) * 2007-02-05 2019-08-08 Infineon Technologies Ag Sensorchip-Modul und Verfahren zur Herstellung eines Sensorchip-Moduls
KR101702837B1 (ko) * 2010-07-22 2017-02-07 삼성전자주식회사 필름형 전자회로를 구비하는 전자제품의 케이스 구조물 및 그 제조방법
US8701267B2 (en) * 2010-11-05 2014-04-22 Authentec, Inc. Method of making a finger sensor package
CN102480872B (zh) * 2010-11-22 2014-12-10 富泰华工业(深圳)有限公司 壳体组件及其制造方法以及应用该壳体组件的电子装置
EP2973238B1 (en) * 2013-03-14 2019-08-07 X-Card Holdings, LLC Information carrying card for displaying one time passcodes, and method of making the same
EP2811427A1 (fr) * 2013-06-07 2014-12-10 Gemalto SA Procédé de fabrication d'un dispositif électronique anti-fissuration
DE202013008144U1 (de) * 2013-06-24 2013-09-26 Few Fahrzeugelektrikwerk Gmbh & Co. Kg Elektrische Verbindungsanordnung
CN104253884A (zh) * 2013-06-28 2014-12-31 深圳富泰宏精密工业有限公司 外壳及其制造方法
US9978719B2 (en) 2014-01-28 2018-05-22 Infineon Technologies Austria Ag Electronic component, arrangement and method

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH660551GA3 (xx) * 1982-12-27 1987-05-15
JPH02143466A (ja) * 1988-11-25 1990-06-01 Mitsubishi Electric Corp 半導体装置の製造方法
GB8911607D0 (en) * 1989-05-19 1989-07-05 Emi Plc Thorn A method of encapsulation for electronic devices and devices so encapsulated
US5477611A (en) * 1993-09-20 1995-12-26 Tessera, Inc. Method of forming interface between die and chip carrier
US5480842A (en) * 1994-04-11 1996-01-02 At&T Corp. Method for fabricating thin, strong, and flexible die for smart cards
US5663106A (en) * 1994-05-19 1997-09-02 Tessera, Inc. Method of encapsulating die and chip carrier
DE19519499B4 (de) * 1995-05-27 2005-05-25 Tesa Ag Thermoplastische Klebstoffolie und deren Verwendung
DE19520034A1 (de) * 1995-05-31 1996-12-05 Fraunhofer Ges Forschung Verfahren zur Herstellung elektrisch isolierender, mechanisch spannungsarmer und permanenter Verbindungen
DE19623826C2 (de) * 1996-06-14 2000-06-15 Siemens Ag Verfahren zur Herstellung eines Trägerelements für Halbleiterchips
US5867368A (en) * 1997-09-09 1999-02-02 Amkor Technology, Inc. Mounting for a semiconductor integrated circuit device
US5919329A (en) * 1997-10-14 1999-07-06 Gore Enterprise Holdings, Inc. Method for assembling an integrated circuit chip package having at least one semiconductor device
DE29722093U1 (de) * 1997-12-15 1998-06-10 Piorr Michael Plastikkarte
DE19803020C2 (de) * 1998-01-27 1999-12-02 Siemens Ag Chipkartenmodul für biometrische Sensoren
JPH11354686A (ja) * 1998-06-11 1999-12-24 Matsushita Electric Works Ltd 基板実装部品への充填材塗布構造
DE19828653A1 (de) * 1998-06-26 2000-01-05 Siemens Ag Chipmodul zum Einbau in einen Chipkartenträger sowie Verfahren zu dessen Herstellung
US6307258B1 (en) * 1998-12-22 2001-10-23 Silicon Bandwidth, Inc. Open-cavity semiconductor die package

Also Published As

Publication number Publication date
US6713677B2 (en) 2004-03-30
DE10016135A1 (de) 2001-10-18
DE10191266D2 (de) 2003-06-05
TW503535B (en) 2002-09-21
KR20020086704A (ko) 2002-11-18
AU2001254609A1 (en) 2001-10-15
JP2003529933A (ja) 2003-10-07
CA2404032A1 (en) 2001-10-11
BR0109645A (pt) 2003-03-18
MXPA02009501A (es) 2003-05-14
US20030090007A1 (en) 2003-05-15
CN1421044A (zh) 2003-05-28
WO2001075962A1 (de) 2001-10-11
CN1199252C (zh) 2005-04-27
EP1269532A1 (de) 2003-01-02

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