IL143337A0 - Component decoder and method thereof in mobile communication system - Google Patents

Component decoder and method thereof in mobile communication system

Info

Publication number
IL143337A0
IL143337A0 IL14333700A IL14333700A IL143337A0 IL 143337 A0 IL143337 A0 IL 143337A0 IL 14333700 A IL14333700 A IL 14333700A IL 14333700 A IL14333700 A IL 14333700A IL 143337 A0 IL143337 A0 IL 143337A0
Authority
IL
Israel
Prior art keywords
llr
path
pes
cells
time
Prior art date
Application number
IL14333700A
Other languages
English (en)
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of IL143337A0 publication Critical patent/IL143337A0/xx

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4138—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions
    • H03M13/4146—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions soft-output Viterbi decoding according to Battail and Hagenauer in which the soft-output is determined using path metric differences along the maximum-likelihood path, i.e. "SOVA" decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
    • H03M13/4184—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using register-exchange
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6577—Representation or format of variables, register sizes or word-lengths and quantization
    • H03M13/6583—Normalization other than scaling, e.g. by subtraction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Artificial Intelligence (AREA)
  • Error Detection And Correction (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
IL14333700A 1999-10-05 2000-10-05 Component decoder and method thereof in mobile communication system IL143337A0 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR19990042924 1999-10-05
KR19990043118 1999-10-06
PCT/KR2000/001109 WO2001026257A1 (en) 1999-10-05 2000-10-05 Component decoder and method thereof in mobile communication system

Publications (1)

Publication Number Publication Date
IL143337A0 true IL143337A0 (en) 2002-04-21

Family

ID=26636175

Family Applications (2)

Application Number Title Priority Date Filing Date
IL14333700A IL143337A0 (en) 1999-10-05 2000-10-05 Component decoder and method thereof in mobile communication system
IL143337A IL143337A (en) 1999-10-05 2001-05-23 Decodes a component and method for it in a mobile communication system

Family Applications After (1)

Application Number Title Priority Date Filing Date
IL143337A IL143337A (en) 1999-10-05 2001-05-23 Decodes a component and method for it in a mobile communication system

Country Status (14)

Country Link
US (1) US6697443B1 (zh)
EP (1) EP1135877B1 (zh)
JP (1) JP3640924B2 (zh)
KR (1) KR100350502B1 (zh)
CN (1) CN1168237C (zh)
AT (1) ATE385629T1 (zh)
AU (1) AU762877B2 (zh)
BR (1) BR0007197A (zh)
CA (1) CA2352206C (zh)
DE (1) DE60037963T2 (zh)
DK (1) DK1135877T3 (zh)
ES (1) ES2301492T3 (zh)
IL (2) IL143337A0 (zh)
WO (1) WO2001026257A1 (zh)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020110206A1 (en) * 1998-11-12 2002-08-15 Neal Becker Combined interference cancellation with FEC decoding for high spectral efficiency satellite communications
US7127664B2 (en) * 2000-09-18 2006-10-24 Lucent Technologies Inc. Reconfigurable architecture for decoding telecommunications signals
US7020214B2 (en) * 2000-09-18 2006-03-28 Lucent Technologies Inc. Method and apparatus for path metric processing in telecommunications systems
US6865710B2 (en) 2000-09-18 2005-03-08 Lucent Technologies Inc. Butterfly processor for telecommunications
EP1220455A1 (en) * 2000-12-29 2002-07-03 Motorola, Inc. Viterbi decoder, method and unit therefor
US20030067998A1 (en) * 2001-07-19 2003-04-10 Matsushita Electric Industrial Co., Ltd. Method for evaluating the quality of read signal and apparatus for reading information
KR100487183B1 (ko) * 2002-07-19 2005-05-03 삼성전자주식회사 터보 부호의 복호 장치 및 방법
US7173985B1 (en) * 2002-08-05 2007-02-06 Altera Corporation Method and apparatus for implementing a Viterbi decoder
KR100515472B1 (ko) * 2002-10-15 2005-09-16 브이케이 주식회사 채널 부호화, 복호화 방법 및 이를 수행하는 다중 안테나무선통신 시스템
US7797618B2 (en) * 2004-12-30 2010-09-14 Freescale Semiconductor, Inc. Parallel decoder for ultrawide bandwidth receiver
JP4432781B2 (ja) * 2005-01-17 2010-03-17 株式会社日立製作所 誤り訂正復号器
US7571369B2 (en) * 2005-02-17 2009-08-04 Samsung Electronics Co., Ltd. Turbo decoder architecture for use in software-defined radio systems
US7603613B2 (en) * 2005-02-17 2009-10-13 Samsung Electronics Co., Ltd. Viterbi decoder architecture for use in software-defined radio systems
KR100800853B1 (ko) 2005-06-09 2008-02-04 삼성전자주식회사 통신 시스템에서 신호 수신 장치 및 방법
US20070006058A1 (en) * 2005-06-30 2007-01-04 Seagate Technology Llc Path metric computation unit for use in a data detector
US7764741B2 (en) * 2005-07-28 2010-07-27 Broadcom Corporation Modulation-type discrimination in a wireless communication network
US7860194B2 (en) * 2005-11-11 2010-12-28 Samsung Electronics Co., Ltd. Method and apparatus for normalizing input metric to a channel decoder in a wireless communication system
US20070268988A1 (en) * 2006-05-19 2007-11-22 Navini Networks, Inc. Method and system for optimal receive diversity combining
US7925964B2 (en) * 2006-12-22 2011-04-12 Intel Corporation High-throughput memory-efficient BI-SOVA decoder architecture
US7716564B2 (en) * 2007-09-04 2010-05-11 Broadcom Corporation Register exchange network for radix-4 SOVA (Soft-Output Viterbi Algorithm)
US8238475B2 (en) 2007-10-30 2012-08-07 Qualcomm Incorporated Methods and systems for PDCCH blind decoding in mobile communications
US20090132894A1 (en) * 2007-11-19 2009-05-21 Seagate Technology Llc Soft Output Bit Threshold Error Correction
US8127216B2 (en) 2007-11-19 2012-02-28 Seagate Technology Llc Reduced state soft output processing
US8401115B2 (en) * 2008-03-11 2013-03-19 Xilinx, Inc. Detector using limited symbol candidate generation for MIMO communication systems
US8413031B2 (en) * 2008-12-16 2013-04-02 Lsi Corporation Methods, apparatus, and systems for updating loglikelihood ratio information in an nT implementation of a Viterbi decoder
EP2442451A1 (en) * 2009-08-18 2012-04-18 TELEFONAKTIEBOLAGET LM ERICSSON (publ) Soft output Viterbi algorithm method and decoder
TWI394378B (zh) * 2010-05-17 2013-04-21 Novatek Microelectronics Corp 維特比解碼器及寫入與讀取方法
CN103701475B (zh) * 2013-12-24 2017-01-25 北京邮电大学 移动通信系统中8比特运算字长Turbo码的译码方法
TWI592937B (zh) * 2016-07-05 2017-07-21 大心電子（英屬維京群島）股份有限公司 解碼方法、記憶體儲存裝置及記憶體控制電路單元
CN108491346A (zh) * 2018-03-23 2018-09-04 江苏沁恒股份有限公司 一种bmc解码方法
KR20220051750A (ko) * 2020-10-19 2022-04-26 삼성전자주식회사 장치간 물리적 인터페이스의 트레이닝을 위한 장치 및 방법

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4583078A (en) * 1984-11-13 1986-04-15 Communications Satellite Corporation Serial Viterbi decoder
DE3910739C3 (de) * 1989-04-03 1996-11-21 Deutsche Forsch Luft Raumfahrt Verfahren zum Verallgemeinern des Viterbi-Algorithmus und Einrichtungen zur Durchführung des Verfahrens
US5295142A (en) * 1989-07-18 1994-03-15 Sony Corporation Viterbi decoder
KR950005860B1 (ko) * 1990-12-22 1995-05-31 삼성전자주식회사 바이터비 복호방법
JPH05335972A (ja) * 1992-05-27 1993-12-17 Nec Corp ビタビ復号器
US5341387A (en) * 1992-08-27 1994-08-23 Quantum Corporation Viterbi detector having adjustable detection thresholds for PRML class IV sampling data detection
JPH08307283A (ja) * 1995-03-09 1996-11-22 Oki Electric Ind Co Ltd 最尤系列推定器及び最尤系列推定方法
JP2907090B2 (ja) 1996-01-12 1999-06-21 日本電気株式会社 信頼度生成装置およびその方法
US5995562A (en) * 1995-10-25 1999-11-30 Nec Corporation Maximum-likelihood decoding
GB2309867A (en) * 1996-01-30 1997-08-06 Sony Corp Reliability data in decoding apparatus
JPH09232973A (ja) 1996-02-28 1997-09-05 Sony Corp ビタビ復号器
JPH09232972A (ja) 1996-02-28 1997-09-05 Sony Corp ビタビ復号器
US6212664B1 (en) * 1998-04-15 2001-04-03 Texas Instruments Incorporated Method and system for estimating an input data sequence based on an output data sequence and hard disk drive incorporating same
JPH11355150A (ja) * 1998-06-09 1999-12-24 Sony Corp パンクチャドビタビ復号方法
US6236692B1 (en) * 1998-07-09 2001-05-22 Texas Instruments Incorporated Read channel for increasing density in removable disk storage devices
JP3196835B2 (ja) * 1998-07-17 2001-08-06 日本電気株式会社 ビタビ復号法及びビタビ復号器
US6405342B1 (en) * 1999-09-10 2002-06-11 Western Digital Technologies, Inc. Disk drive employing a multiple-input sequence detector responsive to reliability metrics to improve a retry operation

Also Published As

Publication number Publication date
AU7690900A (en) 2001-05-10
ATE385629T1 (de) 2008-02-15
EP1135877B1 (en) 2008-02-06
CN1327653A (zh) 2001-12-19
BR0007197A (pt) 2001-09-04
EP1135877A1 (en) 2001-09-26
DK1135877T3 (da) 2008-06-09
KR20010050871A (ko) 2001-06-25
IL143337A (en) 2008-08-07
ES2301492T3 (es) 2008-07-01
CA2352206C (en) 2005-12-06
DE60037963D1 (de) 2008-03-20
CA2352206A1 (en) 2001-04-12
US6697443B1 (en) 2004-02-24
WO2001026257A1 (en) 2001-04-12
KR100350502B1 (ko) 2002-08-28
CN1168237C (zh) 2004-09-22
JP2003511895A (ja) 2003-03-25
JP3640924B2 (ja) 2005-04-20
EP1135877A4 (en) 2004-04-07
AU762877B2 (en) 2003-07-10
DE60037963T2 (de) 2009-01-29

Similar Documents

Publication Publication Date Title
IL143337A0 (en) Component decoder and method thereof in mobile communication system
JP3288683B2 (ja) 変形された逆追跡方式の２段軟出力ビタビアルゴリズム復号化器
CN1808912B (zh) 纠错译码器
US6516444B1 (en) Turbo-code decoder
US20050193308A1 (en) Turbo decoder and turbo interleaver
US5454014A (en) Digital signal processor
US8250448B1 (en) Method of and apparatus for implementing a decoder
US20070113161A1 (en) Cascaded radix architecture for high-speed viterbi decoder
US7219290B2 (en) Turbo decoder and turbo decoding method and storage medium where the method is stored
Berrou et al. An IC for turbo-codes encoding and decoding
US20040120427A1 (en) Branch metric unit duplication for high speed decoder FPGA implementation
US7120851B2 (en) Recursive decoder for switching between normalized and non-normalized probability estimates
KR101760462B1 (ko) 터보 복호기 및 ldpc 복호기를 위한 다중 복호 방법 및 그 장치
El-Dib et al. Memoryless viterbi decoder
RU2247471C2 (ru) Компонентный декодер и способ декодирования в системе мобильной связи
Saouter et al. Fast soft-output Viterbi decoding for duo-binary turbo codes
RU2001115087A (ru) Компонентный декодер и способ декодирования в системе мобильной связи
Devi et al. An Energy-Efficient Lut-Log-Bcjr Architecture Using Constant Log Bcjr Algorithm
Peng et al. The Construction and Viterbi Decoding of New (2k, k, l) Convolutional Codes
WO2001013524A1 (en) Viterbi-decoder system with trace-back implementation
KR19990035420A (ko) 트렐리스 디코더의 브랜치 메트릭 계산 장치
KR20030015903A (ko) 래딕스-4 방식의 고속 터보 맵 복호장치 및 그 방법
KR19980075618A (ko) 트렐리스 디코더의 가산 비교 선택 장치

Legal Events

Date Code Title Description
FF Patent granted
KB Patent renewed