HRP20200393T1 - Transformiranje nekontinuiranih specifikatora instrukcija u kontinuirane specifikatore instrukcija - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
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- G06F8/40—Transformation of program code
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30138—Extension of register space, e.g. register cache
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
- G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/342—Extension of operand address space
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
- G06F9/45516—Runtime code conversion or optimisation
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Claims (20)
1. Računalni programski proizvod za emulaciju instrukcija u računalnom okruženju, računalni programski proizvod koji obuhvaća:
računalno čitljivi medij za skladištenje koji se može čitati procesorskim krugom i koji skladišti instrukcije za izvršenje pomoću procesorskog kruga za izvođenje metode koja obuhvaća:
određivanje iz prve instrukcije definirane za prvu arhitekturu računala da prva instrukcija uključuje nekontinuirani specifikator operanda registra koji ima prvi dio i drugi dio, koji nije kontinuiran sa prvim dijelom;
dobivanje (750) nekontinuiranog specifikatora operanda registra iz prve instrukcije obuhvaćajući dobivanje prvog dijela iz prvog polja (V1) prve instrukcije i drugog dijela iz drugog polja (RXB – eng. register extension bit) prve instrukcije, prvog polja odvojenog od drugog polja najmanje jednim međupoljem, pri čemu dio operacijskog koda prve instrukcije utvrđuje prvo polje i drugo polje koja se primjenjuju za označavanje nekontinuiranog specifikatora;
generiranje (752) kontinuiranog specifikatora operanda registra primjenom prvog dijela i drugog dijela dobivenih iz prve instrukcije, generiranje primjenom jednog ili više pravila skladištenih u memoriji ili vanjskom skladištu ovisno od formata instrukcije utvrđenog pomoću operacijskog koda prve instrukcije;
primjenu (754) kontinuiranog specifikatora operanda registra umjesto nekontinuiranog specifikatora operanda registra za naznačavanje resursa koji se treba primijeniti u izvršavanju druge instrukcije, druge instrukcije definirane za drugu arhitekturu računala različitu od prve arhitekture računala i koja emulira funkciju prve instrukcije; i
izvršavanje druge instrukcije za emulaciju funkcije prve instrukcije, izvršavanje primjenom resursa naznačenog od strane kontinuiranog specifikatora operanda registra bez daljeg razmatranja nekontinuiranog specifikatora operanda registra.
2. Računalni programski proizvod prema patentnom zahtjevu 1, pri čemu prvi dio uključuje prvi jedan ili više bitova, a drugi dio uključuje drugi jedan ili više bitova, a generiranje obuhvaća spajanje drugog jednog ili više bitova sa prvim jednim ili više bitova da bi se formirao kontinuirani specifikator operanda registra, pri čemu su drugi jedan ili više bitova najznačajniji bitovi kontinuiranog specifikatora operanda registra.
3. Računalni programski proizvod prema patentnom zahtjevu 2, pri čemu prvo polje ima položaj operanda povezan s njim, a drugi jedan ili više bitova su podskup velikog broja bitova drugog polja, pri čemu dobivanje obuhvaća odabir drugog jednog ili više bitova iz velikog broja bitova drugog polja na osnovu položaja operanda prvog polja.
4. Računalni programski proizvod prema patentnom zahtjevu 3, pri čemu položaj operanda prvog polja je kao prvi operand i pri čemu su drugi jedan ili više bitova odabrani sa sasvim lijeve lokacije drugog polja.
5. Računalni programski proizvod prema bilo kojem prethodnom patentnom zahtjevu, pri čemu se prvo polje sastoji od polja registra, drugo polje se sastoji od polja proširenja, prvi dio se sastoji od velikog broja bitova iz polja registra, drugi dio se sastoji od bita iz polja proširenja na lokaciji instrukcije koja odgovara polju registra, a generiranje obuhvaća spajanje bita iz polja proširenja s bitovima iz polja registra radi osiguravanja kontinuiranog specifikatora operanda registra.
6. Računalni programski proizvod iz bilo kog prethodnog patentnog zahtjeva, pri čemu primjena kontinuiranog specifikatora operanda registra za naznačavanje resursa uključuje primjenu kontinuiranog specifikatora operanda registra za mapiranje u registar koji će se primjenjivati pomoću druge instrukcije.
7. Računalni programski proizvod prema patentnom zahtjevu 6, pri čemu registar mapiran pomoću kontinuiranog specifikatora operanda registra ima istu vrijednost kao kontinuirani specifikator operanda registra.
8. Računalni programski proizvod prema patentnom zahtjevu 6, pri čemu registar mapiran pomoću kontinuiranog specifikatora operanda registra ima različitu vrijednost od kontinuiranog specifikatora operanda registra.
9. Računalni programski proizvod prema bilo kojem prethodnom patentnom zahtjevu, pri čemu prva arhitektura računala uključuje skup instrukcija koji sadrži prve instrukcije koje imaju polja registra za pristup pododjeljku registarskog prostora prve arhitekture računala i koje imaju druge instrukcije koje imaju nekontinuirana polja registra za pristupanje pododjeljku i preostalim pododjeljcima registarskog prostora, prve instrukcije onemogućene za pristup preostalim pododjeljcima.
10. Računalni programski proizvod prema patentnom zahtjevu 1, pri čemu prvo polje se sastoji od polja registra, drugo polje se sastoji od polja proširenja, prvi dio se sastoji od velikog broja bitova iz polja registra, drugi dio se sastoji od bita iz polja proširenja na lokaciji instrukcije koja odgovara polju registra, a generiranje obuhvaća spajanje bita iz polja proširenja s bitovima iz polja registra radi osiguravanja kontinuiranog specifikatora operanda registra, i koje dalje obuhvaća:
dobivanje, pomoću procesora, iz prve instrukcije, još jednog nekontinuiranog specifikatora operanda registra, još jednog nekontinuiranog specifikatora operanda registra koji ima još jedan prvi dio i još jedan drugi dio, pri čemu dobivanje obuhvaća dobivanje još jednog prvog dijela iz još jednog prvog polja instrukcije i još jednog drugog dijela iz još jednog bita iz polja proširenja, još jednog prvog polja odvojenog od prvog polja i polja proširenja;
generiranje još jednog kontinuiranog specifikatora operanda registra primjenjujući još jedan prvi dio i još jedan bit, generiranje primjenjujući jedno ili više pravila zasnovanih na operacijskom kodu prve instrukcije; i
primjenu još jednog kontinuiranog specifikatora operanda registra da naznači resurs koji će se primjenjivati u izvršavanju druge instrukcije.
11. Računalni sistem za emulaciju instrukcija u računalnom okruženju, računalni sistem koji sadrži:
memoriju; i
procesor u komunikaciji sa memorijom, pri čemu je računalni sistem konfiguriran da izvodi metodu, pri čemu navedena metoda obuhvaća:
određivanje iz prve instrukcije definirane za prvu arhitekturu računala da prva instrukcija uključuje nekontinuirani specifikator operanda registra koji ima prvi dio i drugi dio, koji nije kontinuiran sa prvim dijelom; dobivanje nekontinuiranog specifikatora operanda registra iz prve instrukcije obuhvaćajući dobivanje (750) prvog dijela iz prvog polja (V1) prve instrukcije i drugog dijela iz drugog polja (RXB) prve instrukcije, prvog polja odvojenog od drugog polja najmanje jednim međupoljem, pri čemu dio operacijskog koda prve instrukcije utvrđuje prvo polje i drugo polje primijenjene za označavanje nekontinuiranog specifikatora;
generiranje (752) kontinuiranog specifikatora operanda registra primjenjujući prvi dio i drugi dio dobivene iz prve instrukcije, generiranje primjenjujući jedno ili više pravila skladištenih u memoriji ili vanjskom skladištu ovisno od formata instrukcije utvrđenog pomoću operacijskog koda prve instrukcije;
primjenu (754) kontinuiranog specifikatora operanda registra umjesto nekontinuiranog specifikatora operanda registra za naznačavanje resursa koji će se primjenjivati u izvršavanju druge instrukcije, pri čemu je druga instrukcija definirana za drugu arhitekturu računala različitu od prve arhitekture računala i koja emulira funkciju prve instrukcije; i
izvršavanje druge instrukcije za emulaciju funkcije prve instrukcije, izvršavanje primjenom resursa naznačenog od strane kontinuiranog specifikatora operanda registra bez daljeg razmatranja nekontinuiranog specifikatora operanda registra.
12. Računalni sistem prema patentnom zahtjevu 11, pri čemu prvi dio uključuje prvi jedan ili više bitova, a drugi dio uključuje drugi jedan ili više bitova, a generiranje obuhvaća spajanje drugog jednog ili više bitova sa prvim jednim ili više bitova kako bi formirali kontinuirani specifikator operanda registra, pri čemu su drugi jedan ili više bitova najznačajniji bitovi kontinuiranog specifikatora operanda registra.
13. Računalni sistem prema patentnom zahtjevu 12, pri čemu prvo polje ima poziciju operanda povezanu sa njim, a drugi jedan ili više bitova su drugi podskup velikog broja bitova drugog polja i pri čemu dobivanje uključuje odabir drugog jednog ili više bitova od velikog broja bitova drugog polja na osnovu položaja operanda prvog polja.
14. Računalni sistem prema patentnom zahtjevu 13, pri čemu je položaj operanda prvog polja kao prvi operand i gdje su drugi jedan ili više bitova odabrani sa sasvim lijeve lokacije drugog polja.
15. Računalni sistem prema bilo kojem od patentnih zahtjeva 11 do 14, pri čemu prvo polje sadrži polja registra, drugo polje sadrži polje proširenja, prvi dio sadrži veliki broj bitova iz polja registra, drugi dio sadrži bit iz polja proširenja na lokaciji koja odgovara polju registra, a generiranje obuhvaća spajanje bita iz polja proširenja s bitovima iz polja registra radi dobivanja kontinuiranog specifikatora operanda registra.
16. Računalni sistem prema bilo kojem od patentnih zahtjeva 11 do 15, pri čemu primjena kontinuiranog specifikatora operanda registra za naznačavanje resursa uključuje primjenu kontinuiranog specifikatora operanda registra da bi se mapirao registar koji će se primjenjivati pomoću druge instrukcije.
17. Računalni sistem prema patentnom zahtjevu 16, pri čemu registar mapiran pomoću kontinuiranog specifikatora operanda registra ima jedno od: istu vrijednost kao kontinuirani specifikator operanda registra ili ima drugačiju vrijednost od kontinuiranog specifikatora operanda registra.
18. Metoda emulacije instrukcija u računalnom okruženju, pri čemu metoda obuhvaća:
određivanje iz prve instrukcije definirane za prvu arhitekturu računala da prva instrukcija uključuje nekontinuirani specifikator operanda registra koji ima prvi dio i drugi dio, koji nije kontinuiran sa prvim dijelom;
dobivanje (750) nekontinuiranog specifikatora operanda registra iz prve instrukcije obuhvaćajući dobivanje prvog dijela iz prvog polja (V1) prve instrukcije i drugog dijela iz drugog polja (RXB) prve instrukcije, prvog polja odvojenog od drugog polja najmanje jednim međupoljem, pri čemu dio operacijskog koda prve instrukcije utvrđuje prvo polje i drugo polje koja se primjenjuju za označavanje nekontinuiranog specifikatora;
generiranje (752) kontinuiranog specifikatora operanda registra primjenjujući prvi dio i drugi dio dobivene iz prve instrukcije, generiranje primjenjujući jedno ili više pravila skladištenih u memoriji ili vanjskom skladištu u zavisnosti od formata instrukcije utvrđenog pomoću operacijskog koda prve instrukcije;
primjenu (754) kontinuiranog specifikatora operanda registra umjesto nekontinuiranog specifikatora operanda registra za naznačavanje resursa koji će se primjenjivati u izvršavanju druge instrukcije, druge instrukcije definirane za drugu arhitekturu računala različitu od prve arhitekture računala i koja emulira funkciju prve instrukcije; i
izvršavanje druge instrukcije za emulaciju funkcije prve instrukcije, izvršavanje primjenom resursa naznačenog od strane kontinuiranog specifikatora operanda registra bez daljeg razmatranja nekontinuiranog specifikatora operanda registra.
19. Metoda prema patentnom zahtjevu 18, pri čemu prvi dio uključuje prvi jedan ili više bitova, a drugi dio uključuje drugi jedan ili više bitova, a generiranje obuhvaća spajanje drugog jednog ili više bitova sa prvim jednim ili više bitova da bi se formirao kontinuirani specifikator operanda registra, pri čemu su drugi jedan ili više bitova najznačajniji bitovi kontinuiranog specifikatora operanda registra.
20. Metoda prema patentnom zahtjevu 18 ili 19, pri čemu prvo polje sadrži polje registra, drugo polje sadrži polje proširenja, prvi dio sadrži veliki broj bitova iz polja registra, drugi dio sadrži bit iz polja proširenja na lokaciji koja odgovara polju registra i generiranje obuhvaća spajanje bita iz polja proširenja s bitovima iz polja registra radi dobivanja kontinuiranog specifikatora operanda registra.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US13/421,657 US9280347B2 (en) | 2012-03-15 | 2012-03-15 | Transforming non-contiguous instruction specifiers to contiguous instruction specifiers |
PCT/IB2012/056436 WO2013136144A1 (en) | 2012-03-15 | 2012-11-15 | Transforming non-contiguous instruction specifiers to contiguous instruction specifiers |
EP12871580.2A EP2769301B1 (en) | 2012-03-15 | 2012-11-15 | Transforming non-contiguous instruction specifiers to contiguous instruction specifiers |
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US (2) | US9280347B2 (hr) |
EP (1) | EP2769301B1 (hr) |
JP (1) | JP6108362B2 (hr) |
KR (1) | KR101643065B1 (hr) |
CN (1) | CN104169877B (hr) |
AU (1) | AU2012373735B2 (hr) |
BR (1) | BR112014022638B1 (hr) |
CA (1) | CA2867115C (hr) |
DK (1) | DK2769301T3 (hr) |
ES (1) | ES2779033T3 (hr) |
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HR (1) | HRP20200393T1 (hr) |
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WO2012103359A2 (en) | 2011-01-27 | 2012-08-02 | Soft Machines, Inc. | Hardware acceleration components for translating guest instructions to native instructions |
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US9459867B2 (en) | 2012-03-15 | 2016-10-04 | International Business Machines Corporation | Instruction to load data up to a specified memory boundary indicated by the instruction |
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