US20040215924A1 - Analyzing stored data - Google Patents
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- US20040215924A1 US20040215924A1 US10/426,052 US42605203A US2004215924A1 US 20040215924 A1 US20040215924 A1 US 20040215924A1 US 42605203 A US42605203 A US 42605203A US 2004215924 A1 US2004215924 A1 US 2004215924A1
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- 238000000034 method Methods 0.000 claims abstract description 97
- 238000013500 data storage Methods 0.000 claims abstract description 37
- 230000000295 complement effect Effects 0.000 claims description 11
- 238000003860 storage Methods 0.000 description 8
- 241000283690 Bos taurus Species 0.000 description 5
- 238000004590 computer program Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
- G06F9/30109—Register structure having multiple operands in a single register
Definitions
- This disclosure relates to analyzing data in data storage.
- Software code may contain instructions to locate specific data in data storage (e.g., memory such as volatile memory, and non-volatile memory, and the like).
- software code may include instructions to search for a value in memory and to specify its location. Typically, this is accomplished by comparing each value in the data storage to the value to be searched until the location containing the value is determined.
- Other software code may contain instructions to validate extrema values such as a maximum value or a minimum value in the data storage.
- Each element in the array, y is compared to the maximum value, MAX, one at a time.
- FIG. 1 is a flowchart of a process for locating a target value in data storage.
- FIG. 2 is a diagram of registers used in locating the target value in the data storage.
- FIG. 3 is a flow chart of a process for verifying an initial extrema value in the data storage.
- FIG. 4 is a diagram of registers used in verifying the initial extrema value for nonnegative integer values in the data storage.
- FIG. 5 is a flow chart of a process for verifying an initial maximum value for negative integer values in the data storage.
- FIG. 6 is a diagram of registers used in verifying the initial maximum value for negative integer values in the data storage.
- FIG. 7 is a block diagram of a computer system on which the processes of FIGS. 1 and 3 may be implemented.
- a process 10 may be used to locate a target value in a data storage location (not shown). Instead of comparing each value in an element within the data storage location one-at-a-time with the target value, process 10 searches for the target value N elements-at-a-time (N>0) and as will be described below process 10 saves processing time.
- Each element for example, may include 8-bits or 16-bits.
- the target value may be a value required and requested during the execution of a program (e.g., from a compiler), an arbitrary value, or a user chosen value.
- Process 10 may load ( 12 ) the target value into each element 30 of a first register 32 having N (N>0) elements.
- each element may be 8 bits and a target value of 3 may be loaded into 8 elements of first register 32 , a 64-bit register.
- process 10 may load ( 12 ) the target value using a single computer instruction (e.g., in this embodiment, mux).
- Process 10 may load ( 14 ) the first N elements of the storage location into a second register 34 . This can be done, for example, using one 8-byte load or eight 8-bit loads.
- Process 10 may compare ( 16 ) each element of first register 32 with its corresponding element in second register 34 .
- Process 10 may indicate ( 18 ) which elements match the target value by placing a nonzero value into a corresponding element of a third register 36 .
- Process 10 may place a zero value into the corresponding value of the third register if there is no match.
- the corresponding elements of third register 36 may be set to hexadecimal value 0xff to indicate a match and 0x00 to indicate no match.
- process 10 compares ( 16 ) and indicates ( 18 ) using a single computer instruction (e.g., in this embodiment, pcmp.eq).
- Process 10 may obtain ( 20 ) the complement of third register 36 and place resulting corresponding values into a fourth register 38 .
- process 10 obtains ( 20 ) the complement using a single computer instruction (e.g., in this embodiment, negate). In other embodiments, ( 20 ) may be skipped.
- Process 10 may load ( 22 ) a value into a position field 40 indicating if and where there is an element in fourth register 38 having a zero value.
- a value from “0” to “N ⁇ ” may be loaded into a position field 40 to indicate a match and the position (described below) of the element having the matching value.
- a value of “N” may be loaded into position field 40 to indicate no match.
- Each register (first register 32 , second register 34 , third register 36 , and fourth register 38 ) stores values in a little-endian format, i.e., the least-significant (“right-most”) element is the least significant.
- the least significant element has a value of “1” and the most significant element has a value of “4.”
- the least significant value has a position value of “0” and the most significant value has a position value of “7.”
- the position value of the element of fourth register 38 containing a zero value is position value “5.”
- a value of “5” is placed in position field 40 .
- process 10 may load ( 22 ) into position field 40 the position value of the least significant element in fourth register 38 having a zero value.
- process may load ( 22 ) a position field value using a single computer instruction (e.g., in this embodiment, czx1.r).
- a single computer instruction e.g., in this embodiment, czx1.r
- Process 10 may determine ( 24 ) if there is a match by reading position value 40 . If there are no matches (i.e., a value of “N” in field 40 , e.g., a value of “8” when there are eight elements), process 10 may load ( 26 ) the next N elements (following the first N elements) of the data storage location into second register 34 , and process 10 may compare ( 16 ) each field of the second register with first register 32 , as above.
- a value of “N” in field 40 e.g., a value of “8” when there are eight elements
- RVAL corresponds to first register 32
- RCONT corresponds to second register 34
- RRES corresponds to third register 36
- NR corresponds to fourth register 38
- RIND corresponds to position field 40 .
- other code or even hardware may be used to implement process 10 .
- a process 60 searches data storage and verifies that an initial extrema value, such as a maximum value or a minimum value, is valid.
- Process 60 may load ( 62 ) an initial extrema value into each element of a first register 82 having N (N>0) elements, e.g., eight elements (FIG. 4).
- process 60 may load ( 62 ) an initial extrema value using a single computer instruction (e.g., in this embodiment, mux).
- the initial extrema value is a guess of the actual extrema value for the data storage.
- Process 60 may be used to determine if that guess is correct.
- the initial extrema value can come from a user input or the initial extrema value can be determined by a compiler via a compiler optimization setting. For example, a compiler, prior to executing process 60 , may read the first 10% of the values in the data storage and may take the extrema from those values. The compiler may then process the remaining 90% of the data storage elements using process 60 .
- Process 60 may load ( 64 ) N (N>0) elements from the data storage into a second register 84 .
- Process 60 may compare ( 66 ) each element's value in second register 84 to the initial extrema value loaded in first register 82 .
- Process 60 may load ( 68 ) the extrema value between the first register and the second register into third register 86 . For example, if the initial extrema value is a maximum, the larger of the first register element and the second register element is placed in a corresponding third register element. If the initial extrema value is a minimum, the smaller of the first register element and the second register element is placed in a corresponding third register element.
- process 60 compares ( 66 ) and loads ( 68 ) third register 86 using a computer instruction (e.g., in this embodiment, pmax) if the initial extrema value is a maximum and another computer instruction (e.g., in this embodiment, pmin) is used if the initial extrema value is a minimum.
- a computer instruction e.g., in this embodiment, pmax
- another computer instruction e.g., in this embodiment, pmin
- Process 60 may determine ( 70 ) if the initial extrema value is valid by comparing elements from third register 86 to the initial extrema value. If all values match the initial extrema value, then the initial extrema value is valid. If at least one value in the third register does not match the initial extrema value, the initial extrema value is invalid.
- process 60 may load ( 72 ) the next N (N>0) elements into second register 84 . If the initial extrema value is invalid, process 60 ends.
- RMAX corresponds to first register 82
- RVAL corresponds to second register 84
- RRES corresponds to third register 86 .
- Process 60 may be modified into a process 80 to account for nonnegative integers.
- Actions 62 , 64 and 66 in process 80 are the same as actions 62 , 64 and 66 of process 60 (FIG. 3).
- process 80 may load ( 88 ) a hexadecimal value of 0xff in the corresponding element of a third register 86 .
- process 80 may load ( 88 ) a hexadecimal value of 0x00 into the corresponding element of third register 86 .
- the initial extrema value is a maximum, process 80 may determine that the initial extrema value is valid if values in first register 82 are greater than or equal to values in second register 84 . If the extrema value is a minimum, process 80 determines that the initial extrema value is valid if values in first register 82 are less than or equal to the values in second register 84 .
- process 80 may compare ( 88 ) the values using a single computer instruction (e.g., in this embodiment, pcmpl.gt).
- Process 80 may load ( 90 ) into an invalid count field 94 a count of the elements in third register 86 where the initial extrema value is invalid (i.e., elements having a hexadecimal value of 0xff).
- process 80 may load ( 90 ) invalid count field 94 by using a single computer instruction (e.g., in this embodiment, popcnt).
- Process 80 may determine ( 92 ) if the initial extrema value is invalid by determining if there is a nonzero value in invalid count field 94 .
- process 80 may load ( 72 ) the next N (N>0) elements into second register 84 . If the initial extrema value is invalid (i.e., invalid count field 94 contains a nonzero value), process 80 ends.
- RVAL corresponds to second register 84
- RRES corresponds to third register 86
- RCNT corresponds to invalid count field 94 .
- FIG. 7 shows a computer 100 for using processes 10 , 60 and 80 .
- Computer 100 includes a processor 102 , a memory 104 , and a storage medium 106 (e.g., hard disk).
- Storage medium 106 stores operating system 110 , data storage 112 and registers 116 , and computer instructions 114 which are executed by processor 102 out of memory 104 to perform processes 10 , 60 and 80 .
- Processes 10 , 60 and 80 are not limited to use with the hardware and software of FIG. 7; they may find applicability in any computing or processing environment and with any type of machine that is capable of running a computer program. Processes 10 , 60 and 80 may be implemented in hardware, software, or a combination of the two. For example, processes 10 , 60 and 80 may be implemented in a circuit that includes one or a combination of a processor, a memory, programmable logic and logic gates.
- Processes 10 , 60 and 80 may be implemented in computer programs executed on programmable computers/machines that each includes a processor, a storage medium or other article of manufacture that is readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and one or more output devices.
- Program code may be applied to data entered using an input device to perform processes 10 , 60 and 80 and to generate output information.
- Each such program may be implemented in a high level procedural or object-oriented programming language to communicate with a computer system.
- the programs can be implemented in assembly or machine language.
- the language may be a compiled or an interpreted language.
- Each computer program may be stored on a storage medium or device (e.g., CD-ROM, hard disk, or magnetic diskette) that is readable by a general or special purpose programmable computer for configuring and operating the computer when the storage medium or device is read by the computer to perform processes 10 , 60 and 80 .
- Processes 10 , 60 and 80 may also be implemented as one or more machine-readable storage media, configured with a computer program(s), where upon execution, instructions in the computer program(s) cause a computer to operate in accordance with processes 10 , 60 and 80 .
- Processes 10 , 60 and 80 are not limited to the specific embodiments described herein.
- the elements are not limited to 8-bit or 16-bit, nor are the registers limited to 64 bits. Rather, the elements and registers can be any combination of sizes that are consistent with the processes described herein.
- processes 60 and 80 are not limited to the actions described herein. For example, after determining that an extrema value is invalid by another value in the data storage, processes 60 and 80 can overwrite the elements of the first register with a new extrema value and continue processes 60 and 80 with the rest of the data storage elements.
- overwriting the registers with the new values may reduce the number of registers used to execute processes 10 , 60 and 80 .
- Processes 10 , 60 and 80 are not limited to the specific processing order of FIGS. 1, 3 and 5 . Rather, the blocks of FIGS. 1, 3 and 5 may be re-ordered, as necessary, to achieve the results set forth above.
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Abstract
A method of locating a target value includes loading the target value into elements of a first register. The first register includes N elements (N>0). The method also includes indicating in elements of a second register, which includes N elements corresponding to the first register, whether a corresponding element from data storage matches a corresponding element of the first register.
Description
- This disclosure relates to analyzing data in data storage.
- Software code may contain instructions to locate specific data in data storage (e.g., memory such as volatile memory, and non-volatile memory, and the like). For example, software code may include instructions to search for a value in memory and to specify its location. Typically, this is accomplished by comparing each value in the data storage to the value to be searched until the location containing the value is determined. For example, typical instructions to locate a value, VALUE, in an array, x, having N elements are:
1 pos = −1 2 for (i = 0; i < N; i++) { 3 if (x[i] == VALUE) { 4 pos = i 5 break; 6 } 7 } - Other software code may contain instructions to validate extrema values such as a maximum value or a minimum value in the data storage. For example, typical instructions to verify a maximum value, MAX, in an array, y, having N elements are:
1 MAX = −1 2 for (i = 0; i < N; i++) { 3 if (y[i] > MAX) { 4 MAX = y[i] 5 } 6 } - Each element in the array, y, is compared to the maximum value, MAX, one at a time.
- FIG. 1 is a flowchart of a process for locating a target value in data storage.
- FIG. 2 is a diagram of registers used in locating the target value in the data storage.
- FIG. 3 is a flow chart of a process for verifying an initial extrema value in the data storage.
- FIG. 4 is a diagram of registers used in verifying the initial extrema value for nonnegative integer values in the data storage.
- FIG. 5 is a flow chart of a process for verifying an initial maximum value for negative integer values in the data storage.
- FIG. 6 is a diagram of registers used in verifying the initial maximum value for negative integer values in the data storage. FIG. 7 is a block diagram of a computer system on which the processes of FIGS. 1 and 3 may be implemented.
- Referring to FIGS. 1 and 2, a
process 10 may be used to locate a target value in a data storage location (not shown). Instead of comparing each value in an element within the data storage location one-at-a-time with the target value, process 10 searches for the target value N elements-at-a-time (N>0) and as will be described belowprocess 10 saves processing time. Each element, for example, may include 8-bits or 16-bits. The target value may be a value required and requested during the execution of a program (e.g., from a compiler), an arbitrary value, or a user chosen value. -
Process 10 may load (12) the target value into eachelement 30 of afirst register 32 having N (N>0) elements. For example, each element may be 8 bits and a target value of 3 may be loaded into 8 elements offirst register 32, a 64-bit register. In one embodiment,process 10 may load (12) the target value using a single computer instruction (e.g., in this embodiment, mux).Process 10 may load (14) the first N elements of the storage location into asecond register 34. This can be done, for example, using one 8-byte load or eight 8-bit loads. -
Process 10 may compare (16) each element offirst register 32 with its corresponding element insecond register 34.Process 10 may indicate (18) which elements match the target value by placing a nonzero value into a corresponding element of athird register 36.Process 10 may place a zero value into the corresponding value of the third register if there is no match. With eight one-byte values, the corresponding elements ofthird register 36 may be set to hexadecimal value 0xff to indicate a match and 0x00 to indicate no match. In one embodiment,process 10 compares (16) and indicates (18) using a single computer instruction (e.g., in this embodiment, pcmp.eq). -
Process 10 may obtain (20) the complement ofthird register 36 and place resulting corresponding values into afourth register 38. In one embodiment,process 10 obtains (20) the complement using a single computer instruction (e.g., in this embodiment, negate). In other embodiments, (20) may be skipped. -
Process 10 may load (22) a value into aposition field 40 indicating if and where there is an element infourth register 38 having a zero value. A value from “0” to “N−” may be loaded into aposition field 40 to indicate a match and the position (described below) of the element having the matching value. A value of “N” may be loaded intoposition field 40 to indicate no match. - Each register (
first register 32,second register 34,third register 36, and fourth register 38) stores values in a little-endian format, i.e., the least-significant (“right-most”) element is the least significant. Thus, insecond register 34, the least significant element has a value of “1” and the most significant element has a value of “4.” The least significant value has a position value of “0” and the most significant value has a position value of “7.” In FIG. 2, the position value of the element offourth register 38 containing a zero value is position value “5.” Thus, a value of “5” is placed inposition field 40. - If more than one zero value is in
fourth register 38,process 10 may load (22) intoposition field 40 the position value of the least significant element infourth register 38 having a zero value. - In one embodiment, process may load (22) a position field value using a single computer instruction (e.g., in this embodiment, czx1.r).
-
Process 10 may determine (24) if there is a match byreading position value 40. If there are no matches (i.e., a value of “N” infield 40, e.g., a value of “8” when there are eight elements),process 10 may load (26) the next N elements (following the first N elements) of the data storage location intosecond register 34, andprocess 10 may compare (16) each field of the second register withfirst register 32, as above. - If there are matches (e.g., a value from “0” to “N−1” is placed in field40),
process 10 ends. - A representative example of program code (i.e., machine-executable instructions) for an INTEL® ITANIUM® processor to implement
process 10 is as follows:1 mov rA = addr of the 1st element of x 2 mov RPOS = 0 3 mux1 RVAL = VAL, @bcst 4 L: 5 ld8 RCONT = [rA] , 8 ;; //Post-increment by 8 bytes 6 pcmp1.eq RRES = RVAL, RCONT ;; 7 negate NR=RRES ;; //Using e.g.xor NR=0xffffffffffffffff, RRES 8 czx1.r RIND=NR;; 9 cmp.eq p2, p3=RIND, 8;; 10 (p3) br.cond out 11 (p2) add RPOS=8, RPOS//Increment RPOS by 8 12 br. Cloop L;; 13 out: 14 //If RIND is different from 8, the value was found 15 //Then, its position pos in array x equals RPOS+RIND - In the above code, “RVAL” corresponds to
first register 32, “RCONT” corresponds tosecond register 34, “RRES” corresponds tothird register 36, “NR” corresponds tofourth register 38, and “RIND” corresponds toposition field 40. Of course, other code (or even hardware) may be used to implementprocess 10. - Referring now to FIGS. 3 and 4, another process is shown for validating extrema values. In more detail, a process60 (FIG. 3) searches data storage and verifies that an initial extrema value, such as a maximum value or a minimum value, is valid.
Process 60 may load (62) an initial extrema value into each element of afirst register 82 having N (N>0) elements, e.g., eight elements (FIG. 4). In one embodiment,process 60 may load (62) an initial extrema value using a single computer instruction (e.g., in this embodiment, mux). - The initial extrema value is a guess of the actual extrema value for the data storage.
Process 60 may be used to determine if that guess is correct. The initial extrema value can come from a user input or the initial extrema value can be determined by a compiler via a compiler optimization setting. For example, a compiler, prior to executingprocess 60, may read the first 10% of the values in the data storage and may take the extrema from those values. The compiler may then process the remaining 90% of the data storageelements using process 60. -
Process 60 may load (64) N (N>0) elements from the data storage into asecond register 84.Process 60 may compare (66) each element's value insecond register 84 to the initial extrema value loaded infirst register 82.Process 60 may load (68) the extrema value between the first register and the second register intothird register 86. For example, if the initial extrema value is a maximum, the larger of the first register element and the second register element is placed in a corresponding third register element. If the initial extrema value is a minimum, the smaller of the first register element and the second register element is placed in a corresponding third register element. - In one embodiment,
process 60 compares (66) and loads (68)third register 86 using a computer instruction (e.g., in this embodiment, pmax) if the initial extrema value is a maximum and another computer instruction (e.g., in this embodiment, pmin) is used if the initial extrema value is a minimum. -
Process 60 may determine (70) if the initial extrema value is valid by comparing elements fromthird register 86 to the initial extrema value. If all values match the initial extrema value, then the initial extrema value is valid. If at least one value in the third register does not match the initial extrema value, the initial extrema value is invalid. - If the initial extrema value is valid,
process 60 may load (72) the next N (N>0) elements intosecond register 84. If the initial extrema value is invalid,process 60 ends. - A representative example of program code (i.e., machine-executable instructions) for an INTEL® ITANIUM® processor to implement
process 60 is as follows:1 //Process first elements using method in prior art 2 //At this point, MAX contains the local maximum 3 //rA = addr of the 1st element of x on which this method is applied 4 mux1 RMAX = MAX, @bcst 5 L: 7 ld8 RVAL = [rA] , 8 ;; //8values are loaded in one step 8 pmax1.u RRES = RVAL, RMAX;; 9 cmp.eq p2,p3=RRES,RMAX;; //Are all values in RVAL lower than or equal to MAX? 10 (p3) br.cond method_of_prior_art //No. Branch to recovery 11 (p2) br.cond L;; //Yes. Process 60 can proceed. - In the above code, “RMAX” corresponds to
first register 82, “RVAL” corresponds tosecond register 84 and “RRES” corresponds tothird register 86. The code can be pipelined with an initiation interval of one using the following br.ctop instruction:1 L: 2 (p16) ld8r32 = [rA] , 8 // r32 serves a RVAL3 3 (p17) pmax1.u r34 = r33, RMAX // r32 rotated into r33. r34 serves as RRES 4 (p19) cmp.eq p2, p3 = r36, RMAX //r34 rotated into r36 5 (p3) br.cond method_of_prior_art 6 (p2) br.ctop L ;; - Of course, other code (or even hardware) may be used to implement
process 60. - Heretofore, comparing each element one-at-a-time to validate an initial extrema value took N (N>0) cycles plus a fixed amount of time (e.g., time to load instructions, etc.), assuming the processing is pipelined with an initiation interval of one. For an array x having N elements, assuming that the values are stored using 8 bits per element, assuming
process 60 is applied to the last f*N (0<f<1) elements of the data storage where f is the portion of the data storage analyzed by a compiler before executingprocess 60 and assuming the maximum value was in the first (1−f)*N elements, then process 60 takes: - (1−f)*N+f*N/8+a cycles;
- where a is a constant. Assuming that N is sufficiently large,
process 60 takes 7f/8 cycles. - Referring to FIGS. 5 and 6, other embodiments process values in data storage that may be negative integers instead of nonnegative integers.
Process 60 may be modified into aprocess 80 to account for nonnegative integers. -
Actions actions - For each element in which an initial extrema is false,
process 80 may load (88) a hexadecimal value of 0xff in the corresponding element of athird register 86. For each element in which the initial extrema is true,process 80 may load (88) a hexadecimal value of 0x00 into the corresponding element ofthird register 86. If the initial extrema value is a maximum,process 80 may determine that the initial extrema value is valid if values infirst register 82 are greater than or equal to values insecond register 84. If the extrema value is a minimum,process 80 determines that the initial extrema value is valid if values infirst register 82 are less than or equal to the values insecond register 84. In one embodiment,process 80 may compare (88) the values using a single computer instruction (e.g., in this embodiment, pcmpl.gt). -
Process 80 may load (90) into an invalid count field 94 a count of the elements inthird register 86 where the initial extrema value is invalid (i.e., elements having a hexadecimal value of 0xff). In one embodiment,process 80 may load (90)invalid count field 94 by using a single computer instruction (e.g., in this embodiment, popcnt). -
Process 80 may determine (92) if the initial extrema value is invalid by determining if there is a nonzero value ininvalid count field 94. - If the initial extrema value is valid (i.e., a zero value in invalid count field94),
process 80 may load (72) the next N (N>0) elements intosecond register 84. If the initial extrema value is invalid (i.e.,invalid count field 94 contains a nonzero value),process 80 ends. - A representative example of program code (i.e., machine-executable instructions) for an INTEL® ITANIUM® processor to implement
process 80 is as follows:1 RA = addr of the 1st element of x on which process 80 is applied2 mux1 RMAX = MAX, @bcst 3 L: 4 ld8 RVAL = [rA] , 8;; 5 pcmp1.gt RRES = RVAL, RMAX ;; 6 cmp.eq p2, p3=RCNT, 0;; 7 (p3) br.cond method_of_prior_art 8 (p2) br.cond L;; - In the above code, “RMAX” corresponds to
first register 82, “RVAL” corresponds tosecond register 84, “RRES” corresponds tothird register 86 and “RCNT” corresponds toinvalid count field 94. The instruction above can be pipelined with an initiation interval of one and described as:1 L: 2 (p16) ld8 RVAL = [rA] , 8 ;; 3 (p17) pcmp1.gt RRES = RVAL, RMAX ;; 4 (p19) popcnt RCNT = RRES;; 5 (p21) cmp.eq p2, p3 = RCNT, 0;; 6 (p3) br.cond method_of_prior_art 7 (p2) br.ctop L ;; - Of course, other code (or even hardware) may be used to implement
process 80. - FIG. 7 shows a
computer 100 for usingprocesses Computer 100 includes aprocessor 102, amemory 104, and a storage medium 106 (e.g., hard disk).Storage medium 106stores operating system 110,data storage 112 andregisters 116, andcomputer instructions 114 which are executed byprocessor 102 out ofmemory 104 to performprocesses - Processes10, 60 and 80 are not limited to use with the hardware and software of FIG. 7; they may find applicability in any computing or processing environment and with any type of machine that is capable of running a computer program.
Processes Processes processes - Each such program may be implemented in a high level procedural or object-oriented programming language to communicate with a computer system. However, the programs can be implemented in assembly or machine language. The language may be a compiled or an interpreted language. Each computer program may be stored on a storage medium or device (e.g., CD-ROM, hard disk, or magnetic diskette) that is readable by a general or special purpose programmable computer for configuring and operating the computer when the storage medium or device is read by the computer to perform
processes Processes processes - Processes10, 60 and 80 are not limited to the specific embodiments described herein. For example, the elements are not limited to 8-bit or 16-bit, nor are the registers limited to 64 bits. Rather, the elements and registers can be any combination of sizes that are consistent with the processes described herein.
- In another example, processes60 and 80 are not limited to the actions described herein. For example, after determining that an extrema value is invalid by another value in the data storage, processes 60 and 80 can overwrite the elements of the first register with a new extrema value and continue
processes - In still another example, overwriting the registers with the new values may reduce the number of registers used to execute
processes - Processes10, 60 and 80 are not limited to the specific processing order of FIGS. 1, 3 and 5. Rather, the blocks of FIGS. 1, 3 and 5 may be re-ordered, as necessary, to achieve the results set forth above.
- Other embodiments not described herein are also within the scope of the following claims.
Claims (34)
1. A method of locating a target value, comprising:
loading the target value into elements of a first register, the first register comprising N elements (N>0); and
indicating in elements of a second register, comprising N elements corresponding to the first register, whether a corresponding element from data storage matches a corresponding element of the first register.
2. The method of claim 1 , further comprising:
indicating a position of at least one element in the data storage containing the target value based on the contents of the second register.
3. The method of claim 1 , further comprising:
indicating a position of a least significant element containing the target value.
4. The method of claim 1 , further comprising:
taking a complement of the second register; and
loading the complement of the second register into a third register comprising corresponding N elements.
5. The method of claim 1 , further comprising:
overwriting the second register with its complement.
6. A method of verifying if an initial extrema value is valid, comprising:
loading the initial extrema value into elements of a first register, the first register comprising N elements (N>0); and
indicating in a second register, comprising N elements, the extrema values between corresponding elements in data storage and corresponding elements in the first register.
7. The method of claim 6 , further comprising:
indicating when an initial extrema value is invalid.
8. The method of claim 7 , wherein the extrema value comprises a maximum; and
wherein indicating comprises determining if an element in the second register is greater than the initial extrema value.
9. The method of claim 6 , wherein the initial extrema value is determined by a user.
10. The method of claim 6 , wherein the initial extrema value is determined by a compiler.
11. An apparatus comprising:
circuitry, for locating a value, to:
load the target value into elements of a first register, the first register comprising N elements (N>0); and
indicate in elements of a second register, comprising N elements corresponding to the first register, whether a corresponding element from data storage matches a corresponding element of the first register.
12. The apparatus of claim 11 , further comprising circuitry to:
indicate a position of at least one element in the data storage containing the target value based on the contents of the second register.
13. The apparatus of claim 11 , further comprising circuitry to:
indicate a position of a least significant element containing the target value.
14. The apparatus of claim 11 , further comprising circuitry to:
take a complement of the second register; and
load the complement of the second register into a third register comprising corresponding N elements.
15. The apparatus of claim 11 , further comprising circuitry to:
overwrite the second register with its complement.
16. An apparatus comprising:
circuitry, for locating a value, to:
load the initial extrema value into elements of a first register, the first register comprising N elements (N>0); and
indicate in a second register, comprising N elements, the extrema values between corresponding elements in data storage and corresponding elements in the first register.
17. The apparatus of claim 16 , further comprising circuitry to:
indicate when an initial extrema value is invalid.
18. The apparatus of claim 17 , wherein the extrema value comprises a maximum; and
wherein indicating comprises determining if an element in the second register is greater than the initial extrema value.
19. The apparatus of claim 16 , wherein the initial extrema value is determined by a user.
20. The apparatus of claim 16 , wherein the initial extrema value is determined by a compiler.
21. An article comprising a machine-readable medium that stores executable instructions for locating data, the instructions causing a machine to:
load the target value into elements of a first register, the first register comprising N elements (N>0); and
indicate in elements of a second register, comprising N elements corresponding to the first register, whether a corresponding element from data storage matches a corresponding element of the first register.
22. The article of claim 21 , further comprising instructions causing a machine to:
indicate a position of at least one element in the data storage containing the target value based on the contents of the second register.
23. The article of claim 21 , further comprising instructions causing a machine to:
indicate a position of a least significant element containing the target value.
24. The article of claim 21 , further comprising instructions causing a machine to:
take a complement of the second register; and
load the complement of the second register into a third register comprising corresponding N elements.
25. The article of claim 21 , further comprising instructions causing a machine to:
overwrite the second register with its complement.
26. An article comprising a machine-readable medium that stores executable instructions for locating data, the instructions causing a machine to:
load the initial extrema value into elements of a first register, the first register comprising N elements (N>0); and
indicate in a second register, comprising N elements, the extrema values between corresponding elements in data storage and corresponding elements in the first register.
27. The article of claim 26 , further comprising instructions causing a machine to:
indicate when an initial extrema value is invalid.
28. The article of claim 27 , wherein the extrema value comprises a maximum; and
wherein indicating comprises determining if an element in the second register is greater than the initial extrema value.
29. The article of claim 26 , wherein the initial extrema value is determined by a user.
30. The article of claim 26 , wherein the initial extrema value is determined by a compiler.
31. A system, comprising:
at least one processor;
memory; and
logic coupled to the processing device and the memory, usable by the at least one processor to:
load a target value into elements of a first register, the first register comprising N elements (N>);
indicate in elements of a second register, comprising N elements corresponding to the first register, whether a corresponding element from data storage matches a corresponding element of the first register;
load the initial extrema value into elements of a third register, the third register comprising N elements (N>0); and
indicate in a fourth register, comprising N elements, the extrema values between corresponding elements in data storage and corresponding elements in the third register.
32. The system of claim 31 wherein the first register is the third register and the second register is the fourth register.
33. The system of claim 31 , further comprising logic to:
indicate a position of at least one element in the data storage containing the target value based on the contents of the second register.
34. The system of claim 31 , further comprising logic to:
indicate when an initial extrema value is invalid.
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US7206920B2 (en) | 2007-04-17 |
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