HK84188A - Process of fabricating a semiconductor integrated circuit device - Google Patents

Process of fabricating a semiconductor integrated circuit device

Info

Publication number
HK84188A
HK84188A HK841/88A HK84188A HK84188A HK 84188 A HK84188 A HK 84188A HK 841/88 A HK841/88 A HK 841/88A HK 84188 A HK84188 A HK 84188A HK 84188 A HK84188 A HK 84188A
Authority
HK
Hong Kong
Prior art keywords
fabricating
integrated circuit
semiconductor integrated
circuit device
semiconductor
Prior art date
Application number
HK841/88A
Other languages
English (en)
Inventor
Akihiro Tomozawa
Yoku Kaino
Shigeru Shimada
Nozomi Horino
Yoshiaki Yoshiura
Osamu Tsuchiya
Shozo Hosoda
Original Assignee
Hitachi Ltd
Hitachi Microcumputer Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP58216320A external-priority patent/JPS60109251A/ja
Priority claimed from JP58216319A external-priority patent/JPS60109250A/ja
Application filed by Hitachi Ltd, Hitachi Microcumputer Eng filed Critical Hitachi Ltd
Publication of HK84188A publication Critical patent/HK84188A/xx

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
HK841/88A 1983-11-18 1988-10-20 Process of fabricating a semiconductor integrated circuit device HK84188A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP58216320A JPS60109251A (ja) 1983-11-18 1983-11-18 半導体集積回路装置
JP58216319A JPS60109250A (ja) 1983-11-18 1983-11-18 半導体集積回路装置

Publications (1)

Publication Number Publication Date
HK84188A true HK84188A (en) 1988-10-28

Family

ID=26521363

Family Applications (1)

Application Number Title Priority Date Filing Date
HK841/88A HK84188A (en) 1983-11-18 1988-10-20 Process of fabricating a semiconductor integrated circuit device

Country Status (7)

Country Link
US (1) US4782037A (xx)
KR (1) KR930004984B1 (xx)
DE (1) DE3442037A1 (xx)
FR (1) FR2555364B1 (xx)
GB (1) GB2150349B (xx)
HK (1) HK84188A (xx)
SG (1) SG41888G (xx)

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US4935380A (en) * 1987-08-04 1990-06-19 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing semiconductor device
JPH01138734A (ja) * 1987-11-25 1989-05-31 Mitsubishi Electric Corp 複導電体層を有する半導体装置およびその製造方法
US5252504A (en) * 1988-05-02 1993-10-12 Micron Technology, Inc. Reverse polysilicon CMOS fabrication
JPH0793354B2 (ja) * 1988-11-28 1995-10-09 株式会社東芝 半導体装置の製造方法
GB8907898D0 (en) * 1989-04-07 1989-05-24 Inmos Ltd Semiconductor devices and fabrication thereof
JPH02291150A (ja) * 1989-04-28 1990-11-30 Hitachi Ltd 半導体装置
US4935376A (en) * 1989-10-12 1990-06-19 At&T Bell Laboratories Making silicide gate level runners
US5026657A (en) * 1990-03-12 1991-06-25 Micron Technology, Inc. Split-polysilicon CMOS DRAM process incorporating self-aligned silicidation of the cell plate, transistor gates, and N+ regions
US5030585A (en) * 1990-03-22 1991-07-09 Micron Technology, Inc. Split-polysilicon CMOS DRAM process incorporating selective self-aligned silicidation of conductive regions and nitride blanket protection of N-channel regions during P-channel gate spacer formation
US4996167A (en) * 1990-06-29 1991-02-26 At&T Bell Laboratories Method of making electrical contacts to gate structures in integrated circuits
US6008078A (en) 1990-07-24 1999-12-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
GB2249217A (en) * 1990-10-23 1992-04-29 Samsung Electronics Co Ltd Semiconductor device planarisation
KR960001611B1 (ko) 1991-03-06 1996-02-02 가부시끼가이샤 한도다이 에네르기 겐뀨쇼 절연 게이트형 전계 효과 반도체 장치 및 그 제작방법
US6849872B1 (en) * 1991-08-26 2005-02-01 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor
US5323047A (en) * 1992-01-31 1994-06-21 Sgs-Thomson Microelectronics, Inc. Structure formed by a method of patterning a submicron semiconductor layer
EP0557098B1 (en) * 1992-02-20 1998-04-29 Matsushita Electronics Corporation Solid-State Image Pick-up Device and Method of manufacturing the same
US6624450B1 (en) 1992-03-27 2003-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
JP3065829B2 (ja) * 1992-12-25 2000-07-17 新日本製鐵株式会社 半導体装置
US5719065A (en) 1993-10-01 1998-02-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device with removable spacers
US6133620A (en) * 1995-05-26 2000-10-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and process for fabricating the same
US6867432B1 (en) * 1994-06-09 2005-03-15 Semiconductor Energy Lab Semiconductor device having SiOxNy gate insulating film
JP3337825B2 (ja) * 1994-06-29 2002-10-28 三菱電機株式会社 内部配線を有する半導体装置およびその製造方法
JP2755176B2 (ja) * 1994-06-30 1998-05-20 日本電気株式会社 固体撮像素子
KR0149256B1 (ko) * 1995-08-25 1998-10-01 김주용 씨모스 트랜지스터 제조방법
JP3565983B2 (ja) * 1996-04-12 2004-09-15 株式会社半導体エネルギー研究所 半導体装置の作製方法
US5808353A (en) * 1996-06-20 1998-09-15 Harris Corporation Radiation hardened dielectric for EEPROM
US7078342B1 (en) * 1996-07-16 2006-07-18 Micron Technology, Inc. Method of forming a gate stack
US7041548B1 (en) 1996-07-16 2006-05-09 Micron Technology, Inc. Methods of forming a gate stack that is void of silicon clusters within a metallic silicide film thereof
JP3524326B2 (ja) * 1997-05-07 2004-05-10 キヤノン株式会社 微小短針の製造に用いる雌型基板と該雌型基板の製造方法、及び該雌型基板を用いた微小短針とプローブの製造方法
KR100253311B1 (ko) * 1997-09-02 2000-06-01 김영환 반도체 소자의 평탄화 방법
US20020000626A1 (en) * 1997-11-26 2002-01-03 Advanced Micro Devices, Inc. Improving field leakage by using a thin layer of nitride deposited by chemical vapor deposition

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US4180596A (en) * 1977-06-30 1979-12-25 International Business Machines Corporation Method for providing a metal silicide layer on a substrate
US4273805A (en) * 1978-06-19 1981-06-16 Rca Corporation Passivating composite for a semiconductor device comprising a silicon nitride (Si1 3N4) layer and phosphosilicate glass (PSG) layer
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US4392150A (en) * 1980-10-27 1983-07-05 National Semiconductor Corporation MOS Integrated circuit having refractory metal or metal silicide interconnect layer
JPS5780739A (en) * 1980-11-07 1982-05-20 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
DE3045922A1 (de) * 1980-12-05 1982-07-08 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von strukturen von aus siliziden oder aus silizid-polysilizium bestehenden schichten durch reaktives sputteraetzen
JPS57113235A (en) * 1980-12-29 1982-07-14 Nec Corp Semiconductor device
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DE3138960A1 (de) * 1981-09-30 1983-04-14 Siemens AG, 1000 Berlin und 8000 München Verfahren zur erzeugung elektrisch leitender schichten
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Also Published As

Publication number Publication date
FR2555364B1 (fr) 1990-02-02
KR850004353A (ko) 1985-07-11
GB8428534D0 (en) 1984-12-19
KR930004984B1 (ko) 1993-06-11
SG41888G (en) 1989-01-27
DE3442037A1 (de) 1985-05-30
FR2555364A1 (fr) 1985-05-24
GB2150349B (en) 1987-07-08
US4782037A (en) 1988-11-01
GB2150349A (en) 1985-06-26

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Legal Events

Date Code Title Description
NR Patent deemed never to have been added to the register under section 13(7) of patents (transitional arrangements) rules