HK61697A - Semiconductor apparatus including semiconductor integrated circuit and operating method thereof - Google Patents

Semiconductor apparatus including semiconductor integrated circuit and operating method thereof

Info

Publication number
HK61697A
HK61697A HK61697A HK61697A HK61697A HK 61697 A HK61697 A HK 61697A HK 61697 A HK61697 A HK 61697A HK 61697 A HK61697 A HK 61697A HK 61697 A HK61697 A HK 61697A
Authority
HK
Hong Kong
Prior art keywords
integrated circuit
apparatus including
operating method
semiconductor integrated
semiconductor
Prior art date
Application number
HK61697A
Other languages
English (en)
Inventor
Kazuhiro Sakashita
Takeshi Hashizume
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of HK61697A publication Critical patent/HK61697A/xx

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
HK61697A 1990-02-26 1997-05-08 Semiconductor apparatus including semiconductor integrated circuit and operating method thereof HK61697A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2046569A JP2561164B2 (ja) 1990-02-26 1990-02-26 半導体集積回路

Publications (1)

Publication Number Publication Date
HK61697A true HK61697A (en) 1997-05-16

Family

ID=12750952

Family Applications (1)

Application Number Title Priority Date Filing Date
HK61697A HK61697A (en) 1990-02-26 1997-05-08 Semiconductor apparatus including semiconductor integrated circuit and operating method thereof

Country Status (5)

Country Link
US (1) US5109190A (de)
EP (1) EP0444845B1 (de)
JP (1) JP2561164B2 (de)
DE (1) DE69118952T2 (de)
HK (1) HK61697A (de)

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US6704895B1 (en) * 1987-06-02 2004-03-09 Texas Instruments Incorporated Integrated circuit with emulation register in JTAG JAP
JPH05302961A (ja) * 1991-03-27 1993-11-16 Nec Corp Ｌｓｉに於けるテスト信号出力回路
JP2741119B2 (ja) * 1991-09-17 1998-04-15 三菱電機株式会社 バイパススキャンパスおよびそれを用いた集積回路装置
EP0533476B1 (de) * 1991-09-18 1998-12-02 Fujitsu Limited Integrierte Halbleiterschaltung mit Abtastpfad
JP2973641B2 (ja) * 1991-10-02 1999-11-08 日本電気株式会社 Ｔａｐコントローラ
US5231314A (en) * 1992-03-02 1993-07-27 National Semiconductor Corporation Programmable timing circuit for integrated circuit device with test access port
JPH05273311A (ja) * 1992-03-24 1993-10-22 Nec Corp 論理集積回路
US5270642A (en) * 1992-05-15 1993-12-14 Hewlett-Packard Company Partitioned boundary-scan testing for the reduction of testing-induced damage
US5471481A (en) * 1992-05-18 1995-11-28 Sony Corporation Testing method for electronic apparatus
JP2748069B2 (ja) * 1992-05-19 1998-05-06 三菱電機株式会社 フリップフロップ回路
US5357572A (en) * 1992-09-22 1994-10-18 Hughes Aircraft Company Apparatus and method for sensitive circuit protection with set-scan testing
US5448576A (en) * 1992-10-29 1995-09-05 Bull Hn Information Systems Inc. Boundary scan architecture extension
US5477545A (en) * 1993-02-09 1995-12-19 Lsi Logic Corporation Method and apparatus for testing of core-cell based integrated circuits
US5379302A (en) * 1993-04-02 1995-01-03 National Semiconductor Corporation ECL test access port with low power control
JP2746076B2 (ja) * 1993-09-02 1998-04-28 日本電気株式会社 半導体集積回路、その設計方法およびそのテスト方法
US5422891A (en) * 1993-07-23 1995-06-06 Rutgers University Robust delay fault built-in self-testing method and apparatus
US5687312A (en) * 1993-07-30 1997-11-11 Texas Instruments Incorporated Method and apparatus for processor emulation
US6006343A (en) * 1993-07-30 1999-12-21 Texas Instruments Incorporated Method and apparatus for streamlined testing of electrical circuits
FI100136B (fi) * 1993-10-01 1997-09-30 Nokia Telecommunications Oy Menetelmä integroidun piirin testaamiseksi sekä integroitu piiri
US5809036A (en) * 1993-11-29 1998-09-15 Motorola, Inc. Boundary-scan testable system and method
DE4340899A1 (de) * 1993-12-01 1995-06-08 Philips Patentverwaltung Meßvorrichtung zum Testen der Verbindungen zwischen wenigstens zwei Baugruppen
GB2290877B (en) * 1994-07-01 1997-08-20 Advanced Risc Mach Ltd Integrated circuit test controller
US5636227A (en) * 1994-07-08 1997-06-03 Advanced Risc Machines Limited Integrated circuit test mechansim and method
GB9417602D0 (en) * 1994-09-01 1994-10-19 Inmos Ltd A controller for implementing scan testing
GB9421977D0 (en) * 1994-10-31 1994-12-21 Inmos Ltd A scan latch and test method therefor
US5715255A (en) * 1994-11-21 1998-02-03 Texas Instruments Incorporated Low overhead memory designs for IC terminals
US5732091A (en) * 1994-11-21 1998-03-24 Texas Instruments Incorporated Self initializing and correcting shared resource boundary scan with output latching
US5715254A (en) * 1994-11-21 1998-02-03 Texas Instruments Incorporated Very low overhead shared resource boundary scan design
US5615217A (en) * 1994-12-01 1997-03-25 International Business Machines Corporation Boundary-scan bypass circuit for integrated circuit electronic component and circuit boards incorporating such circuits and components
US5701307A (en) * 1994-12-16 1997-12-23 Texas Instruments Incorporated Low overhead input and output boundary scan cells
JP2768910B2 (ja) * 1995-02-27 1998-06-25 日本モトローラ株式会社 半導体集積装置におけるスキャンテスト回路
US5627839A (en) * 1995-02-28 1997-05-06 Texas Instruments Incorporated Scan cell output latches using switches and bus holders
US6055659A (en) * 1999-02-26 2000-04-25 Texas Instruments Incorporated Boundary scan with latching output buffer and weak input buffer
US7611533B2 (en) * 1995-06-07 2009-11-03 Cook Incorporated Coated implantable medical device
US6804725B1 (en) * 1996-08-30 2004-10-12 Texas Instruments Incorporated IC with state machine controlled linking module
US6000051A (en) * 1997-10-10 1999-12-07 Logic Vision, Inc. Method and apparatus for high-speed interconnect testing
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
CA2273603C (en) * 1999-06-04 2007-11-20 Acculogic, Inc. Method and apparatus for adaptive clocking for boundary scan testing and device programming
DE60021705T2 (de) * 1999-11-29 2006-06-01 Koninklijke Philips Electronics N.V. Verfahren und integrierte schaltung gestaltet zur beschickung eines prüfmusters auf einen einzelnen gemeinsamen anschlussstift
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
JP4887552B2 (ja) * 2000-07-04 2012-02-29 富士通セミコンダクター株式会社 Ｌｓｉチップのレイアウト設計方法
US6647433B1 (en) * 2000-08-14 2003-11-11 Hewlett-Packard Development Company, L.P. Architecture and related methods facilitating secure port bypass circuit settings
DE102004028632B4 (de) * 2004-06-15 2016-08-04 Infineon Technologies Ag Halbleiter-Chip
US7512856B2 (en) * 2006-11-22 2009-03-31 Faraday Technology Corp. Register circuit, scanning register circuit utilizing register circuits and scanning method thereof
EP2331979B1 (de) * 2008-09-26 2012-07-04 Nxp B.V. Verfahren zur prüfung einer teilweise zusammengebauten mehrchipanordnung, integrierter schaltungschip und mehrchipanordnung
US9791505B1 (en) * 2016-04-29 2017-10-17 Texas Instruments Incorporated Full pad coverage boundary scan

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2183853B (en) * 1985-12-02 1989-12-20 Trw Inc Power supply switch circuit for wafer scale applications
NL8801362A (nl) * 1988-05-27 1989-12-18 Philips Nv Elektronische module bevattende een eerste substraatelement met een funktioneel deel, alsmede een tweede substraatelement voor het testen van een interkonnektiefunktie, voet bevattende zo een tweede substraatelement, substraatelement te gebruiken als zo een tweede substraatelement en elektronisch apparaat bevattende een plaat met gedrukte bedrading en ten minste twee zulke elektronische modules.
US4945536A (en) * 1988-09-09 1990-07-31 Northern Telecom Limited Method and apparatus for testing digital systems
US4963824A (en) * 1988-11-04 1990-10-16 International Business Machines Corporation Diagnostics of a board containing a plurality of hybrid electronic components
US5001713A (en) * 1989-02-08 1991-03-19 Texas Instruments Incorporated Event qualified testing architecture for integrated circuits

Also Published As

Publication number Publication date
EP0444845B1 (de) 1996-04-24
EP0444845A1 (de) 1991-09-04
US5109190A (en) 1992-04-28
DE69118952T2 (de) 1996-10-02
JP2561164B2 (ja) 1996-12-04
JPH03248067A (ja) 1991-11-06
DE69118952D1 (de) 1996-05-30

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Legal Events

Date Code Title Description
PF Patent in force
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20080225