HK106193A - Method and circuit arrangement for the parallel write-in of data in a semiconductor memory - Google Patents

Method and circuit arrangement for the parallel write-in of data in a semiconductor memory

Info

Publication number
HK106193A
HK106193A HK1061/93A HK106193A HK106193A HK 106193 A HK106193 A HK 106193A HK 1061/93 A HK1061/93 A HK 1061/93A HK 106193 A HK106193 A HK 106193A HK 106193 A HK106193 A HK 106193A
Authority
HK
Hong Kong
Prior art keywords
semiconductor memory
data
circuit arrangement
parallel write
parallel
Prior art date
Application number
HK1061/93A
Other languages
English (en)
Inventor
Hans-Dieter Dipl-Ing Oberle
Oskar Dr Rer Nat Kowarik
Rainer Dipl-Phys Kraus
Manfred Dipl-Ing Paul
Kurt Dr Prof Hoffmann
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of HK106193A publication Critical patent/HK106193A/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
HK1061/93A 1987-03-16 1993-10-07 Method and circuit arrangement for the parallel write-in of data in a semiconductor memory HK106193A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3708527 1987-03-16

Publications (1)

Publication Number Publication Date
HK106193A true HK106193A (en) 1993-10-15

Family

ID=6323209

Family Applications (1)

Application Number Title Priority Date Filing Date
HK1061/93A HK106193A (en) 1987-03-16 1993-10-07 Method and circuit arrangement for the parallel write-in of data in a semiconductor memory

Country Status (7)

Country Link
US (1) US4885748A (fr)
EP (1) EP0282976B1 (fr)
JP (1) JP2610598B2 (fr)
KR (1) KR950006963B1 (fr)
AT (1) ATE68289T1 (fr)
DE (1) DE3865330D1 (fr)
HK (1) HK106193A (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2222461B (en) * 1988-08-30 1993-05-19 Mitsubishi Electric Corp On chip testing of semiconductor memory devices
KR910005306B1 (ko) * 1988-12-31 1991-07-24 삼성전자 주식회사 고밀도 메모리의 테스트를 위한 병렬리드회로
EP0455653B1 (fr) * 1989-01-26 1993-05-05 Siemens Aktiengesellschaft Memoire semiconductrice integree
DE3920871A1 (de) * 1989-06-26 1991-01-03 Siemens Ag Integrierter halbleiterspeicher
KR920001081B1 (ko) * 1989-06-10 1992-02-01 삼성전자 주식회사 램 테스트시 고속기록회로
KR920007909B1 (ko) * 1989-11-18 1992-09-19 삼성전자 주식회사 램 테스트시 고속 기록방법
JPH04212799A (ja) * 1990-01-31 1992-08-04 Nec Ic Microcomput Syst Ltd テスト回路内蔵半導体メモリ
US5073891A (en) * 1990-02-14 1991-12-17 Intel Corporation Method and apparatus for testing memory
US5222067A (en) * 1990-03-08 1993-06-22 Terenix Co., Ltd. Detection of pattern-sensitive faults in RAM by use of M-sequencers
US5546343A (en) * 1990-10-18 1996-08-13 Elliott; Duncan G. Method and apparatus for a single instruction operating multiple processors on a memory chip
US5241500A (en) * 1992-07-29 1993-08-31 International Business Machines Corporation Method for setting test voltages in a flash write mode
US5490115A (en) * 1994-07-29 1996-02-06 Cypress Semiconductor Corp. Method and apparatus for writing to memory cells in a minimum number of cycles during a memory test operation
US5996097A (en) * 1997-04-28 1999-11-30 International Business Machines Corporation Testing logic associated with numerous memory cells in the word or bit dimension in parallel
US5959911A (en) * 1997-09-29 1999-09-28 Siemens Aktiengesellschaft Apparatus and method for implementing a bank interlock scheme and related test mode for multibank memory devices
KR100498414B1 (ko) * 1997-12-08 2005-09-08 삼성전자주식회사 반도체메모리장치를위한테스트보드및테스트방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5539073B2 (fr) * 1974-12-25 1980-10-08
JPS51147924A (en) * 1975-06-13 1976-12-18 Fujitsu Ltd Memory unit
US4055754A (en) * 1975-12-22 1977-10-25 Chesley Gilman D Memory device and method of testing the same
JPS55163699A (en) * 1979-06-06 1980-12-19 Fujitsu Ltd Testing system for memory board
EP0055594B1 (fr) * 1980-12-23 1988-07-13 Fujitsu Limited Dispositif de mémoire non-volatile à semi-conducteur programmable électriquement
JPS58114391A (ja) * 1981-12-25 1983-07-07 Nec Corp センスアンプ回路
JPS5925319A (ja) * 1982-07-30 1984-02-09 Nitto Electric Ind Co Ltd 気化性薬剤含有フイルムの製造方法
KR900005666B1 (ko) * 1984-08-30 1990-08-03 미쓰비시전기 주식회사 반도체기억장치
JPS61202400A (ja) * 1985-03-05 1986-09-08 Mitsubishi Electric Corp 半導体記憶装置

Also Published As

Publication number Publication date
JPS63241799A (ja) 1988-10-07
KR950006963B1 (ko) 1995-06-26
KR880011812A (ko) 1988-10-31
ATE68289T1 (de) 1991-10-15
EP0282976A1 (fr) 1988-09-21
DE3865330D1 (de) 1991-11-14
US4885748A (en) 1989-12-05
JP2610598B2 (ja) 1997-05-14
EP0282976B1 (fr) 1991-10-09

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)