HK1006754A1 - Multi-mode microprocessor with electrical pin for selective re-initialization of processor state - Google Patents
Multi-mode microprocessor with electrical pin for selective re-initialization of processor state Download PDFInfo
- Publication number
- HK1006754A1 HK1006754A1 HK98105911A HK98105911A HK1006754A1 HK 1006754 A1 HK1006754 A1 HK 1006754A1 HK 98105911 A HK98105911 A HK 98105911A HK 98105911 A HK98105911 A HK 98105911A HK 1006754 A1 HK1006754 A1 HK 1006754A1
- Authority
- HK
- Hong Kong
- Prior art keywords
- microprocessor
- registers
- pin
- control unit
- initialization
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Debugging And Monitoring (AREA)
- Microcomputers (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US79458491A | 1991-11-19 | 1991-11-19 | |
| US07794584 | 1991-11-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| HK1006754A1 true HK1006754A1 (en) | 1999-03-12 |
| HK1006754B HK1006754B (en) | 1999-03-12 |
Family
ID=
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05257808A (ja) | 1993-10-08 |
| US5555423A (en) | 1996-09-10 |
| KR930010732A (ko) | 1993-06-23 |
| KR100261527B1 (ko) | 2000-07-15 |
| GB9217947D0 (en) | 1992-10-07 |
| GB2261753A (en) | 1993-05-26 |
| CN1040156C (zh) | 1998-10-07 |
| DE4238099C2 (de) | 1998-06-10 |
| DE4238099A1 (enExample) | 1993-05-27 |
| CN1072521A (zh) | 1993-05-26 |
| GB2261753B (en) | 1995-07-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PF | Patent in force | ||
| PE | Patent expired |
Effective date: 20120823 |