JPS6488657A - Stack control circuit - Google Patents

Stack control circuit

Info

Publication number
JPS6488657A
JPS6488657A JP24549687A JP24549687A JPS6488657A JP S6488657 A JPS6488657 A JP S6488657A JP 24549687 A JP24549687 A JP 24549687A JP 24549687 A JP24549687 A JP 24549687A JP S6488657 A JPS6488657 A JP S6488657A
Authority
JP
Japan
Prior art keywords
bank
stack area
register
interruption processing
coincidence detecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24549687A
Other languages
Japanese (ja)
Inventor
Shigenori Tokumitsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP24549687A priority Critical patent/JPS6488657A/en
Publication of JPS6488657A publication Critical patent/JPS6488657A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the runaway of a program by switching to a bank fixed forcibly when a microprocessor accesses an address space to show a stack area. CONSTITUTION:A bank switching circuit 28, when a CPU accesses a stack area and a coincidence detecting signal is outputted from a coincidence detecting circuit 27, selects a fixed bank regardless of the data set to a bank register 25. Namely, a return destination address is stored into the stack area of a bank 0, shifted to an interruption processing and the bank is set to a bank register 25 toward the bank register 25 during the interruption processing. When the interruption processing is completed, the bank register 25 is on the bank 3. Since the stack area is accessed, a coincidence detecting signal is outputted, and the output from a decoder 29 makes the bank 0 active. Thus, the correct return destination address is read.
JP24549687A 1987-09-29 1987-09-29 Stack control circuit Pending JPS6488657A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24549687A JPS6488657A (en) 1987-09-29 1987-09-29 Stack control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24549687A JPS6488657A (en) 1987-09-29 1987-09-29 Stack control circuit

Publications (1)

Publication Number Publication Date
JPS6488657A true JPS6488657A (en) 1989-04-03

Family

ID=17134532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24549687A Pending JPS6488657A (en) 1987-09-29 1987-09-29 Stack control circuit

Country Status (1)

Country Link
JP (1) JPS6488657A (en)

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