HK1004998A1 - Method for testing semiconductor memory circuit - Google Patents

Method for testing semiconductor memory circuit

Info

Publication number
HK1004998A1
HK1004998A1 HK98104148A HK98104148A HK1004998A1 HK 1004998 A1 HK1004998 A1 HK 1004998A1 HK 98104148 A HK98104148 A HK 98104148A HK 98104148 A HK98104148 A HK 98104148A HK 1004998 A1 HK1004998 A1 HK 1004998A1
Authority
HK
Hong Kong
Prior art keywords
chip
blh
reference voltage
semiconductor memory
internal reference
Prior art date
Application number
HK98104148A
Other languages
English (en)
Inventor
Johann Rieger
Der Ropp Thomas Von
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of HK1004998A1 publication Critical patent/HK1004998A1/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
HK98104148A 1995-03-15 1998-05-13 Method for testing semiconductor memory circuit HK1004998A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP95103791A EP0732703B1 (de) 1995-03-15 1995-03-15 Verfahren zur Überprüfung einer Halbleiter-Speichervorrichtung

Publications (1)

Publication Number Publication Date
HK1004998A1 true HK1004998A1 (en) 1998-12-18

Family

ID=8219073

Family Applications (1)

Application Number Title Priority Date Filing Date
HK98104148A HK1004998A1 (en) 1995-03-15 1998-05-13 Method for testing semiconductor memory circuit

Country Status (8)

Country Link
US (1) US6366511B2 (ja)
EP (1) EP0732703B1 (ja)
JP (1) JP3878243B2 (ja)
KR (1) KR100399450B1 (ja)
AT (1) ATE201529T1 (ja)
DE (1) DE59509288D1 (ja)
HK (1) HK1004998A1 (ja)
TW (1) TW301746B (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101350226B (zh) * 2007-07-20 2011-09-07 中芯国际集成电路制造(上海)有限公司 验证检测设备检测结果是否正确的方法
JP5359570B2 (ja) 2009-06-03 2013-12-04 富士通株式会社 メモリ試験制御装置およびメモリ試験制御方法
US8370719B2 (en) 2010-05-21 2013-02-05 Intel Corporation Persistent moving read reference
KR20190047217A (ko) * 2017-10-27 2019-05-08 삼성전자주식회사 메모리 셀 어레이에 대한 테스트를 수행하는 메모리 장치 및 이의 동작 방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4409676A (en) * 1981-02-19 1983-10-11 Fairchild Camera & Instrument Corporation Method and means for diagnostic testing of CCD memories
US4816757A (en) * 1985-03-07 1989-03-28 Texas Instruments Incorporated Reconfigurable integrated circuit for enhanced testing in a manufacturing environment
EP0387379B1 (de) * 1989-03-16 1995-01-18 Siemens Aktiengesellschaft Integrierter Halbleiterspeicher vom Typ DRAM und Verfahren zu seinem Testen
EP0411594A3 (en) * 1989-07-31 1991-07-03 Siemens Aktiengesellschaft Circuit and method for testing the reliability of the function of a semi-conductor memory

Also Published As

Publication number Publication date
KR960035660A (ko) 1996-10-24
ATE201529T1 (de) 2001-06-15
US20010040832A1 (en) 2001-11-15
KR100399450B1 (ko) 2003-12-18
JPH08263997A (ja) 1996-10-11
EP0732703A1 (de) 1996-09-18
TW301746B (ja) 1997-04-01
EP0732703B1 (de) 2001-05-23
US6366511B2 (en) 2002-04-02
DE59509288D1 (de) 2001-06-28
JP3878243B2 (ja) 2007-02-07

Similar Documents

Publication Publication Date Title
US6781908B1 (en) Memory having variable refresh control and method therefor
EP0543408B1 (en) Semiconductor memory and screening test method thereof
US6781862B2 (en) Semiconductor memory device
CN100570750C (zh) 半导体存储器和半导体存储器的预烧测试方法
EP0892408A3 (en) Ferroelectric memory device
KR910010519A (ko) 반도체 메모리 회로장치
JPH11501441A (ja) アレイ・エッジ部での基準検知を具備するｄｒａｍ
CA2212089A1 (en) Bist memory test system
KR910003674A (ko) 반도체기억장치
Womack et al. A 16 kb ferroelectric nonvolatile memory with a bit parallel architecture
US4300210A (en) Calibrated sensing system
TW370621B (en) Apparatus and method for test time reduction in a dynamic random access memory
US6297985B1 (en) Cell block structure of nonvolatile ferroelectric memory
EP1006444A2 (en) Method and apparatus for testing random access memory device
KR970067367A (ko) 단일칩 동기식 다이너믹 랜덤 억세스 메모리(dram) 시스템
EP1665275B1 (en) Method and apparatus for read bitline clamping for gain cell dram devices
US6026009A (en) Ferroelectric memory device increasing voltage on a bit line to remove dummy cells and a reference voltage generator
US5844915A (en) Method for testing word line leakage in a semiconductor memory device
US6288930B1 (en) Semiconductor memory device
HK1004998A1 (en) Method for testing semiconductor memory circuit
EP0987717B1 (en) Method and apparatus for testing dynamic random access memory
US5710738A (en) Low power dynamic random access memory
KR950010085A (ko) 다이나믹 랜덤 억세스 메모리
US6788606B2 (en) Method and apparatus for refreshing memory cells
TW238387B (en) Decoding circuit for semiconductor memory device and its process

Legal Events

Date Code Title Description
PF Patent in force
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20050315