GB2338594A - A method of forming a selective metal layer - Google Patents

A method of forming a selective metal layer Download PDF

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GB2338594A
GB2338594A GB9822332A GB9822332A GB2338594A GB 2338594 A GB2338594 A GB 2338594A GB 9822332 A GB9822332 A GB 9822332A GB 9822332 A GB9822332 A GB 9822332A GB 2338594 A GB2338594 A GB 2338594A
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metal layer
forming
layer
film
chamber
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Sang-Bom Kang
Yun-Sook Chae
Sang-In Lee
Hyun-Seok Lim
Mee-Young Yoon
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C23C16/0272—Deposition of sub-layers, e.g. to promote the adhesion of the main coating
    • C23C16/0281—Deposition of sub-layers, e.g. to promote the adhesion of the main coating of metallic sub-layers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/08—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
    • C23C16/14—Deposition of only one other metal element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
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  • Physics & Mathematics (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Chemical Vapour Deposition (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

In a method of forming a selective metal layer a sacrificial metal layer is selectively deposited on a conductive layer by supplying a sacrificial metal source gas which deposits selectively on a semiconductor substrate having an insulating film and the conductive layer. Sacrificial metal atoms and a halide are formed, and the sacrificial metal layer is replaced with a deposition metal layer such as titanium (Ti) or platinum (Pt), by supplying a metal halide gas having a halogen coherence smaller than the halogen coherence of the metal atoms in the sacrificial metal layer. If such a process is used to form a capacitor lower electrode or form an ohmic layer on the bottom of a contact hole, a metal layer can be selectively formed at a temperature of 500‹C or lower.

Description

2338594 1 A METHOD OF FORMING A SELECTIVE METAL LAYER The present
invention relates to a method of manufacturing semiconductor devices, and more particularly, to a method of forming a selective metal layer and methods of forming a capacitor of a semiconductor device and filling a contact hole using the same.
As semiconductor devices become highly integrated and complicated, a metal layer must often be selectively formed while manufacturing, the semiconductor devices. Inaprocessfor manufacturing a capacitor of a semiconductor device, a lower electrode is formed using a metal instead of-polysilicon to obtain high capacitance, thereby achieving a metal insulator silicon (MIS) or metal insulator metal (MIM) structure. Or, in a process for filling a contact hole. an ohmic layer is formed on the bottom of a small contact hole having a high aspect ratio. The above two processes have many difficulties.
In the manufacturing process of the capacitor having the metallic lower electrode, it is very difficult to -selectively deposit a metal layer without patterning the metal layer on a hemispherical grain (HSG) polysilicon lower electrode. At present, such technology is not known at all. Also, in order to use PZT(Pb(Zr,T')03 or BST(BaSrT'03), having a Perovskite structure, as a high dielectric film of a capacitor. it is preferable that platinium (Pt), which is not oxidized and has excellent leakage current properties, is used instead of an existing polysilicon electrode, when a dielectric film is deposited. However, when a metal layer such as a platinum film is deposited by a blanket method not a selective method, etching is hard. That is, when the platinum film formed by the blanket method is dry-etched using chlorine (Cl,) gas as an etchant, PtClx generated as a by-product of etching is a non volatile conductive polymer. Thus, a process for removing the PtClx by wet etching must be additionally performed. In the wet etching process, since part of a platinum lower electrode is etched together, it is difficult to perform a repeatable process in a manufacturing process of a dynamic random access memory (DRAM) which requires fine patterning.
Also, the ohmic layer is formed on the bottom of the contact hole by forming a highly conductive metal having a high melting point, such as titanium, by plasma enhanced chemical vapor deposition (PECVD) or sputtering. However, when sputtering is used to form the 2 ohmic layer, step coverage is low. The PECV1) is not suitable to apply to an actual process, since leakage current is increased by a high deposition temperature of 600'C or more and thus the electrical characteristics of the semiconductor devices are deteriorated.
In addition, if the ohmic layer such as a titanium (Ti) layer is formed by sputtering, and a barrier layer, e.g., a titanium nitride (TiN) layer, is formed on the ohmic layer by chemical vapor deposition (CVD), the ohmic layer may be corroded and the interface between the ohmic layer and the barrier layer may lift. If the barrier layer (TiN) is formed on a titanium (Ti) ohmic layer by sputtering, the interface between the ohmic layer and the barrier layer does not lift. However, when a plug layer for filling the contact is formed using tungsten by CVI) in a subsequent process, the lifting problem occurs.
Therefore. a method is required of selectively forming a metal layer at a temperature of 50WC or lower where the electrical characteristics of semiconductor devices are not 1 degraded. However, at present, it is very difficult to realize such a technique in the process of forming the lower electrode of the capacitor and forming the ohmic layer of the contact hole.
According to a first aspect of the present invention, a method of forming a selective metal layer comprising the steps of:
introducing into a chamber a semiconductor substrate on which an insulating film and a conductive layer are formed, and supplying a purge gas into the chamber; forming a sacrificial metal layer on only the conductive layer by supplying to the chamber a sacrificial metal source gas which is deposited selectively with respect to the insulating film and the conductive layer; and.
replacing the sacrificial metal layer with a deposition metal layer by supplying to the chamber a metal halide gas having a halogen coherence smaller than the halogen coherence of metal atoms in the sacrificial metal layer.
Preferably, the insulating film is an oxide film (SiO,) or a complex film including the oxide film, and that the conductive layer is formed of silicon doped with impurities., or metal.
3 Preferably, the metal of the deposition metal layer is one selected from the group consisting of titanium, tantalum, zirconium, hafnium, cobalt, molybdenum, tungsten, nickel and platinum. It is preferable that T'C14 is used as the metal halogen compound gas when the deposited metal is titanium. Also, it is preferable that a gas obtained by dissolving platinic chloride (C16H6P0 or PtC12 in water (H.)0) or alcohol and vaporizing the C16H6Pt or PtC12 is used as the metal halogen compound gas when the deposited metal is platinum.
According to a second aspect of the present invention, a method of forming a capacitor of a semiconductor device comprising the steps of:
(a) forming a contact hole exposing a source region of a semiconductor substrate, by forming an insulating Iffirh on the semiconductor substrate and patterning the insulating film; (b) forming a conductive layer filling the contact hole and covering the insulating film; (c) forming a cQnductive layer pattern connected to the contact hole by processing the conductive layer; (d) introducing the semiconductor substrate into a chamber and supplying a purge gas into the chamber; (e) forming a sacrificial metal layer on only the conductive layer, by supplying to the chamber a sacrificial metal source gas which is deposited selectively with respect to the insulating film and the conductive layer, (f) replacing the sacrificial metal layer with a deposition metal layer by supplying to the chamber a metal halide gas having a halogen coherence smaller than the halogen coherence of metal atoms in the sacrificial metal layer: (g) forming a dielectric film on the deposition metal layer; and, (h) forming an upper electrode on the dielectric film.
According to a preferred embodiment of the present invention, the step of forming a hemispherical grain on the surface of a conductive pattern can be further comprised after the conductive layer pattern is formed.
In the preferred embodiment of the present invention, the step of siliciding the deposition metal layer follows the step of forming the deposition metal layer.
4 According to a third aspect of the present invention, a method of filling a contact hole comprising the steps of: (a) forming an insulating film on a semiconductor substrate and forming a contact hole exposing a lower film by patterning the insulating film; (b) introducing into a chamber the semiconductor substrate on which the contact hole is formed, and supplying a purge gas into the chamber; (c) forming a sacrificial metal layer on only the lower film by supplying to the chamber a sacrificial metal source gas which is deposited selectively with respect to the insulating film and the lower film; (d) replacing the sacrificial metal layer with a deposition metal layer by supplying to the chamber a metal halide gas having a halogen coherence smaller than the halogen coherence of metal atoms in the sacrificial metal layer; and, (e) forming a conductive layer filling the contact hole.
According to the preferred embodiment of the present invention, the purge gas is continuously supplied, or first supplied in a predetermined amount to purge and periodically supplied in predetermined amounts after the sacrificial metal layer is formed and replaced with the deposition metal layer. Preferably, a purge gas supplied after the deposited metal layer is replaced has a longer supply time and greater amount of supply than a purge gas supplied in other steps.
Also, it is preferable that the step of forming a barrier layer, e.g., a TiN layer, on a deposition metal layer is further comprised after the step of replacing the sacrificial metal layer with the deposition metal layer.
In the present invention, in a process for manufacturing semiconductor devices, a specific metal selectively formed at a temperature of 50WC or lower is applied to the process for forming a lower electrode of a capacitor, thereby forming a metallic lower electrode of a capacitor without serious process difficulty. Also, when the ohmic layer is formed on the bottom surface of the contact hole, property degradation or lifting of a thin film due to corrosion can be prevented, while simultaneously increasing step coverage.
c Examples of the present invention will now be described in detail with reference to the accompanying drawings, in which:
FIG, 1 is a flowchart illustrating a process for forming a selective metal layer, according to the present invention FIGS. 2A and 213 are gas flow graphs of the process for forming a selective metal layer according to the present invention; FIG. 3 is a flowchart illustrating a method of forming a capacitor using the selective metal layer formation process according to the present invention, FIGS. 4A through 417 are cross-sectional views illustrating a method of forming a capacitor using the process for forming a selective metal layer, according to a first embodiment of the present invention; FIGS. SA through SF are cross-sectional views illustrating a method of forming a capacitor using the process for forming a selective metal layer, according to a second embodiment of the present invention; FIGS. 6A through 6C are cross-sectional views illustrating a method of forming a capacitor using the process for forming a selective metal layer, according to a third embodiment of the present invention; FIG. 7 is a flowchart showing a method of filling a contact hole using the selective metal layer formation process according to the present invention; and, FIGS. 8A through 8E are cross-sectional views illustrating a contact hole filling method using the selective metal layer formation process, according to a fourth embodiment of the present invention.
Referring to FIG. 1, first, a semiconductor substrate on which an insulating film and a conductive layer are formed is introduced into a chamber of a semiconductor manufacturing device, in step 100. Here, the insulating film is an oxide film (S'02) which does not absorb a metal deposited to form a selective metal layer, or a complex film of the oxide film. The conductive layer is formed of a metal such as titanium nitride (TiN) or polysilicon doped with impurities having hydrogen termination radical, on which aluminum AI can be easily and selectively deposited. Next, a gas mixed with hydrogen H2 and silane SiH4 as a purge gas is supplied to the chamber to purge the inside of the chamber, in step 110. Here, the purge gas can be supplied by the following two methods. First, the purge gas can be continuously supplied in a predetermined amount from the beginning. Second. the purge gas 6 is supplied to the chamber after supplying a sacrificial metal source gas or a metal halide gas, to purge the chamber, and a predetermined amount of purge gas can be periodically supplied after the steps 120 of depositing a sacrificial metal and the step 140 of replacing the sacrificial metal layer with a deposition metal layer.
A sacrificial metal layer made of aluminum (AI) is formed on the surface of the conductive layer by supplying to the chamber dimethyl aluminum hydride (DMAH: (C113)2ALH) or dimethyl ethylamine alane (DMEAA: (CH3)2C,>H5N:AIH3) as a sacrificial metal source gas, in step 120. Here, the reason why the sacrificial metal layer is made of aluminum is that aluminum has a halogen-family element such as Cl, Br, F or 1, and the highest Gibbs free energy and that various precursors for aluminum have already been developed. Precursors for the deposition of aluminum include di-i-butylaluminum hydride K4H9)2AM), tri-i butylauminum K4HO3A1), triethylanuminum ((C2H5)2A1), trimethylaluminum QC113)3A1), trimethylamine (A1H3N(CH3)3), dimethyl aluminum hydride ((CH3)2ALH), and dimethyl ethylamine alane ((CH3)2C,HSN:AIH3). The dimethyl aluminum hydride ((CH3)2ALH) (hereinafter called 'DMAH') and dimethyl ethylamine alane ((CH3)2CFl5N:A1H3) (hereinafter called 'DMEAA') are not deposited on an insulating film such as the oxide film (SiO,)) but they are deposited selectively on only a metal such as TiN or silicon which is doped with the impurities of hydrogen (H,) termination radical. That is, the DMAH and DMEAA are deposited not on the insulating film of the semiconductor substrate in the chamber but selectively on only the conductive layer.
Then, a purge gas is supplied to the chamber having the semiconductor substrate on which the sacrificial metal layer is selectively formed, to purge the sacrificial metal source gas from the chamber, in step 130.
Next, T'C14 is changed into AIC1x and aluminum of the sacrificial metal layer is replaced with a deposition metal layer made of titanium, by reacting the semiconductor substrate with T'C14, as a metal halide gas including a metal for deposition, supplied into the chamber, in step 140. Here, the metal in the metal halide gas has a weaker halogen coherence than a metal atom of the sacrificial metal layer, so that the metal atom of the sacrificial metal layer reacts with the metal halide gas. That is, the Gibbs free energy of TiC14 is 678.3Ulmol at 427T (70OK), which is higher than that of most metal halides, whereas the Gibbs free 7 energy of AIC16 is 1121.9kJ/mol which is higher than that of T'C14, so that the metal atoms of the sacrificial metal layer react with the metal halide gas. Thus, aluminum atoms of the sacrificial metal layer are separated from the surface of the conductive layer and react with a chlorine (Cl) gas having a higher coherence, thus becoming AIC1X of a gaseous state.
Also, titanium (Ti) resolved from TiC14 is deposited in the empty places where the aluminum atoms separate from the surface of the conductive layer. When the metal halide gas having a smaller Gibbs free energy, i.e., the coherence between a sacrificial metal and the halogen atom, is supplied into the chamber having the semiconductor substrate on which the sacrificial metal is formed. a metal layer can be selectively formed. The deposition metal layer formed as described above can use titanium, tantalum, zirconium, hafnium, cobalt, molybdenum, tungsten, nickel or platinum.
Here, when the deposited metal is titanium, TiC14 'S used as the metal halide gas, and when the deposited metal is platinum, a gas obtained by melting and vaporizing platinic chloride (C16H6P0 or Pte12 in water (H,O) or alcohol is used as the metal halide gas. Also, when the deposited metal is cobalt, either cobalt chloride CoCI, cobalt fluoride CoF, or cobalt iodide Col, is used as the metal halide gas. Here, since platinic chloride (C16H6Pt) or PtCl.), which is a metal halide containing platinum, is solid, it must be used after being melted in a solvent and vaporized. Since platinum is inert compared with other metals. it has a lower coherence with the halogen atom. Accordingly, when the platinum reacts with the sacrificial metal layer such as aluminum, it can be easily deposited.
When the deposited metal is molybdenum, either bis (cyclopentadienyl) molybdenum dichloride (C5H5)2MOC11, cyclopentadienylmolybdenum tetrachloride C5H5MOC14, molybdenum MoF6, Molybdenum fluoride MoC131MOC15, or molybdenum iodide MoI, is used as the metal halide gas. When the deposited metal is nickel, either 1(C6H5)2PCH,CH2CH,,P(C6H5)2]NiCI,, (1,2-bis(diphenylphosphineo) propane nickel), I(C6H5)5C512MBr2 (bis(triphenylphosphin) nickel bromide), K6H5)3P12MC12 (bis(triphenylphosphin) nickel chloride), [Ni(NH3)61C1, (hexaaminenickel chloride), [Ni(NH3)6112 (Hexaamine iodide), NiBr/NiBr, (nickel bromide), NiCI, (nickel chloride), NiF, (nickel fluoride), or Nil, (nickel iodide) is used as the metal hahde gas. When the deposited metal is tungsten, either bis(cyclopentadienyl)tungsten dichloride (C5H5)2WC11-, 8 tungsten bromide WWW2B1WPS, tungsten chloride WC14/WC16, or tungsten fluoride WF6 is used as the metal halide gas.
For reference, Tables 1 through 5 show the Gibbs free energies of many metal halide gases at an absolute temperature of 70OK(427C).
[Table 11 The Gibbs free energies of various gaseous compounds containing Cl at 4270C compound gibbs free compound Obs free energy compound gibbs free energy (kJ/mol) to energy (kJ/mol) (kJ/mol) All-C16 -1121.9 WC13 -626.7 BeCL, -373.1 ThC14 895.8 EuC13 -621.6 BC13 -367.7 UC15 -811.9 YbC13 -621.5 SiC13 -365.7 WCL4 -804.7 K2C12 -609.8 SnC14 -362.3 ZrC14 -777.6 Rb,Cl, -607.6 InCI3 -335.8 LaC13 -708.9 Li,Cl, -597.8 AICI.7 -305.5 PrC13 -706.9 SiC14 -569.6 TaC13 -300.1 In,C16 -703.7 AIC13 -550.1 GeC13 -299.8 CeC13 -699.5 FeC16 -526.8 MnCI,) -286.4 NdC13 -696.6 BaCI, -524.3 WC15 -285.6 Be,C14 -692.6 SrCI, -498.1 CS0 -22 7 6. 7 TiC14 -678.3 TaC14 -497.5 ZnC12 -273.5 GdC13 -674.3 CaCI, -489.1 WC14 -267.6 rbC13 -668.1 PbC14 -462.1 Ti2C11 -259.8 H0C13 -659.7 VaC14 -447.2 GaC12 -258.4 ErC13 -651.7 GeC14 -410.8 Sb05 -249.9 Cs,Cl, -644.1 MgO, -407.8 CU3C13 -242.9 TmC13 -641.5 FeC14 -406.5 PC13 -242.3 TaCI5 -636.6 GaC13 -388.6 FeC13 -240.6 9 [Table 21
The Gibbs free energies of many gaseous compounds containing iodine 1 at 427C compound gibbs free compound gibbs free energy compound gibbs free energy (kJ/moI) (kJ/mol) energy (kJ/mol) Th14 -512 Zr14 -409 Ti14 - 320 A1,16 -510 Hf14 -405 PM4 -266 KIL) -480 Dy13 -402 Mg12 -239 Lah -457 Tm13 -399 CUI -237 Pr13 -448 W3 -388 CSI -220 Ce13 -442 Bal, -380 TaI, -202 Nd13 -438 U14 -377 S'14 -150 1-111, -427 Srl) -353 HI -11.8 Er13 -410 Cal, -338 - [Table 31
The Gibbs free energies of many gaseous compounds containing bromine (Br) at 427C compound gibbs free compound gibbs free energy compound gibbs free energy (kJ/mol) (kJ/mol) energy (kJ/mol) Al,Br6 -860 HoBr3 -567 CaBr, -435 Mg2W4 -764 ErBr3 -566 PbW4 -428 ThBr4 -743 TmBr3 -563 TaBrS -424 HfBr4 -639 ThBr3 -559 EuBr, -413 ZrW4 -627 DyBr3 -559 SiBr4 -387 LaBr3 -621 GdBr3 -551 CU3W3 -187 CeBr3 -616 U2Br, -534 Wk -139 PrBr3 -612 TiBr4 -527 HBr -58.6 UBr4 -602 Na2Br, -510 - NdBr3 -598 SrBr, -453 [Table 41
The Gibbs free energies of many gaseous compounds containing fluorine (F) at 4270C compound gibbs free compound gibbs free energy compound gibbs free energy (kJ/mol) (kJ/mol) energy (kJ/mol) Al,F -2439 W4 -1592 Li3F -1457 6 3 U176 -1953 ZrF4 -1587 PrF3 -1231 TaF, -1687 S21710 -1581 As175 -1080 Th174 -1687 SiF4 -1515 CuF2 -287.3 M92F4 -1624 W176 -1513 HF -277.1 NbF5 -1607 TiF4 -1467 - [Table 51
The Gibbs free energies of many gaseous compounds containing platinum (Pt) at 427C compound gibbs free compound gibbs free energy compound gibbs free energy (kJ/mol) (kJ/mol) energy (kJ/mol) Ptcl, -78.6 PtC13 -105.9 PtC14 -141.9 PtBr, +29.2 PtBr3 +27.3 PtBr4 -38.2 Pt14 +62.8 - - At the end, after the metal layer such as titanium, tantalum, zirconium, hafnium, cobalt, molybdenum, tungsten, nickel or platinum is formed by a replacement method using the metal halide gas, a purge gas is supplied to the chamber, in step 150. Here, the supply time and amount of purge gas are greater than in the step of forming the sacrificial metal layer 0 and in other steps. Therefore, the metal halide gas such as TiClx adsorbed in a portion such as the insulating film, but not the sacrificial metal layer, is desorbed and purged.
FIGS. 2A and 213 are gas flow graphs of the selective metal layer formation process according to the present invention, wherein a Y axis denotes the supply state of a gas, and a X axis denotes time. FIG. 2A is the gas flow graph when a purge gas mixed with hydrogen (H2) and silane (SiH4) is supplied periodically. FIG. 2B is the gas flow graph when the purge gas is continuously supplied from the beginning. When the purge gas is 30 periodically supplied as shown in FIG. 2A, a purge gas 150 is supplied for a longer time and 11 in a larger amount, right after a metal halide gas is supplied, to prevent the metal halide gas from being absorbed into the insulating film and to sufficiently desorb the metal halide gas from the insulating film. To be more brief, a purge gas 110 is first supplied, and a sacrificial metal source gas 120 is then supplied, to form a sacrificial metal layer. When a purge gas is periodically supplied, a purge gas 130 is supplied to the chamber to purge the remaining sacrificial metal source gas. Also, a metal halide gas including a metal to be deposited is supplied to replace a sacrificial metal layer with a deposition metal layer. At this time, a compound gas of aluminum, being a sacrificial metal, and halogen atoms remains in the chamber, and this is again purged to the outside of the chamber by supplying the purge gas 150 to the chamber. This process is set as a cycle, and when this cycle is repeated, the thickness of a deposited metal can be easily controlled. and step coverage problems can be solved.
FIG. 3 is a flowchart illustrating a method of forming a capacitor using the selective metal layer formation process according to the present invention.
Referring to- FIG. 3. a lower structure such as a transistor is formed. and an insulating film as an interlayer dielectric (ILD) is formed using an oxide film or a complex film of the oxide film. A contact hole exposing a source area of a transistor is formed by performing photolithography on the insulating film, in step 300. Optionally, an ohmic layer and barrier layer can be formed using a material such as titanium (Ti) or titanium nitride (TiN), to improve conductivity between the contact hole and a filling material and prevent diffusion, in step 310. Then, a conductive layer covering the surface of the insulating film is formed by filling the contact hole using a conductive material for a lower electrode, e.g., a metallic material such as TiN or polysilicon doped with impurities. Here, it is preferable that the impurities doped in the polysilicon have hydrogen termination radical to allow a sacrificial metal layer to be selectively formed in the subsequent process. Next, a conductive layer pattern for use as lower electrode connected to the contact hole is formed by patterning the conductive layer, in step 320. The conductive layer pattern can be formed after forming a plug layer for filling only the inside of the contact hole, or by simultaneously depositing and patterning a conductive layer for filling the inside of the contact hole. Here, the step 330 of forming hemispherical grains (HSG) on the conductive layer pattern can be optionally performed to increase the surface area of the lower electrode. Then, the semiconductor 12 substrate with the HSG is introduced into a chamber of semiconductor manufacturing equipment, and a purge gas is supplied continuously or periodically as shown in FIGS. 2A and 2B, in step 340. DMAH ((C113)2ALH) or DMEAA ((CH3)2C2HSN:AIH3) being a sacrificial metal source gas is supplied to the chamber. Then, a sacrificial metal layer, being an aluminum layer, is formed selectively on only the conductive layer, in step 350. A metal halide gas containing a metal to be deposited, e.g., T'C14, platinic chloride (C16H6Pt), or PC,, is melted in water (H20) or alcohol and then vaporized, and the vapor is supplied to form a deposition metal layer made of Ti or Pt using a replacement method, in step 360.
Then, a silicide layer can be optionally formed by conducting a thermal treatment on the deposition metal layer, in step 365. A nitride film can be optionally formed using ammonia plasma or rapid thermal nitridation (RTN), in step 370. An oxide film can optionally be formed by performing a thermal treatment at an oxygen atmosphere, in step 375. Then, the nitride film and oxide film can be used as the dielectric film of a capacitor.
Here, when Ti is used as the first deposition metal layer, TiN is formed as the nitride film, and the selective metal layer formation process shown in FIG. 1 is repeated, thereby forming a second deposition metal layer made of platinum in step 373. The step 373 is optional.
Thereafter, the dielectric film is deposited on the resultant structure, in step 380. The dielectric film can be a complex film of an oxide film and a nitride film, or can be formed of a monatomic metal oxide selected from the group consisting of Ta205, TiO2, ZrO", All-03, and Nb,05, a monatomic metal nitride such as AIN, or a polyatomic metal oxide selected from the group consisting of SM03, M(Pb(ZrJO03, and BST(BaSM03).
Finally, an upper electrode is formed on the semiconductor substrate on which the dielectric film is formed, using polysilicon or a metal such as TiN, TiAIN, or TiSiN, in step 390.
FIGS. 4A through 4F are cross-sectional views illustrating a method of forming a capacitor using a selective metal layer formation process according to a first embodiment of the present invention.
Referring to FIG. 4A, a lower structure (not shown) such as a transistor is formed on a semiconductor substrate 400, and an oxide film or a complex film of the oxide film is formed as an interlayer dielectric (ILD) 402 on the resultant structure. A contact hole 404 exposing 1 - 13 a source area of the transistor is formed by patterning the ILD 402. Polysilicon which is doped with impurities and has hydrogen termination radical is deposited on the semiconductor substrate in which the contact hole 404 is formed, and the deposited polysilicon is patterned, thus forming a lower electrode conductive layer pattern 406 connected to the contact hole.
Referring to FIG. 4B, a deposition metal layer 408 such as Ti or Pt is formed on the resultant structure, using the selective metal layer deposition method shown in FIG. 1. Here, a process for forming HSG can optionally be performed on the conductive layer pattern 406 before the deposition metal layer is formed, in order to increase the surface area of the lower electrode of the capacitor. 71us, according to the present invention, a metal can be deposited on the HSG surface without patterning a lower electrode such as an HSG type lower electrode, on account of the selective metal layer deposition.
Referring to FIG. 4C. a nitride film 410 is formed on the semiconductor substrate on which the deposition metal layer 408 is formed, by nitridation or RTN using ammonia plasma (NH3 plasma). The n-itride film 410 prevents an oxidation which degrades capacitance from forming on---theinterface between the lower electrode and the dielectric film, when the dielectric film is deposited in the subsequent process.
Referring to FIG. 41), an oxide film 412, e.g., titanium oxide (TiO.2), is formed by performing a thermal treatment in oxygen atmosphere on the resultant structure. The nitride film 410 and the oxide film 412 can be used as the dielectric film.
Referring to FIG. 4E, the dielectric film 414 is formed on the resultant structure, using a monatomic metal oxide selected from the group consisting of Ta205, TiOl, Zi-0,-, A1203, and Nb205, a monatomic metal nitride such as AIN, or a polyatomic metal oxide selected from the group consisting of SM03, M(Pb(ZrJO03, and BST(BaSrT'03).
Referring to FIG. 4F, an upper electrode 416 of polysilicon or a metal is formed on the semiconductor substrate on which the dielectric film 414 is formed, thereby forming the capacitor of a semiconductor device having a structure of silicon insulator metal (SIM) or metal insulator metal (MIM).
1 1 1 14 If the capacitor of a semiconductor device is formed as described above, a photo process can be omitted since patterning is not required after the lower electrode is formed. Particularly. patterning on a lower electrode having HSG is not required, so that the lower electrode can be formed of a metal while solving many problems caused by etching.
FIGS. SA through 5F are cross-sectional views illustrating a method of forming a capacitor using a selective metal layer formation process according to a second embodiment of the present invention.
Since processes shown in FIGS. SA and 513 are the same as those in thefirst embodiment, the descriptions of these processes are omitted to avoid redundancy. Here, reference numerals correspond to those in the first embodiment for the sake of easy understanding.
Referring to FIG. 5C, a deposition metal layer 508, being the selective metal layer, is changed into a silicide layer 510 such as TiSix by performing silicidation on the semiconductor substrate on which the deposition metal layer 508 is formed.
Referring to FIG. 5D. a nitride film 512 is formed on the semiconductor substrate on which the silicide layer 510 is formed, using NH, plasma or by performing RTN.
Referring to FIG. 5E, a dielectric film 514 can be formed on the semiconductor substrate on which the nitride film 510 is formed. Here, the dielectric film 514 can be a complex film of an oxide film and a nitride film, or can be formed of a monatomic metal oxide selected from the group consisting of Ta.,05, T'02, Zr02, A1,03, and Nb205, a monatomic metal nitride such as AIN. or a polyatomic metal oxide selected from the group consisting of SM03, M(Pb(Zr,Ti)03, and BST(BaSrTio3).
Referring to FIG. 5F, an upper electrode 516 of polysilicon or a metal is formed on the semiconductor substrate on which the dielectric film is formed, thereby forming the capacitor of an SIM or MIM structure.
FIGS. 6A through 6C are cross-sectional views illustrating a method of forming a capacitor using a selective metal layer formation method according to a third embodiment of the present invention.
This embodiment can use the selective metal layer deposition process twice, to prevent a highly-resistive platinum silicide (PtSix) from forming when a platinum film is deposited selectively on a capacitor lower electrode.
Referring to FIG. 6A, a lower structure (not shown) such as a transistor is formed on a semiconductor substrate 600, and an inter layer dielectric (ILD) 602 is formed on the resultant structute, using an oxide film or a complex film of the oxide film. A contact hole exposing a source region of the transistor is formed on the semiconductor substrate 600. A plug layer 604 fQr filling the contact hole is formed using polysilicon. Titanium nitride (TiN) being a capacitor lower electrode conductive layer, connected to the plug layer 604, is blanket-deposited by chemical vapor deposition (M) or physical vapor deposition. The capacitor lower electrode conductive layer is patterned to form a capacitor lower electrode conductive film pattern 606. Then, a platinum film 608 is formed on the surface of the TiN conductive film pattern 606, using the selective metal layer formation method shown in FIG.
The capacitor lower electrode conductive film pattern 606 covered with the platinum film 608 can also be formed by the following modified method. After the contact hole exposing the source region of the transistor is formed, the plug layer 604 for filling the contact hole is formed of polysilicon doped with impurities and having hydrogen termination radical.
Titanium is selectively deposited on the surface of the exposed plug layer 604 by the selective metal layer formation method of FIG. 1, thereby forming a planer type lower electrode conductive film pattern 606. The Ti conductive film pattern 606 undergoes nitridation using NH3 plasma, or rapid thermal nitridation (RTN), to form TiN on the resultant structure.
Thereafter, the platinum film 608 is formed by the selective metal layer formation method of FIG. 1, thereby forming the capacitor lower electrode formed of the platinum film.
Referring to FIG. 6B, a dielectric film 610 is deposited on the platinum film 608. Here, the dielectric film 610 can be a complex film of an oxide film and a nitride film, or can be 16 formed of a monatomic metal oxide selected from the group consisting of Ta205, TiO, ZrO,, A1,03, and Nb.)05, a monatomic metal nitride such as AIN, or a polyatomic metal oxide selected from the group consisting of SM03, M(Pb(Zrj')03, and BST(BaSM03).
Referring to FIG. 6C, a capacitor upper electrode 612 is formed on the semiconductor substrate on which the dielectric film 610 is formed, using polysilicon or a metal such as platinum, thereby completing the formation of the capacitor of a semiconductor device using the selective metal layer formation method according to the third embodiment of the present invention.
FIG. 7 is a flowchart showing a method of filling a contact hole using the selective metal layer formation process according to the present invention.
Referring to FIG. 7, an insulating film is deposited on a semiconductor substrate on which a lower structure such as a transistor bit line is formed, using an interlayer dielectric (ILD), and a contact hole exposing a lower film is formed by patterning the ILD, in step 700.
Here, the ILD is an oxide film or a complex film of the oxide film, and the lower film is formed of TiN, or polysilicon doped with impurities and having hydrogen termination. This is to allow the selective deposition of a sacrificial metal from a sacrificial metal source gas on the lower film in a subsequent process. Also, the contact hole can be a capacitor lower electrode contact hole directly connected to the semiconductor substrate, or a metal contact hole. Next, a deposition metal layer of a material such as titanium (Ti) is formed on the bottom of the contact hole, using the selective metal layer formation method shown in FIG.
1, in steps 710, 720 and 730. The deposition metal layer formed of a conductive material such as titanium (Ti) is used as an ohmic layer, in a process for filling the contact hole.
Then, a barrier layer such as titanium nitride (TiN) is optionally formed on the ohmic layer being the deposition metal layer. by RTN, or nitridation using NH3 plasma, in step 740. A plug layer is formed of aluminum (AI) and tungsten (W) on the barrier layer, in step 750.
A conductive layer connected to the plug layer is formed in step 760. thereby completing the filling of the contact hole. Here, without specially forming the plug layer, a conductive layer for filling a contact hole can be formed directly on the barrier layer or ohmic layer.
In the step 740, the barrier layer can be formed and patterned by a blanket method of CV1) or sputtering, instead of RTN or nitridation using NH3 plasma.
FIGS. 8A through 8E are cross-sectional views illustrating a method of filling a contact hole using a selective metal layer formation process according to a fourth embodiment of the present invention.
Referring to FIG. 8A, an insulating film 802, e.g., an oxide film or a complex film of the oxide film. is formed on a semiconductor substrate 800, and a contact hole 804 exposing a lower film is formed by patterning the insulating film 802. Here, the contact hole 804 can be a capacitor lower electrode contact hole connected to the semiconductor substrate, or a metal contact hole formed in a metal interconnection process.
Referring to FIG. 8B, a deposition metal layer of a material such as titanium (Ti) is formed on the semiconductor substrate on which the contact hole 804 is formed, using the selective metal layer formation method of FIG. 1. The deposition metal layer serves as an ohmic layer 806 for improving the conductivity between the lower film and a conductive material for filling the contact hole, in the process for filling the contact hole.
Referring to FIG. 8C, a barrier layer 808 for preventing diffusion of impurities, e.g., a titanium nitride (TiN) layer, is optionally formed on the semiconductor substrate on which the ohmic layer 806 is deposited. The barrier layer can be formed by nitridation using NH3 plasma, RTN, or blanket deposition. Referring to FIG. 81), a conductive layer 810 for covering the surface of the semiconductor 25 substrate while filling the contact hole is deposited on the semiconductor substrate on which the barrier layer 808 is formed, thereby completing the contact hole filling process using the selective metal layer formation method according to the fourth embodiment of the present invention.
FIG. 8E is a cross-sectional view of a modification of FIG. 8D. Here, a plug layer 812 is formed of tungsten (W) or aluminum (AI) on the semiconductor substrate on which the barrier layer 808 is formed. Next, the plug layer 812 is removed except inside the contact 18 hole, by etchback or chemical mechanical polishing (CMP). The conductive layer 810 is then formed in contact with the plug layer 812.
In this embodiment, a relatively thin ohmic layer can be formed inside a contact hole having a high aspect ratio without problems such as lifting or corrosion, at a temperature of SOWC or lower. This renders unnecessary a process for controlling the thickness of the ohmic layer, e.g., the etchback process.
In the present invention, since a metal layer of a material such as titanium (Ti) or platinum (Pt) is selectively formed of at a temperature of 500T or lower, a lower electrode can be easily formed of a metal instead of polysilicon in the process for forming a capacitor of a semiconductor device. Therefore, many problems generated in the prior art when the lower electrode is formed of titanium or platinum can be solved. Also, in the process for forming an ohmic layer on the bottom of a contact hole, the ohmic layer having an appropriate thickness is formed selectively at low temperature on only the bottom of the contact hole, thus filling the contact hole while preventing defects such as lifting or corrosion.
19

Claims (23)

CLAIMS:
1. A method of forming a selective metal layer comprising the steps of:
introducing into a chamber a semiconductor substrate on which an insulating film and a conductive layer are formed, and supplying a purge gas into the chamber; forming a sacrificial metal layer on only the conductive layer by supplying to the chamber a sacrificial metal source gas which is deposited selectively with respect to the insulating film and the conductive layer, and.
replacing the sacrificial metal layer with a deposition metal layer by supplying to the chamber a metal halide gas having a halogen coherence smaller than the halogen coherence of metal atoms in the sacrificial metal layer.
2. A method according to claim 1, in which the insulating film or a complex film including the oxide film.
is an oxide film (SiO.,)
3. A method according to claim 1 or 2, in which the conductive layer is formed of silicon doped with impurities, or metal.
4. A method according to claim 3, in which the silicon doped with impurities has hydrogen termination radical.
5. A method according to claim 3 or 4, in which the metal is TiN.
6. A method according to any preceding claim, in which the purge gas is a mixture of hydrogen and silane.
7. A method according to any preceding claim in which the purge gas is continuously supplied, or first supplied in a predetermined amount to purge and periodically supplied in predetermined amounts after the sacrificial metal layer is formed and replaced with the deposition metal layer.
8.
A method of forming a capacitor of a semiconductor device comprising the steps of.
(a) forming a contact hole exposing a source region of a semiconductor substrate, by forming an insulating film on the semiconductor substrate and patterning the insulating film:
(b) forming a conductive layer filling the contact hole and covering the insulating film., (c) forming a conductive layer pattern connected to the contact hole by processing the conductive layer; (d) introducing the semiconductor substrate into a chamber and supplying a purge gas into the chamber; (e) forming a sacrificial metal layer on only the conductive layer, by supplying to the chamber a sacrificial metal source gas which is deposited selectively with respect to the insulating film and the conductive layer; (f) replacing the-sacrificial metal layer with a deposition metal layer by supplying to the chamber a metal halide gas having a halogen coherence smaller than the halogen coherence of metal atoms in the sacrificial metal layer; (g) forming a dielectric film on the deposition metal layer., and, (h) forming an upper electrode on the dielectric film.
9. A m6thod according to claim 8 or 9, in which the insulating film is an oxide film (SiO,,) or a complex film including the oxide film.
10. A method according to claim 8 or 9, in which the conductive layer in the step (b) is formed of polysilicon doped with impurities, or titanium nitride (TiN).
11. A method according to claim 10, wherein the polysilicon doped with impurities has hydrogen termination radical.
12. A method according to any one of claims 8 to 11, in which the purge gas in the step (d) is a mixture of hydrogen (H,) and silane (SiH4).
13. A method according to any one of claims 8 to 12. in which the purge gas in the step (d) is continuously supplied, or first supplied in a predetermined amount to purge and periodically supplied in predetermined amounts after the sacrificial metal layer is formed and replaced with the deposition metal layer.
21
14. A method according to any one of claims 8 to 13, further comprising the step of siliciding the deposition metal layer, after the step (0 of forming the deposition metal layer.
15. A method of filling a contact hole comprising the steps of:
(a) forming an insulating film on a semiconductor substrate and forming a contact hole exposing a lower film by patterning the insulating film., (b) introducing into a chamber the semiconductor substrate on which the contact hole is formed, and supplying a purge gas into the chamber, (c) forming a sacrificial metal layer on only the lower film by supplying to the chamber a sacrificial metal source gas which is deposited selectively with respect to the insulating film and the lower film.
(d) replacing the sacrificial metal layer with a deposition metal layer by supplying to the chamber a metal-halide gas having a halogen coherence smaller than the halogen coherence of metal atoms in the sacrificial metal layer; and, (e) forming a conductive layer filling the contact hole.
16. A method according to claim 15, in which the insulating film in the step (a) is an oxide film (SiO,)) or a complex film including the oxide film.
17. A method according to claim 15 or 16, in which the lower film in the step (a) is formed of silicon doped with impurities and having hydrogen termination radical, or titanium nitride (TiN).
18. A method according to any one of claims 15 or 17, in which the purge gas in the step (b) is a mixture of hydrogen (H,) and silane (SiH4).
19. A method according to any one of claims 15 to 18, in which the purge gas in the step (b) is continuously supplied, or first supplied in a predetermined amount to purge and periodically supplied in predetermined amounts after the sacrificial metal layer is formed and replaced with the deposition metal layer.
20. A method according to any one of claims 15 to 19, further comprising the step of forming a barrier layer on a deposition metal layer, after the step (d) of replacing the sacrificial metal layer with the deposition metal layer.
21. A method of forming a selective metal layer substantially as shown in andlor described with reference to any of Figures of the accompanying drawings.
22. A method of forming a capacitor substantially as shown in and/or described with reference to any of Figures of the accompanying drawings.
23. A method of filling a contact hole substantially as shown in andlor described with reference to any of Figures of the accompanying drawings.
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US8212299B2 (en) 2001-06-13 2012-07-03 Renesas Electronics Corporation Semiconductor device having a thin film capacitor of a MIM (metal-insulator-metal) structure
US9905414B2 (en) 2000-09-28 2018-02-27 President And Fellows Of Harvard College Vapor deposition of metal oxides, silicates and phosphates, and silicon dioxide
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JP7296002B2 (en) * 2018-11-15 2023-06-21 日機装株式会社 Semiconductor light emitting device and method for manufacturing semiconductor light emitting device

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US8212299B2 (en) 2001-06-13 2012-07-03 Renesas Electronics Corporation Semiconductor device having a thin film capacitor of a MIM (metal-insulator-metal) structure
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US10170321B2 (en) 2017-03-17 2019-01-01 Applied Materials, Inc. Aluminum content control of TiAIN films

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