JPH02304928A - Forming method of wiring - Google Patents
Forming method of wiringInfo
- Publication number
- JPH02304928A JPH02304928A JP12420689A JP12420689A JPH02304928A JP H02304928 A JPH02304928 A JP H02304928A JP 12420689 A JP12420689 A JP 12420689A JP 12420689 A JP12420689 A JP 12420689A JP H02304928 A JPH02304928 A JP H02304928A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- aluminum
- polysilicon
- substrate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 23
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 34
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 125000005843 halogen group Chemical group 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- YNLAOSYQHBDIKW-UHFFFAOYSA-M diethylaluminium chloride Chemical compound CC[Al](Cl)CC YNLAOSYQHBDIKW-UHFFFAOYSA-M 0.000 abstract description 4
- 238000000206 photolithography Methods 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 5
- 238000000354 decomposition reaction Methods 0.000 description 4
- 230000003197 catalytic effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000010494 dissociation reaction Methods 0.000 description 3
- 230000005593 dissociations Effects 0.000 description 3
- 229930195733 hydrocarbon Natural products 0.000 description 3
- 150000002430 hydrocarbons Chemical class 0.000 description 3
- 238000001819 mass spectrum Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical group [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 125000001309 chloro group Chemical group Cl* 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- NRUQNUIWEUZVLI-UHFFFAOYSA-O diethanolammonium nitrate Chemical compound [O-][N+]([O-])=O.OCC[NH2+]CCO NRUQNUIWEUZVLI-UHFFFAOYSA-O 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 125000002370 organoaluminium group Chemical group 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000006722 reduction reaction Methods 0.000 description 1
- 238000000682 scanning probe acoustic microscopy Methods 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は配線の形成方法に関し、さらに詳しくはアルミ
ニウム配線の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for forming wiring, and more particularly to a method for forming aluminum wiring.
[従来の技術]
光通信に代表される大容量の通信や、高速の計算機を実
現するために、より高速動作の可能な半導体集積回路の
実現が望まれている。集積回路の動作速度を決定する要
因には、個々の素子のスイッチング速度の他に配線抵抗
が挙げられる。素子の微細化が進むにつれてスイッチン
グ速度は向上してきたが、逆に配線幅が小さくなるため
配線抵抗は増加する傾向にある。従って高速の動作を得
るためには、配線の抵抗を低減することが不可欠である
。[Background Art] In order to realize large-capacity communications such as optical communications and high-speed computers, it is desired to realize semiconductor integrated circuits that can operate at higher speeds. Factors that determine the operating speed of an integrated circuit include wiring resistance in addition to the switching speed of individual elements. Although switching speed has improved as elements have become smaller, wiring resistance has tended to increase as wiring width has become smaller. Therefore, in order to obtain high-speed operation, it is essential to reduce the resistance of the wiring.
従来の配線プロセスでは、配線材料としてポリシリコン
やアルミニウムが主に用いられてきた。In conventional wiring processes, polysilicon and aluminum have been mainly used as wiring materials.
このうち、アルミニウムは、抵抗率が2.7μΩ・cm
とポリシリコンに比べて2桁以上低く、また加工も容易
であるなど、低抵抗配線材料として有利である。通常、
アルミニウム配線は、アルミニウム層をスパッタまたは
蒸着で堆積した後、フォトリソグラフィーを用いてパタ
ーニングし、さらにエツチングを行って形成される。Among these, aluminum has a resistivity of 2.7μΩ・cm
It is advantageous as a low-resistance wiring material because it is more than two orders of magnitude lower than polysilicon and is easy to process. usually,
The aluminum wiring is formed by depositing an aluminum layer by sputtering or vapor deposition, patterning using photolithography, and then etching.
[発明が解決しようとする課題]
MOSトランジスタのソース、ドレイン領域は、通常ゲ
ート電極をマスクとしてイオン打ち込みを行うセルファ
ラインプロセスにより作製されている。セルファライン
プロセスでは、まずゲート電極形成および配線形成を行
った俊、イオン打ち込みを行い、イオン打ち込み後に不
純物の活性化をはかるため高温熱処理が行われる。従っ
て、ゲート電極材料および配線材料は、打ち込み後の熱
処理に耐え得る高耐熱性のものである必要がある。[Problems to be Solved by the Invention] The source and drain regions of a MOS transistor are usually fabricated by a self-alignment process in which ions are implanted using the gate electrode as a mask. In the Selfaline process, first, after forming the gate electrode and wiring, ions are implanted, and after the ion implantation, high-temperature heat treatment is performed to activate the impurities. Therefore, the gate electrode material and the wiring material need to be highly heat resistant and able to withstand post-implant heat treatment.
しかし、アルミニウムは融点が660 ’Cと低く、熱
処理によって断線するため、ゲート電極やその周辺の配
線として用いることができない。セルファラインでない
プロセスによれば低抵抗のアルミニウムゲートを実現す
ることが可能となるが、使用するフォトマスク数が増え
、歩留まりの低下を招くという欠点がある。However, aluminum has a low melting point of 660'C and breaks due to heat treatment, so it cannot be used for gate electrodes or wiring around them. Although it is possible to realize a low-resistance aluminum gate using a non-self-line process, it has the disadvantage that the number of photomasks used increases, leading to a decrease in yield.
本発明は以上述べたような従来の課題に対処してなされ
たもので、ポリシリコン配線プロセスをそのまま用いな
がら、かつ低抵抗のアルミニウム配線を行うことのでき
る配線の形成方法を提供することを目的とする。The present invention has been made in response to the conventional problems as described above, and an object of the present invention is to provide a wiring formation method that can use the polysilicon wiring process as is and also form low-resistance aluminum wiring. shall be.
[課題を解決するための手段]
本発明は、基板上にポリシリコンよりなる配線を形成す
る工程と、分子中にアルミニウムとハロゲン原子の結合
を1個または2個含む有機アルミニウムガス雰囲気中で
前記基板を熱処理し、ポリシリコン配線の一部またはす
べてをアルミニウムに置換する工程とを備えてなること
を特徴とする配線の形成方法である。[Means for Solving the Problems] The present invention includes a step of forming a wiring made of polysilicon on a substrate, and a step of forming a wiring made of polysilicon on a substrate, and forming the wire in an organoaluminum gas atmosphere containing one or two bonds of aluminum and halogen atoms in the molecule. This method of forming wiring is characterized by comprising the steps of heat treating the substrate and replacing part or all of the polysilicon wiring with aluminum.
[作用]
以下、本発明の作用について、分子内にアルミニウムと
ハロゲン原子の結合を1個または2個含む有機金属とし
てジエチルアルミニウムクロライド((02H5)2
Al1 Cll :DEAβCβ)を例にとって説明す
る。[Function] Hereinafter, regarding the function of the present invention, diethylaluminum chloride ((02H5)2
This will be explained by taking Al1 Cll :DEAβCβ) as an example.
第2図はアルミニウム基板上にDEAβCβを供給した
ときの生成炭化水素のマススペクトルである。DEAj
Cβは、アルミニウム表面での触媒作用によってβ解離
により分解し、AβCflとC2H4を生成する。一方
、S i 02上にDEAj7G!を供給したときはラ
ジカル解裂により分解し、第3図に示すようにC2H6
、C4H1oを生成してAICβとなる。ラジカル解裂
の分解温度T1は、β解離の分解温度Toに比べ高い。FIG. 2 is a mass spectrum of hydrocarbons produced when DEAβCβ is supplied onto an aluminum substrate. DEAj
Cβ is decomposed by β dissociation under catalytic action on the aluminum surface, producing AβCfl and C2H4. On the other hand, DEAj7G on S i 02! When supplied, it decomposes by radical cleavage and becomes C2H6 as shown in Figure 3
, C4H1o is generated to become AICβ. The decomposition temperature T1 of radical dissociation is higher than the decomposition temperature To of β dissociation.
従って、基板としてアルミニウムが部分的に堆積された
SiO2を用いた場合、前記基板上にD巳AI C1が
供給されると、基板温度To以上T1以下においては、
DEAfl C2はアルミニウム上でのみA470βに
分解する。同様に3i表面も、アルミニウム基板表面で
認められる触媒作用を有するため、DEAICffiは
これらの表面上で選択的にAll C1に分解する。Therefore, in the case of using SiO2 on which aluminum is partially deposited as a substrate, when Dami AI C1 is supplied onto the substrate, at the substrate temperature of To or higher and T1 or lower,
DEAfl C2 decomposes to A470β only on aluminum. Similarly, 3i surfaces also have the catalytic activity observed on aluminum substrate surfaces, so DEAICffi selectively decomposes to All C1 on these surfaces.
Si基板上においては、分解により生じたAItC2は
、3iにより次式に示すように還元される。On the Si substrate, AItC2 generated by decomposition is reduced by 3i as shown in the following formula.
4Aj20β+3i→
4Aβ+SiCβ4 ・・・(1)従って、5i0
2上にポリシリコン配線を形成し、DEAICI!雰囲
気で熱処理すると、ポリシリコン部分においてのみDE
Aj2 Clが分解して八βC!となり、(1)式の還
元反応により5ih(A2に置換される。すなわち直接
A1配線を行ったのと同じ効果が得られる。4Aj20β+3i→ 4Aβ+SiCβ4...(1) Therefore, 5i0
Form a polysilicon wiring on 2 and DEAICI! When heat treated in an atmosphere, DE occurs only in the polysilicon part.
Aj2 Cl decomposes into 8βC! Then, by the reduction reaction of formula (1), 5ih(A2) is substituted. That is, the same effect as directly wiring A1 can be obtained.
本発明によるアルミニウム配線の形成は、イオン打ち込
み後のアニールを行った後で行うことができるので、本
発明による配線プロセスは、ポリシリコンの配線プロセ
スと同等の高耐熱性を有する。Since the aluminum wiring according to the present invention can be formed after performing annealing after ion implantation, the wiring process according to the present invention has high heat resistance equivalent to that of a polysilicon wiring process.
さらに、ポリシリコン配線の表面をAでで置換して形成
した配線は、ポリシリコン配線よりも低抵抗で、また八
で金属のみによる配線と比べてエレクトロマイグレーシ
ョンが減少する。Furthermore, a wiring formed by replacing the surface of a polysilicon wiring with A has a lower resistance than a polysilicon wiring, and electromigration is reduced compared to a wiring made only of metal.
[実施例]
以下、本発明の一実施例について、図面を用いて詳細に
説明する。[Example] Hereinafter, an example of the present invention will be described in detail using the drawings.
第1図は本発明によるアルミニウム配線の形成工程を示
す配線部の断面図である。基板としては、第1図(a)
に示すように、S i (too)基板101上に10
0人の熱酸化5i02層102.5000へのノンドー
プポリシリコン層103が順次形成されているものを用
いた。FIG. 1 is a cross-sectional view of a wiring portion showing the process of forming an aluminum wiring according to the present invention. As for the substrate, Fig. 1(a)
As shown in FIG.
A non-doped polysilicon layer 103 was sequentially formed on a thermally oxidized 5i02 layer 102.5000.
第1の工程において、前記基板101上に、フォトリソ
グラフィーにより第1図(b)に示す幅5000人のポ
リシリコン配線103aを形成した。引き続き第2の工
程においては、前記ポリシリコン配線基板をDEAIC
j!雰囲気中で熱処理し、第1図(C)に示すアルミニ
ウム配線104を形成した。In the first step, a polysilicon wiring 103a having a width of 5,000 lines as shown in FIG. 1(b) was formed on the substrate 101 by photolithography. Subsequently, in a second step, the polysilicon wiring board is coated with DEAIC.
j! Heat treatment was performed in an atmosphere to form aluminum wiring 104 shown in FIG. 1(C).
熱処理は、90 Torrの水素雰囲気中で行い、熱処
理条件は、基板温度を340℃、熱処理時間を3分、D
EAJ CJ!分圧を0.05Torrとした。The heat treatment was performed in a hydrogen atmosphere of 90 Torr, and the heat treatment conditions were: substrate temperature at 340°C, heat treatment time at 3 minutes, D
EAJ CJ! The partial pressure was set to 0.05 Torr.
上記熱処理後、S i 02部分にはなんら堆積物は認
められなかった。オージェ電子分光により分析を行った
結果、ポリシリコン配線はすべてアルミニウムに置換さ
れていることが確認された。置換されたアルミニウム配
線の抵抗率を測定したところ、2.9μΩ・cmであり
、バルクのアルミニウムの抵抗率2.7μΩ・cmとほ
ぼ等しい値が1qられた。After the above heat treatment, no deposits were observed in the S i 02 portion. Analysis using Auger electron spectroscopy confirmed that all polysilicon wiring had been replaced with aluminum. When the resistivity of the replaced aluminum wiring was measured, it was found to be 2.9 μΩ·cm, which is approximately the same value as the resistivity of bulk aluminum, 2.7 μΩ·cm.
次に、熱処理時間を30秒として同様の処理を行った。Next, the same treatment was performed with a heat treatment time of 30 seconds.
この場合、表面から1000人だけがA2に置換されて
いることがわかった。従って、熱処理時間を調整するこ
とにより、Af!に置換される割合を制御できることが
確認された。In this case, it was found that only 1000 people from the surface were substituted with A2. Therefore, by adjusting the heat treatment time, Af! It was confirmed that it is possible to control the rate of substitution.
本実施例では、八で原子を含む有機金属とじてジエチル
アルミニウムクロライドを用いたが、本発明はこれに限
定されず、ジメチルアルミニウムクロライド、ジイソブ
チルアルミニウムクロライド、エチルアルミニウムジク
ロライド、メチルアルミニウムジクロライド、イソブチ
ルアルミニウムジクロライドを用いた場合も同様の効果
が得られる。さらにこれらの分子中のアルミニウムとハ
ロゲン原子の結合における塩素原子が、フッ素、臭素、
ヨウ素で置き換えられたものについても同様の効果が得
られる。In this example, diethylaluminum chloride was used as the organic metal containing an atom at 8, but the present invention is not limited thereto. A similar effect can be obtained when using . Furthermore, the chlorine atom in the bond between the aluminum and halogen atoms in these molecules is fluorine, bromine,
A similar effect can be obtained with iodine substituted.
また、本実施例では、減圧下での熱処理を示したが、本
発明におけるアルミニウム選択形成は、有機アルミニウ
ムの分解が基板表面の触媒作用により選択的に起こるこ
とを刊用したものなので、常圧下での熱処理でも同様の
効果が得られる。Furthermore, although this example shows heat treatment under reduced pressure, the selective formation of aluminum in the present invention is based on the fact that the decomposition of organoaluminium occurs selectively due to the catalytic action of the substrate surface. A similar effect can be obtained by heat treatment.
[発明の効果]
以上説明したように、本発明の方法を用いれば、ポリシ
リコン配線プロセスをそのまま用い、ざらにポリシリコ
ンプロセスの高耐熱性を維持しながら抵抗の低いアルミ
ニウム配線を形成することができる。従って本発明によ
り、集積度が高く、かつ高速の半導体集積回路を実現す
ることができる。[Effects of the Invention] As explained above, by using the method of the present invention, it is possible to form aluminum wiring with low resistance while maintaining the high heat resistance of the polysilicon process using the polysilicon wiring process as is. can. Therefore, according to the present invention, a semiconductor integrated circuit with a high degree of integration and high speed can be realized.
第1図は本発明の一実施例を工程順に示す配線部の断面
図、第2図はAβ基板上にDEAJICJ!を供給した
ときに生成される炭化水素のマススペクトルを示す図、
第3図はS i 02基板上にDEAN C9を供給し
たときに生成される炭化水素のマススペクトルを示す図
でおる。
101・・・S i (100)基板
102・・・S i 02
103・・・ポリシリコン
103a・・・ポリシリコン配線
104・・・アルミニウム配線FIG. 1 is a cross-sectional view of a wiring section showing an embodiment of the present invention in the order of steps, and FIG. 2 is a diagram showing DEAJICJ! A diagram showing the mass spectrum of hydrocarbons produced when supplying
FIG. 3 is a diagram showing the mass spectrum of hydrocarbons produced when DEAN C9 is supplied onto an S i 02 substrate. 101...S i (100) Substrate 102...S i 02 103... Polysilicon 103a... Polysilicon wiring 104... Aluminum wiring
Claims (1)
程と、分子中にアルミニウムとハロゲン原子の結合を1
個または2個含む有機アルミニウムガス雰囲気中で前記
基板を熱処理し、ポリシリコン配線の一部またはすべて
をアルミニウムに置換する工程とを備えてなることを特
徴とする配線の形成方法。(1) The process of forming wiring made of polysilicon on the substrate and forming a bond between aluminum and halogen atoms in the molecule.
1. A method for forming wiring, comprising the step of heat-treating the substrate in an organic aluminum gas atmosphere containing one or two polysilicon wirings, and replacing part or all of the polysilicon wiring with aluminum.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12420689A JPH02304928A (en) | 1989-05-19 | 1989-05-19 | Forming method of wiring |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12420689A JPH02304928A (en) | 1989-05-19 | 1989-05-19 | Forming method of wiring |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02304928A true JPH02304928A (en) | 1990-12-18 |
Family
ID=14879618
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12420689A Pending JPH02304928A (en) | 1989-05-19 | 1989-05-19 | Forming method of wiring |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02304928A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06326052A (en) * | 1993-05-14 | 1994-11-25 | Nec Corp | Thin film formation |
GB2338594A (en) * | 1998-06-16 | 1999-12-22 | Samsung Electronics Co Ltd | A method of forming a selective metal layer |
US6372598B2 (en) | 1998-06-16 | 2002-04-16 | Samsung Electronics Co., Ltd. | Method of forming selective metal layer and method of forming capacitor and filling contact hole using the same |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6421942A (en) * | 1987-07-17 | 1989-01-25 | Hitachi Ltd | Manufacture of semiconductor device |
-
1989
- 1989-05-19 JP JP12420689A patent/JPH02304928A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6421942A (en) * | 1987-07-17 | 1989-01-25 | Hitachi Ltd | Manufacture of semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06326052A (en) * | 1993-05-14 | 1994-11-25 | Nec Corp | Thin film formation |
GB2338594A (en) * | 1998-06-16 | 1999-12-22 | Samsung Electronics Co Ltd | A method of forming a selective metal layer |
US6372598B2 (en) | 1998-06-16 | 2002-04-16 | Samsung Electronics Co., Ltd. | Method of forming selective metal layer and method of forming capacitor and filling contact hole using the same |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH0458688B2 (en) | ||
JPS61203636A (en) | Formation of heatproof metal silicide layer | |
US5756392A (en) | Method of formation of polycide in a semiconductor IC device | |
KR100456315B1 (en) | Gate electrode formation method of semiconductor device | |
JPH02304928A (en) | Forming method of wiring | |
JP4955848B2 (en) | Substrate manufacturing method for electronic device | |
JPH07114203B2 (en) | Method for manufacturing semiconductor device | |
JPS587864A (en) | Semicondutor device and manufacture thereof | |
US5946599A (en) | Method of manufacturing a semiconductor IC device | |
KR950007671B1 (en) | Method for evaporation a thin film of tungsten | |
JP2946543B2 (en) | Method for manufacturing semiconductor device | |
KR100317338B1 (en) | Method for manufacturing of semiconductor device | |
JPH07107933B2 (en) | Method of forming polycide pattern | |
KR100431306B1 (en) | Method for formig gate of semiconductor device using gate oxide made of double film of aluminium oxide and yttrium oxynitride | |
KR100293819B1 (en) | Manufacturing method of semiconductor device | |
JPH10125676A (en) | Production of aluminum wiring | |
KR100447979B1 (en) | Method for forming gate of semiconductor device | |
KR100332134B1 (en) | Method for forming gate electrode in semiconductor device | |
KR20040059918A (en) | Method of forming interconnection line for semiconductor device | |
JP2639672B2 (en) | Method for manufacturing semiconductor device having carbon film formed thereon | |
JPH09293722A (en) | Manufacture of semiconductor device | |
JPH0669498A (en) | Semiconductor device and its manufacture | |
JPS6138264B2 (en) | ||
JPH0529346A (en) | Manufacture of semiconductor device | |
JPH02250354A (en) | Manufacture of semiconductor device |