DE19848444A1 - Method of forming a selective metal layer to fill contact hole in manufacture of semiconductor capacitor - Google Patents

Abstract

A method of forming selective metal layer comprises: (1) forming insulating film and conductive layer on semiconductor substrate in chamber and purging with gas; (2) forming sacrificial metal layer on the conductive layer using metal source gas; (3) replacing sacrificial metal layer with deposition metal layer using metal halide gas. A metal layer can be selectively formed at a temperature <= 500 deg C.

Description

The invention relates to a method of manufacture a selective metal layer and using it Capacitor manufacturing and filling method a contact hole. Such methods are part of the Manufacture of semiconductor devices

With a higher degree of integration and greater complexity of Semiconductor devices is common during the manufacture of the Semiconductor devices selectively a metal layer to build. So in a process for producing a Kon capacitor of a semiconductor component has a lower electrode often formed from a metal instead of polysilicon maintain a high capacity, making a metal Insulator Silicon (MIS) - or Metal Insulator Metal (MIM) - Structure is achieved. Another example is education an ohmic layer at the bottom of a small contact hole with a high aspect ratio within a process for filling the contact hole. In these two processes mentioned there are numerous difficulties.  

In the manufacturing process for the capacitor with the metallic lower electrode's, it is very difficult to selectively deposit a metal layer without structuring the metal layer on a lower polysilicon electrode with hemispherical grains (HSG). No technology is currently known for this. In addition, in order to be able to use PZT, ie Pb (Zr, Ti) O ₃ , or BST, ie BaSrTiO ₃ , which have a perovskite structure for a highly dielectric film of a capacitor, platinum is preferred instead of an existing polysilicon electrode To use (Pt), which is not oxidized and has excellent leakage current properties when it comes to the deposition of a dielectric film. However, if a metal layer such as a platinum film is deposited by an opaque process and not a selective process, the etching is difficult. Namely, when the platinum film formed by the opaque process is dry etched using chlorine gas (Cl ₂ ) as an etchant, PtClx is formed as a by-product of the etching, which is a non-volatile, conductive polymer. Therefore, a process for removing the PtClx by wet etching must also be carried out. In the wet etching process, since a part of a lower platinum electrode is also etched, it is difficult to perform a repeatable process in a manufacturing method for a random access memory (DRAM) which requires fine patterning.

In the case of the ohmic layer, this is on the bottom of the Contact hole by applying a highly conductive metal with a high melting point, such as titanium, by means of plasma support chemical vapor deposition (PECVD) or sputtering posed. However, when making the ohmic layer sputtering, the step coverage is low. On the other hand the PECVD method is not good for use in a sol Chen actual process suitable because the leakage current through a high deposition temperature of 600 ° or more rises  and therefore the electrical properties of the semiconductor component can deteriorate.

In addition, if the ohmic layer, such as. B. a titanium (Ti) layer, formed by sputtering and a Barrie layer, e.g. B. a titanium nitride (TiN) layer on the ohm layer by chemical vapor deposition (CVD) is brought, the ohmic layer corrode, and the Boundary layer between the ohmic layer and the barriers layer can peel off. If the barrier layer is made of TiN on an ohmic layer of titanium (Ti) by means of sputtering is applied, the boundary layer between the ohmic layer and the barrier layer. However The peeling problem occurs when a terminal contact layer for contact filling in a subsequent process under Ver tungsten using CVD.

There is therefore a need for a selective method Production of a metal layer at a temperature of 500 ° C or less, at which the electrical properties of the semiconductor device are not deteriorated. Ge However, at present it is very difficult to use such a technique in the process of forming the lower electrode of the condenser tors and in the formation of the ohmic layer of contact to realize lochs.

The invention is the technical problem of providing development of a method for producing a selective measurement layer that does not require temperatures above 500 ° C, causes no special manufacturing process difficulties and no deterioration in electrical properties of the semiconductor component in question, and of method using this method for producing a Capacitor and for filling a contact hole.

The invention solves this problem by providing it a method of making a selective metal  layer with the features of claim 1, one of these ver using the method for producing a capacitor the features of claim 8 as well as one that he process using a process for filling a Contact hole with the features of claim 15.

According to claim 1, a sacrificial metal layer is selectively applied to a previously formed conductive layer, which can be done at temperatures of 500 ° C or less. For this purpose, the relevant semiconductor substrate, on which an insulation film and the conductive layer have been formed, is introduced into the reaction chamber and a purge gas is introduced into the same. Then a sacrificial metal source gas is introduced into the reaction chamber, which in particular may be dimethylaluminium hydride (DMAH), ie (CH ₃ ) ₂ AlH, or dimethylethylaminalane (DMEAA), ie (CH ₃ ) ₂ C ₂ H ₅ N: AlH ₃ . The sacrificial metal layer is then replaced with a deposition metal layer by supplying a metal halide gas to the chamber with a lower halogen binding force than that of the metal atoms in the sacrificial metal layer.

In a further development of the invention, the purge gas becomes continuous Lich fed, or it is first in a predetermined Amount for flushing and after formation of the sacrificial metal layer and their replacement by the deposition metal layer peri supplied odically in predetermined quantities. It is preferred that the supply time and the amount of purge gas to be supplied after replacement of the sacrificial metal layer by the deposition metal layer is larger than in other steps.

The metal of the deposition metal layer is preferably selected from the group consisting of titanium, tantalum, zirconium, haf nium, cobalt, molybdenum, tungsten, nickel and platinum. Preferably, when the deposition metal is titanium, TiCi _{4 is used} as the metal halide compound gas. It is also preferred that, as the metal halide compound gas when the deposition metal is platinum, a gas is used which is obtained by dissolving platinum chloride (Cl ₆ H ₆ Pt) or PtCl ₂ in water (H ₂ O) or alcohol and evaporating the Cl ₆ H ₆ Pt or PtCl _{2 is} obtained.

The capacitor manufacturing method according to claim 8 provides for the formation of a contact hole which exposes a source region of a semiconductor substrate, wherein an insulating film, for. B. a silicon oxide film (SiO ₂ ) or a complex film containing an oxide film of the semiconductor substrate is formed and the insulation film is structured. A conductive layer of impurity doped polysilicon or a metal is then formed to fill the via and cover the insulation film. A conductive layer pattern connected to the contact hole is produced by structuring or chemically mechanical polishing of the conductive layer. The semiconductor substrate is introduced into a chamber into which a purge gas in the form of a mixture of hydrogen (H ₂ ) and silane (SiH ₄ ) is introduced. A sacrificial metal layer is only formed on the conductive layer by supplying a sacrificial metal source gas to the chamber that selectively deposits with respect to the insulation film and the conductive layer. The sacrificial metal source gas here is dimethyl aluminum hydride (DMAH), ie (CH ₃ ) ₂ AlH, or dimethyl ethyl aminalane (DMEAA), ie (CH ₃ ) ₂ C ₂ H ₅ N: AlH ₃ . Then, the sacrificial metal layer is replaced by a deposition metal layer by supplying a metal halide gas with a halogen binding force smaller than that of the metal atoms in the sacrificial metal layer to the chamber. Then, a dielectric film is formed on the deposition metal layer, and an upper electrode is formed on the dielectric film.

In further development of this method, after generation of the conductive layer pattern is a step to formation half spherical grains on the surface of the conductive Layer pattern may be provided.  

A purge gas is preferably used continuously or for the purpose of purging first in a predetermined amount and after formation of the Sacrificial metal layer and replacement by the deposition metal layer supplied periodically in predetermined quantities. Here it is useful if the purge gas after replacing the Op fermetallschicht through the deposition metal layer longer and is supplied in a larger amount than in other steps ten.

In a further embodiment of this method, according to Step of forming the deposition metal layer one step provided for siliciding the deposition metal layer be.

In the method for filling a contact hole according to claim 15, the following measures are provided in particular. An insulating film such as a silicon oxide film (SiO ₂ ) or a complex film containing an oxide film is applied to the semiconductor substrate. Then, by patterning the insulation film, a contact hole is created that exposes a bottom film of impurity-doped polysilicon film or a metal such as TiN. The semiconductor substrate provided with the contact hole is introduced into a reaction chamber, and a purge gas is introduced into the chamber, e.g. B. a mixture of hydrogen (H ₂ ) and silane (SiH ₄ ). By introducing a sacrificial metal source gas into the chamber, which separates selectively with respect to the insulation film and the lower film, a sacrificial metal layer, e.g. B. made of aluminum (Al), only on the lower film. The sacrificial tall gas source is z. B. dimethyl aluminum hydride (DMAH), ie (CH ₃ ) ₂ AlH, or dimethylethyl aminalane (DMEAA), ie (CH ₃ ) ₂ C ₂ H ₅ N: AlH ₃ . Then, the sacrificial metal layer is replaced by supplying a metal halide gas into the chamber with a lower halogen binding force than that of the metal atoms in the sacrificial metal layer by a deposition metal layer. Finally, a conductive layer filling the contact hole is applied.

A continuous feed is again preferred tion of the purge gas or a first supply of the same in egg ner predetermined amount and then a periodic supply in predetermined amounts after formation of the sacrificial metal layer and Replacement of the same with the deposition metal layer hen. Appropriately after replacing the Op fermetallschicht through the deposition metal layer longer feed time and a larger amount of purge gas chosen than in other procedural steps.

This method preferably further includes one Step to form a barrier layer, e.g. B. one TiN layer, on the deposition metal layer after the step the replacement of the sacrificial metal layer by the deposition metal layer.

According to the invention is thus in a manufacturing process of semiconductor devices selectively select a specific metal applied at a temperature of 500 ° C or less, and this procedure can be used when forming a lower elec trode of a capacitor can be used so that a metal Lische lower capacitor electrode without serious process difficulties can be generated. In addition, the Vorge can be used for this purpose, an ohmic layer on the Bo to generate the area of a contact hole, which is a ver deterioration in the properties of the contact or detachment Prevent thin film due to corrosion can while improving the step coverage is.

Advantageous embodiments of the invention are in the Drawings are shown and are described below. Here show:

Fig. 1 is a flowchart of a method for producing egg ner selective metal layer,

Figs. 2A and 2B gas flow timing diagrams for the Ver drive to Fig. 1,

Fig. 3 is a flowchart showing a procedural proceedings for capacitor production using the method according to claim 1,

FIGS. 4A-4F are cross sectional views of successive stages of manufacture for illustrating a first implementation of the capacitor manufacturing method according to Fig. 3,

Fig. 5A to 5F are cross-sectional views of successive stages of manufacture to illustrate a second implementation of the capacitor manufacturing method according to Fig. 3,

FIGS. 6A to 6C are cross sectional views of successive stages of manufacture for illustrating a third implementation of the capacitor manufacturing method according to Fig. 31

Fig. 7 is a flow chart illustrating a method for filling a via hole using the method of FIGS . 1 and

FIGS. 8A to 8E are cross sectional views showing successive manufacturing steps of the procedure according to Fig. 7.

According to the procedure illustrated in FIG. 1, in a first step 100, a semiconductor substrate, on which an insulation film and a conductive layer are formed, is introduced into a reaction chamber of a device for semiconductor component production. The insulation film here is an oxide film made of SiO ₂ , which does not absorb any metal which is deposited to form a selective metal layer, or a complex film made of the oxide film. The conductive layer is formed from a metal such as titanium nitride (TiN) or from impurity-doped polysilicon with terminal hydrogen radicals on which aluminum (Al) can be easily and selectively deposited. In a next step 110 , a purge gas containing hydrogen (H ₂ ) and silane (SiH ₄ ) is introduced into the chamber to purge the interior of the chamber. The purge gas can be supplied by the following two techniques. In the first technique, the purge gas is supplied continuously from the beginning in a predetermined amount, ie with a predetermined flow. According to a second technique, the purge gas is introduced into the chamber after purging a sacrificial metal source gas or a metal halide gas to purge the chamber, and after depositing a sacrificial metal and replacing the sacrificial metal layer with a deposition metal layer, a predetermined amount may be given periodically be supplied to purge gas.

In a subsequent step 120 , dimethylaluminum hydride (DMAH), ie (CH ₃ ) ₂ AlH, or dimethylethylaminalane (DMEAA), ie (CH ₃ ) ₂ C ₂ H ₅ N: AlH ₃ , is introduced onto the surface of the conductive layer. as a sacrificial metal source gas, an aluminum (Al) sacrificial metal layer is formed. The reason why the sacrificial metal layer is made of aluminum is that aluminum is an element from the halogen family, such as Cl, Br, F or I, and has the highest Gibbs free energy and that various precursors to aluminum already exist have been developed. Precursor for the deposition of aluminum include di-i-butyl aluminum hydride ((C ₄ H _{9) 2} AlH), tri-i-butylaluminum ((C ₄ H _{9) 3} Al), triethylaluminum ((C ₂ H _{5) 2} Al ), Trimethylaluminium ((CH ₃ ) ₃ Al), trimethylamine (AlH ₃ N (CH ₃ ) ₃ ), dimethylaluminum hydride ((CH ₃ ) ₂ AlH) and dimethylethylaminalane ((CH ₃ ) ₂ C ₂ H ₅ N: AlH ₃ ) . The dimethylaluminum hydride ((CH ₃ ) ₂ AlH), hereinafter referred to as DMAH, and the dimethylethylaminalane ((CH ₃ ) ₂ C ₂ H ₅ N: AlH ₃ ), hereinafter referred to as DMEAA, do not separate on an insulating film, such as the SiO ₂ -Oxide film, but selectively only on a metal such as TiN or silicon, which is doped with impurities with terminal oxygen radicals. This means that the DMAH and DMEAA in the reaction chamber do not deposit on the insulating film of the semiconductor substrate, but selectively only on the conductive layer.

In a next step 130 , a purge gas is introduced into the reaction chamber, in which the semiconductor substrate with the sacrificial metal layer selectively formed thereon is located in order to drive the sacrificial metal source gas out of the chamber.

Next, in a step 140, TiCl _{4 is changed} to AlCl _x , and the aluminum of the sacrificial metal layer is replaced with a titanium deposition metal layer by reacting the semiconductor substrate with TiCl ₄ , which is a metal halide gas containing a metal for deposition , is introduced into the chamber. The metal in the metal halide gas has a weaker halogen binding force than the metal atoms of the sacrificial metal layer, so that the metal atoms of the sacrificial metal layer react with the metal halide gas. More specifically, the Gibbs free energy of TiCl is ₄ 678.3 kJ / mol at 427 ° C, ie 700K, which is a higher value than for most metal halides, while the Gibbs free energy of AlCl _{6 is} 1121 , 9 kJ / mol and is therefore larger than that of TiCl ₄ , so that the metal atoms of the sacrificial metal layer react with the metal halide gas. The aluminum atoms of the sacrificial metal layer are therefore removed from the surface of the conductive layer and react with a chlorine gas with a higher binding force, ie AlCl _{x is formed} in a gaseous state. In addition, the titanium (Ti) obtained from the TiCl _{4 is} deposited in the free places where the aluminum atoms have been removed from the surface of the conductive layer. When the metal halide gas having a smaller Gibbs free energy, that is, binding force between a sacrificial metal and the halogen atom, is introduced into the chamber in which the semiconductor substrate with the sacrificial metal formed thereon is located, the metal layer can be selectively applied . The deposition metal layer formed as described above can use titanium, tantalum, zirconium, hafnium, cobalt, molybdenum, tungsten, nickel or platinum.

When the deposited metal is titanium, TiCl ₄ is used as the metal halide gas, and when the deposited metal is platinum, a gas is used as the metal halide gas by melting and evaporating platinum chloride (Cl ₆ H ₆ Pt) or PtCl ₂ in Water (H ₂ O) or alcohol is obtained. In addition, when the deposited metal is cobalt, either cobalt chloride CoCl ₂ , cobalt fluoride CoF ₂ or cobalt iodide CoI _{2 is used} as the metal halide gas. Since platinum chloride (Cl ₆ H ₆ Pt) or PtCl ₂ , which is a platinum-containing metal halide, is solid, it must be used here after melting in a solvent and evaporation. Since platinum is inert compared to other metals, it has a lower binding force with the halogen atom. Accordingly, it can be easily deposited when the platinum reacts with the sacrificial metal layer, such as aluminum.

When the deposited metal is molybdenum, the metal halide gas is either bis (cyclopentadienyl) molybdenum dichloride (C ₅ H ₅ ) ₂ Mocl ₂ , cyclopentadienylmolybdenum tetrachloride C ₅ H ₅ MoCl ₄ , molybdenum fluoride MoF ₆ , molybdenum chloride MoCl ₃ / MoCliod ₅ or Molybdenum ₂ used. When the deposited metal is nickel, the metal halide gas is either [(C ₆ H ₅ ) ₂ PCH ₂ CH ₂ CH ₂ P (C ₆ H ₅ ) ₂ ] NiCl ₂ , ie 1,2-bis (diphenylphosphine) propane nickel , [(C ₆ H ₅ ) ₅ C ₅ ] ₂ NiBr ₂ , ie bis (triphenylphosphine) - nickel bromide, [(C ₆ H ₅ ) ₃ P] ₂ NiCl ₂ , ie bis (triphenylphosphine) - nickel chloride, [Ni (NH ₃ ) ₆ ] Cl ₂ , ie hexaamine nickel chloride, [Ni (NH ₃ ) ₆ ] I ₂ , ie hexaamine iodide, NiBr / NiBr ₂ , ie nickel bromide, NiCl ₂ , ie nickel chloride, NiF ₂ , ie nickel fluoride, or NiI ₂ , ie Nickel iodide. If the deposited metal is tungsten, the bis (cyclopentadienyl) tungsten dichloride (C ₅ H ₅ ) ₂ WCl ₂ , wolf rambromide WB / W ₂ B / W ₂ B ₅ , tungsten chloride WCl ₄ / WCl ₆ or tungsten is used as the metal halide gas fluoride WF ₆ used.

Below are Tables 1 to 5 of Gibbs free energies of numerous metal halide gases with an Ab solute temperature of 700K, d. H. 427 ° C.

Table 1

Gibbs free energies of various gaseous, Cl-containing compounds at 427 ° C

Table 2

Gibbs free energies of some gaseous, iodine-containing compounds at 427 ° C

Table 3

Gibbs free energies of some gaseous, bromine-containing compounds at 427 ° C

Table 4

Gibbs free energies of some gaseous, fluorine-containing compounds at 427 ° C

Table 5

Gibbs free energies of some gaseous, platinum-containing compounds at 427 ° C

Finally, after the metal layer of titanium, tan tal, zirconium, hafnium, cobalt, molybdenum, tungsten, nickel or platinum has been formed by a replacement process using the metal halide gas, a purge gas is introduced into the chamber in a step 150 . Here, the supply time and the supply amount of purge gas are larger than in the step of forming the sacrificial metal layer and in other steps. As a result, the metal halide gas, such as TiCl _x , which has been adsorbed in an area such as the insulation film but not the sacrificial metal layer, is desorbed and expelled.

Figs. 2A and 2B show gas flow timing diagrams of the process for the selective formation of the metal layer, wherein the time is plotted on the ordinate of the Zuflußzustand a respective gas and on the abscissa. Fig. 2A shows graphically the gas flow when a mixed gas of hydrogen (H ₂ ) and silane (SiH ₄ ) is periodically supplied. Fig. 2B graphically shows the gas flow when the purge gas is continuously supplied from the beginning. As shown in Fig. 2A, when the purge gas is periodically introduced, immediately after supplying a metal halide gas, a purge gas 150 is supplied for a longer period of time and in a larger amount to prevent the metal halide gas from being absorbed in the insulation film, and so on sufficiently desorb the metal halide gas from the insulation film. In short, a purge gas 110 is first supplied, and then a sacrificial metal source gas 120 is introduced to form a sacrificial metal layer. When the purge gas is periodically supplied, a purge gas 130 is introduced into the chamber to purge the remaining sacrificial metal source gas. In addition, a metal halide gas containing a metal to be deposited is supplied to replace the sacrificial metal layer with a deposition metal layer. At this time, a composite gas made of aluminum as a sacrificial metal and halogen atoms remains in the chamber, and this in turn is purged out of the chamber by introducing the purge gas 150 into the chamber. This process is given as a cycle, and if this cycle is repeated, the thickness of a deposited metal can be easily controlled and the step coverage problems can be solved.

Method of manufacturing a capacitor of a semi-lead terbauelementes using selective metal stratification process

Fig. 3 shows a flow chart illustrating a method for the manufacture lung of a capacitor using the selective Me tallschichtbildungsprozesses. Referring to Fig. 3, a lower structure such as a transistor is first formed, and then an insulating film as an interlayer dielectric (ILD) is applied using an oxide film or a complex film made of the oxide film. In a step 300 , a contact hole is then produced by performing a photolithography process on the insulation film, which exposes a source region of a transistor. Optionally, an ohmic layer and a barrier layer can be formed in a step 310 using a material such as titanium (Ti) or titanium nitride (TiN) in order to improve the conductivity between the contact hole and a filler material and to prevent diffusion. Then, a conductive layer covering the surface of the insulation film is applied while filling the contact hole, for which purpose a conductive material for a lower electrode, e.g. B. a metal material such as TiN or impurity-doped polysilicon is used. It is preferred before that the impurities doped in the polysilicon end have permanent hydrogen radicals in order to enable a sacrificial metal layer to be applied selectively in a subsequent process. In a next step 320 , a conductive layer pattern for use as the lower electrode connected to the contact hole is generated by structuring the conductive layer. The conductive layer pattern can be generated after the formation of a connection contact layer, with which only the inside of the contact hole is filled, or at the same time with the deposition and structuring of a conductive layer for filling the inside of the contact hole. Optionally, a step 330 can be performed in which hemispherical grains (HSG) can be formed on the conductive layer pattern to increase the surface area of the lower electrode. Then, in a step 340, the semiconductor substrate provided with the HSG is introduced into a reaction chamber of a system for semiconductor component production, and a purge gas is introduced continuously or periodically, as shown in FIGS . 2A and 2B. DMAH, ie (CH ₃ ) ₂ AlH, or DMEAA, ie (CH ₃ ) ₂ C ₂ H ₅ N: AlH ₃ , is introduced into the chamber as a sacrificial metal source gas. Then, in a step 350, a sacrificial metal layer in the form of an aluminum layer is selectively formed only on the conductive layer. In a step 360 , a metal halide gas containing a metal to be deposited, e.g. B. TiCl ₄ , platinum chloride (Cl ₆ H ₆ Pt) or PtCl ₂ , melted in water (H ₂ O) or alcohol and then evaporated, and the steam is supplied to a deposition measurement consisting of Ti or Pt using a replacement technique to generate tall layer. Then, in step 365, a silicide layer can optionally be formed by performing a thermal treatment of the deposition metal layer. In step 370 , a nitride film can optionally be applied using an ammonia plasma or rapid thermal nitriding (RTN). In a step 375 , an oxide film can optionally be formed by performing a thermal treatment in an oxygen atmosphere. The nitride film and the oxide film can then be used as a dielectric film for a capacitor.

Here, if Ti is used as the first deposition metal layer, TiN is formed as the nitride film, and the selective metal layer formation process shown in FIG. 1 is repeated in a step 373 to form a second deposition metal layer of platinum, the step 373 op is tional.

Then, in a step 380, a dielectric film is deposited on the resulting structure. The dielectric film may be a complex film of an oxide film and a nitride film, or it may be a monoatomic metal oxide selected from the group consisting of Ta ₂ O ₅ , TiO ₂ , ZrO ₂ , Al ₂ O ₃ and Nb ₂ O ₅ is a monoatomic metal nitride such as AlN, or a polyatomic metal oxide selected from the group consisting of SrTiO ₃ , PZT, ie Pb (Zr, Ti) O ₃ , and BST, ie BaSrTiO ₃ . Finally, an upper electrode is formed on the semiconductor substrate on which the dielectric film is formed using polysilicon or a metal such as TiN, TiAlN or TiSiN in a step 390 .

First embodiment

FIGS. 4A-4F illustrate, in respective cross-sectional views, a first example of a position Kondensatorher method using a selective metal layer formation process.

Referring to FIG. 4A, a bottom structure, not shown, such as a transistor, is first formed on a semiconductor substrate 400 , after which an oxide film or a complex film of such an oxide film is applied as an interlayer dielectric (ILD) 402 to the resulting structure. By structuring the ILD 402 , a contact hole 404 is created that exposes a source region of the transistor. Polysilicon containing terminal hydrogen radicals is deposited on the semiconductor substrate in which the contact hole 404 has been formed, and the deposited polysilicon is patterned so that a conductive layer pattern 406 of a lower electrode connected to the contact hole is formed.

Referring to FIG. 4B, a deposition metal layer 408 , e.g., is then deposited on the resulting structure using the selective metal layer deposition method of FIG . B. made of Ti or Pt. Here, optionally, a process for forming HSG on the conductive layer pattern 406 may be performed before the deposition metal layer is formed to increase the surface area of the lower electrode of the capacitor. Thus, according to the invention, a metal can be deposited on the HSG surface without structuring a lower electrode, such as one of the HSG type, thanks to the selective metal layer deposition.

Referring to Figure 4C. Tersubstrat then on the semiconducting on which the deposited metal layer was det gebil 408 formed by nitriding or RTN using ammonia plasma (NH ₃ plasma), a nitride film 410th The nitride film 410 prevents capacitance-reducing oxidation that may otherwise occur at the interface between the lower electrode and a dielectric film when the dielectric film is deposited in a subsequent process.

Referring to Fig. 4D, by performing thermal treatment in an oxygen atmosphere, an oxide film 412 , e.g. B. made of titanium oxide (TiO ₂ ). The nitride film 410 and the oxide film 412 can be used as the dielectric film.

Referring to FIG. 4E, a dielectric film 414 is formed on the resulting structure, with a monoatomic metal oxide selected from the group consisting of Ta ₂ O ₅ , TiO ₂ , ZrO ₂ , Al ₂ O _3, and Nb ₂ O ₅ is a monoatomic metal nitride such as AlN, or a polyatomic metal oxide selected from the group consisting of SrTiO ₃ , PZT, ie Pb (Zr, Ti) O ₃ , and BST, ie BaSrTiO ₃ .

Referring to FIG. 4F, an upper electrode 416 made of polysilicon or a metal is applied to the semiconductor substrate on which the dielectric film 414 has been formed, so as to capacitor a semiconductor device with a silicon insulator metal (SIM) or a metal -Isolator- to produce metal (MIM) structure.

If the capacitor of the semiconductor device as above be a photolithography process can ent fall because no structure after the formation of the lower electrode ration is required. In particular, is not a structure a lower electrode with HSG is required so that the lower electrode is formed from a metal can, while many, problems caused by etching be solved.

Second embodiment

FIGS. 5A-5F illustrate, in respective cross-sections, a second example of a capacitor manufacturing method using a selective metal layer formation process. The processes illustrated in FIGS . 5A and 5B correspond to those of the first example, so that the above explanations can be referred to for their description. The elements that are identified by a reference number that is one hundred times higher than in FIGS. 4A to 4F are functionally identical elements.

Referring to Fig. 5C ei ne-deposited metal layer 508, which tallschicht selective Me is at this stage of manufacture is, by performing a Silicidie tion on the semiconductor substrate on which the Abscheidungsme tallschicht was formed 508, changed into a silicide layer 510, such as TiSi _x.

Referring to Fig. 5D using a NH ₃ -Plasmas or by performing an RTN Ni is formed on the semiconductor substrate on which the silicide layer 510 was formed, tridfilm generated 512th

Referring to Fig. 5E, a dielectric film 514 may be on the semiconductor substrate on which the nitride film 510 has been formed, are produced. The dielectric film 514 may be a complex film of an oxide film and a nitride film, or it may be a monoatomic metal oxide selected from the group consisting of Ta ₂ O ₅ , TiO ₂ , ZrO ₂ , Al ₂ O ₃ and Nb ₂ O ₅ , a monoatomic metal nitride such as AlN, or a polyatomic metal oxide selected from the group consisting of SrTiO ₃ , PZT, ie Pb (Zr, Ti) O ₃ , and BST, ie BaSrTiO ₃ , are formed.

Referring to FIG. 5F, an upper electrode 516 made of polysilicon or a metal is formed on the semiconductor substrate on which the dielectric film was formed, where the capacitor having a SIM or MIM structure is formed.

Third embodiment

FIGS. 6A to 6C illustrate in respective cross-sectional views of a method for producing a condensate crystallizer using a selective Metallschichtbil decision procedure according to a third example.

In this example, the selective metal layer deposition process can be used twice to prevent the formation of a high resistance platinum silicide (PtSi _x ) when a platinum film is selectively deposited on a lower capacitor electrode.

Referring to FIG. 6A, a bottom structure, not shown, such as a transistor, is first formed on a semiconductor substrate 600 , after which an interlayer dielectric (ILD) 602 is formed on the resulting structure using an oxide film or a complex film made of the oxide film. A contact hole is then produced on the semiconductor substrate 600 and exposes a source region of the transistor. A contact layer 604 is formed using polysilicon to fill the via. By means of chemical vapor deposition (CVD) or physical vapor deposition, titanium nitride (TiN) is covered as a conductive layer connected to the connection contact layer 604 for a lower capacitor electrode. The conductive layer for the lower capacitor electrode is structured to form a conductive layer pattern 606 for the lower capacitor electrode. Then, using the selective metal film forming method shown in FIG. 1, a platinum film 608 is formed on the surface of the conductive TiN film pattern 606 .

The conductive film pattern 606 for the lower capacitor electrode covered with the platinum film 608 can also be produced by the following modified method. After the contact hole exposing the source region of the transistor has been produced, the connection contact layer 604 for filling the contact hole is formed from polysilicon which is doped with impurities and has terminal hydrogen radicals. By the selective metal film forming method of Fig. 1 titanium is deposited on the surface of the exposed terminal contact layer 604 then selectively arises whereby a leitfä Higes film pattern 606 for the lower electrode planar type. The conductive Ti film pattern 606 then undergoes nitriding using an NH ₃ plasma or rapid thermal nitriding (RTN) to form TiN on the resulting structure. The platinum film 608 is then applied by the selective metal layer formation method from FIG. 1, as a result of which the lower capacitor electrode consisting of the platinum film is formed.

Referring to Fig. 6B on the platinum film 608, a di electric film 610 is deposited. The dielectric film 610 may be a complex film of an oxide film and a nitride film, or it may be made of a monoatomic metal oxide selected from the group consisting of Ta ₂ O ₅ , TiO ₂ , ZrO ₂ , Al ₂ O ₃ and Nb ₂ O ₅ , a monoatomic metal nitride such as AlN, or a polyatomic metal oxide selected from the group consisting of SrTiO ₃ , PZT, ie Pb (Zr, Ti) O ₃ , and BST, ie BaSrTiO ₃ , exists.

Referring to FIG. 6C, an upper capacitor electrode 612 is applied to the semiconductor substrate on which the dielectric film 610 was formed using polysilicon or a metal such as platinum, which enables the capacitor of the semiconductor device to be fabricated using the selective metal layering method completed according to the third embodiment.

Via filling method using the selective Metal layer manufacturing process

FIG. 7 is a flow diagram illustrating a via filling method that uses the selective metal layer forming process of the present invention.

Referring to FIG. 7, a Isola, in a step 700 tion film deposited on a semiconductor substrate on which a lower structure such as a transistor bit-line, was det gebil, wherein an interlayer dielectric (ILD) and a contact hole are used, the lower film exposed and generated by structuring the ILD. Here, the ILD is an oxide film or a complex film made of the oxide film, and the lower film is made of TiN or polysilicon with terminal hydrogen, which is endangered by a defect. This serves to enable the selective deposition of a sacrificial metal on the lower film from a sacrificial metal source gas in a subsequent process. Furthermore, the contact hole can be a contact hole, which is connected directly to the semiconductor substrate, for a lower capacitor electrode or a metal contact hole. Next, in successive steps 710 , 720 and 730 , using the selective metal layer formation method of FIG. 1, a deposition metal layer made of a material such as titanium (Ti) is created at the bottom of the via. The deposition metal layer formed of a conductive material such as titanium (Ti) is used as an ohmic layer in a contact hole filling process. Then, a barrier layer, such as titanium nitride (TiN), is formed on the ohmic layer, which is the deposition metal layer, by RTN or by nitriding using an NH ₃ plasma, optionally in its step 740 . In a step 750 , a connection contact layer made of aluminum (Al) and tungsten (W) is formed on the barrier layer. In a step 760 , a conductive layer connected to the connection contact layer is formed, which completes the filling of the contact hole. Thus, a conductive layer for filling a contact hole can be produced directly on the barrier layer or the ohmic layer without special formation of the connection contact layer.

In step 740 , the barrier layer can be applied and then structured instead of by RTN or by nitriding using an NH ₃ plasma using a covering method such as CVD or sputtering.

Fourth embodiment

FIGS. 8A to 8E illustrate in cross-sectional views corresponding manufacturing steps of an example of the Ver drive to the contact-hole filling by using a metal layer formation process selekti ven.

Referring. To Figure 8A is applied to a semiconductor substrate 800, an insulating film 802 z. B. an oxide film or a complex film from the oxide film is formed, and by structuring the insulation film 802 , a contact hole 804 is produced which exposes a lower film. Contact hole 804 may be a contact hole connected to the semiconductor substrate for a lower capacitor electrode or a metal contact hole produced in a metal interconnection process.

Referring to FIG. 8B, a deposition metal layer made of a material such as titanium (Ti) is formed on the semiconductor substrate on which the via 804 was formed using the selective metal layering method of FIG. 1. The deposition metal layer serves as an ohmic layer 806 in the via filling process to improve the conductivity between the lower film and a conductive material to fill the via.

Referring to FIG. 8C, a barrier layer 808 is optionally formed on the semiconductor substrate on which the ohmic layer 806 has been deposited, e.g. B. a layer of Ti tannitride (TiN) to prevent impurity diffusion. The barrier layer can be generated by nitriding using an NH ₃ plasma, by RTN or by covering it.

Referring to FIG. 8D, a conductive layer 810 is deposited on the semiconductor substrate on which the barrier layer 808 has been formed to cover the surface of the semiconductor substrate while the contact hole is being filled, thereby the contact hole filling process using the selective metal layer formation method according to these four th embodiment is completed.

FIG. 8E shows a modification of FIG. 8D in a cross section. Here, a terminal contact layer 812 made of tungsten (W) or aluminum (Al) is formed on the semiconductor substrate on which the barrier layer 808 was formed. Next, the contact layer 812 is removed by etching back or chemical mechanical polishing (CMP) except in the interior of the contact hole. The conductive layer 810 is then formed so that it is in contact with the contact layer 812 .

According to the invention, a relatively thin ohmic layer can thus within a contact hole with high aspect ratio without Problems with peeling or corrosion at a temperature temperature of 500 ° C or less. This makes egg NEN process for controlling the thickness of the ohmic layer, such as an etching back process, superfluous.

According to the Er explained above with corresponding examples Invention can easily be a lower electrode from egg metal instead of polysilicon within one process for producing a capacitor of a semiconductor device tes are formed because the metal layer is made of one material such as titanium (Ti) or platinum (Pt) selectively at a temperature of 500 ° C or less can be generated. This allows many difficulties caused by the known techniques ten when forming the lower electrode from titanium or plat tin be solved. In addition, in the process of manufacturing an ohmic layer at the bottom of a contact hole ohmic layer with a suitable thickness selectively at low temperature only formed at the bottom of the contact hole where through the contact hole while avoiding defects such as Ab loosen or corrosion, is filled.

Claims (20)

1. A method for producing a selective metal layer, characterized by the following steps:

• Introducing a semiconductor substrate ( 400 ) on which an insulation film ( 402 ) and a conductive layer ( 406 ) are formed into a reaction chamber and introducing a purge gas into the chamber,
• Forming a sacrificial metal layer only on the conductive layer ( 406 ) by injecting a sacrificial metal source gas into the chamber that selectively deposits with respect to the insulation film and the conductive layer, and
• - Replacing the sacrificial metal layer by a Abscheidungsme tallschicht ( 408 ) by introducing a metal halide gas into the chamber with a lower than that of the metal atoms in the sacrificial metal layer lower halogen binding strength.

2. A selective metal layer manufacturing method according to claim 1, further characterized in that the insulating film ( 402 ) is an oxide film (SiO ₂ ) or a complex film with an oxide film. 3. Selective metal layer manufacturing process according to Claim 1 or 2, further characterized in that the conductive layer of impurity-doped silicon or Me tall is formed. 4. Selective metal layer manufacturing process according to Claim 3 further characterized in that the sturgeon end-doped silicon has terminal hydrogen radicals points.   5. Selective metal layer manufacturing process according to Claim 3 further characterized in that the metal is TiN is. 6. Selective metal layer manufacturing process according to one of claims 1 to 5, further characterized in that that the purge gas from a mixture of hydrogen and silane consists. 7. Selective metal layer manufacturing process according to one of claims 1 to 6, further characterized in that that the purge gas is supplied continuously or first in a predetermined amount for rinsing and after formation of the Sacrificial metal layer and replacement by the deposition metal layer is periodically supplied in predetermined quantities. 8. A method for producing a capacitor of a semiconductor component using a selective metal layer production method, in particular a method according to one of claims 1 to 7, characterized by the following steps:

• a) forming a contact hole ( 404 ), which exposes a source region of a semiconductor substrate, by forming an insulation film ( 402 ) on the semiconductor substrate and structuring the insulation film,
• b) forming a conductive layer filling the contact hole and covering the insulation film,
• c) forming a conductive layer pattern ( 406 ) connected to the contact hole by processing the conductive layer,
• d) introducing the semiconductor substrate into a reaction chamber and introducing a purge gas into the chamber,
• e) forming a sacrificial metal layer only on the conductive layer by introducing a sacrificial metal source gas into the chamber that selectively deposits with respect to the insulation film and the conductive layer,
• f) replacing the sacrificial metal layer with a deposition metal layer ( 408 ) by introducing a metal halide gas into the chamber with a lower halogen binding strength than that of the metal atoms in the sacrificial metal layer,
• g) forming a dielectric film ( 414 ) on the deposition metal layer and
• h) forming an upper electrode ( 416 ) on the dielectric film.

9. The capacitor manufacturing method according to claim 8, further characterized in that the insulation film is an oxide film (SiO ₂ ) or a complex film with an oxide film. 10. A capacitor manufacturing method according to claim 8 or 9, further characterized in that the conductive layer ( 406 ) is formed in step b from impurity-doped polysilicon or from titanium nitride (TiN). 11. capacitor manufacturing method according to claim 10, further characterized in that the impurity doped Polysilicon has terminal hydrogen radicals. 12. Capacitor manufacturing method according to one of claims 8 to 11, further characterized in that the purge gas in step d is a mixture of hydrogen (H ₂ ) and silane (SiH ₄ ). 13. Capacitor manufacturing process according to one of the An sayings 8 to 12, further characterized in that the Purge gas continuously supplied in step d or first in a predetermined amount for rinsing and after forming the Sacrificial metal layer and replacement of the same with the Abschei metal layer periodically added in predetermined amounts leads.   14. Capacitor manufacturing process according to one of the An sayings 8 to 13, further characterized by a step the silicidation of the deposition metal layer after the Step f of forming the deposition metal layer. 15. A method for filling a contact hole using a selective metal layer production method, in particular a method according to one of claims 1 to 7, characterized by the following steps:

• 1) forming an insulation film ( 802 ) on a semiconductor substrate ( 800 ) and producing a contact hole ( 804 ) exposing a lower film by structuring the insulation film,
• 2) introducing the semiconductor substrate on which the contact hole was formed into a reaction chamber and introducing a purge gas into the chamber,
• 3) forming a sacrificial metal layer only on the lower film by introducing into the chamber a sacrificial metal source gas that selectively separates with respect to the insulation film and the lower film,
• 4) Replacing the sacrificial metal layer with a deposition metal layer ( 806 ) by introducing a metal halide gas into the chamber with a lower halogen bond strength than that of the metal atoms in the sacrificial metal layer and
• 5) forming a conductive layer ( 810 ) filling the via hole

16. via filling method according to claim 15, further characterized in that the insulating film in step 1 is an oxide film (SiO ₂ ) or a complex film with an oxide film. 17. contact hole filling method according to claim 15 or 16, further characterized in that the lower film in Step 1 from impurity-doped silicon, the terminal  Has hydrogen radicals, or of titanium nitride (TiN) ge forms is. 18. Contact hole filling method according to one of claims 15 to 17, further characterized in that the purge gas in step 2 is a mixture of hydrogen (H ₂ ) and silane (SiH ₄ ). 19. Contact hole filling method according to one of claims 15 to 18, further characterized in that the purge gas in Step 2 fed continuously or first in a pre given amount for rinsing and after making sacrifices tallschicht and replacing them with the Abscheidungsme tallschicht is periodically supplied in predetermined amounts. 20. Contact hole filling method according to one of claims 15 to 19, further characterized by a step of forming a barrier layer ( 808 ) on the deposition metal layer ( 806 ) after step 4 of replacing the sacrificial metal layer by the deposition metal layer.