TW403991B - Method of forming selective metal layer and method of forming capacitor and filling contact hole using the same - Google Patents

Method of forming selective metal layer and method of forming capacitor and filling contact hole using the same Download PDF

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Publication number
TW403991B
TW403991B TW87116247A TW87116247A TW403991B TW 403991 B TW403991 B TW 403991B TW 87116247 A TW87116247 A TW 87116247A TW 87116247 A TW87116247 A TW 87116247A TW 403991 B TW403991 B TW 403991B
Authority
TW
Taiwan
Prior art keywords
metal layer
forming
contact hole
sacrificial
layer
Prior art date
Application number
TW87116247A
Other languages
Chinese (zh)
Inventor
Sang-Bom Kang
Yun-Sook Chae
Sang-In Lee
Hyun-Seok Lim
Mee-Young Yoon
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of TW403991B publication Critical patent/TW403991B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C23C16/0272—Deposition of sub-layers, e.g. to promote the adhesion of the main coating
    • C23C16/0281—Deposition of sub-layers, e.g. to promote the adhesion of the main coating of metallic sub-layers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/08—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
    • C23C16/14—Deposition of only one other metal element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

A selective metal layer formation method, a capacitor formation method using the same, and a method of forming an ohmic layer on a contact hole and filling the contact hole using the same, are provided. A sacrificial metal layer is selectively deposited on a conductive layer by supplying a sacrificial metal source gas which deposits selectively on a semiconductor substrate having an insulating film and the conductive layer. Sacrificial metal atoms and a halide are formed, and the sacrificial metal layer is replaced with a deposition metal layer such as titanium (Ti) or platinum (Pt), by supplying a metal halide gas having a halogen coherence smaller than the halogen coherence of the metal atoms in the sacrificial metal layer. If such a process is used to form a capacitor lower electrode or form an ohmic layer on the bottom of a contact hole, a metal layer can be selectively formed at a temperature of 500 DEG C or lower.

Description

經濟部中央標準局貝工消費合作社印*. 403991 五、發明説明（I ) 本發明之背景 1. 本發明之領域 本發明係有關於一種製造半導體裝置的方法，並且更 特別地是有關於形成選擇性金屬層之方法，和使用此來形 成半導體裝置電容器與塡充接觸孔之方法。 2. 相關技術之說明 由於半導體裝置變得高度整合化且複雜化，所以在製 造半導體裝置時’金屬層必須經常選擇性地被形成。在半 導體裝置之電容器的製程中，一較低電極係使用金屬而非 多晶矽來形成，以獲致高電容量，因而獲得金屬-絕緣體_ 矽(MIS)或金屬-絕緣體-金屬(MIM)結構。或者，在塡充接 觸孔的製程中’一歐姆層(ohmic layer)形成於具有高的高寬 比之微小接觸孔的底部。上述之二個製程具有許多的困難 〇 在製造具有金屬較低電極之電容器的製程中，其係非 常難以在未將金屬層佈局圖案化的情況下，選擇性地沉積 一金屬層於半球形晶粒(hemispherical grain，HSG)多晶石夕 較低電極上。目前，該項技術尙爲未知。再者，爲了使用 具有鈣鈦礦結構之PZT (Pb(Zr，Ti)03)或BST (BaSrTi03)作 爲電容器之高介電膜，當介電膜被沉積時，最好使用不會 被氧化且具有優越漏電流性質的鉑(Pt)，而非既存的多晶 矽電極。然而，當諸如鉑膜等金屬層以毯覆式法而非選擇 性法被沉積時，蝕刻將變得困難。亦即，當以毯覆式法所 形成之鉑膜使用氯氣(Cl2)作爲蝕刻劑做乾式蝕刻時，所產 4 本紙伕尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再4/讀本頁) -裝· 訂 A7 B7 inafl-Qt 五、發明説明（：！） 生的PtClx蝕刻副產物係非揮發性導電高分子。因此，必 須額外執行用溼式蝕刻移除PtClx的製程。在溼式蝕刻製 程中，由於部分鉑較低電極將一道被蝕刻，所以將難以在 要求微細佈局圖案的動態隨機存取記憶體(DRAM)的製程中 ，執行一重複性的製程。 再者，歐姆層將形成於接觸孔的底部，其係藉由電漿 增強化學氣相沉積(PECVD)或濺鏟，形成諸如鈦等具有高 熔點的高導電性金屬。然而，當用濺鍍形成歐姆層時，梯 級覆蓋(step coverage)係不良的。該電漿增強化學氣相沉積 並不適合應用於實際製程中，因爲漏電流將因600°C或更 高溫的高沉積溫度而增加，因此半導體裝置的電性將劣化 〇 此外，若諸如鈦(Ti)層等歐姆層係以濺鎪形成，而一 諸如氮化鈦(TiN)層等阻障層係以化學氣相沉積(CVD)形成 於歐姆層上，則歐姆層可能被侵蝕，而歐姆層與阻障層之 間的界面將剝離。若阻障層(TiN)係以濺鏟形成於鈦(Ti)歐 姆層上，則歐姆層與阻障層之間的界面將不會剝離。然而 ，當後續製程中以CVD而使鎢形成塡充接觸之插塞(piUg) 層時，剝離的問題將發生。 因此，要求一種選擇性地形成一金屬層於半導體裝置 的電性不會被劣化的500°C或更低的溫度之方法。然而， 在目前，其係極難以將該技術實行於形成電容器之較低電 極與形成接觸孔之歐姆層的製程中。 5 本紙張尺度適用中國國家標準（CNS > Α4規格（210Χ297公釐） ---------裝— (請先聞讀背面之注意事項再^Γ本頁) 、·ιτ 經濟部中央標準局貝工消费合作社印装 經濟部中央標準局貝工消费合作杜印装 _ 403991 B7____ 五、發明説明（$ ) 主發明之槪要 爲解決上述之問題，本發明之一目的係提供一種形成 選擇性金屬層之方法，藉此在500°C或更低之溫度所選擇 性地沉積之一犧牲金屬層，爲沉積金屬層所取代，此乃將 犧牲金屬層與具有鹵素親和力較犧牲金屬層中之金屬原子 的鹵素親和力爲低之金屬鹵素化合物氣體反應而達成。 本發明之另一個目的，係提供一種使用選擇性金屬層 形成法來形成半導體裝置電容器之方法。 本發明之又一目的，係提供—種使用選擇性金屬層形 成法塡充接觸孔之方法。 因此，爲達成第一個目的，在選擇性金屬層形成法中 ’ 一絕緣膜與一導電層形成其上之半導體基板置入腔室中 ，氫氣與砂院(silane)之混合物的淸洩氣體(purge gas)供給 至腔室中。藉由提供對於絕緣膜與導電層乃選擇性沉積之 犧牲金屬源氣體至腔室中，一犧牲金屬層僅形成於導電層 上。該犧牲金屬源氣體若非氫化二甲基鋁（DMAH : (CH3)2A1H)，則爲二甲基乙胺鋁烷（DMEAA : (CH3)2C2H5N:A1H3)。最後，藉由供給具有鹵素親和力較犧 牲金屬層中之金屬原子的鹵素親和力爲低之金屬鹵化物氣 體至腔室，該犧牲金屬層被沉積金屬層所取代。 根據本發明之一較佳實施例，淸洩氣體將不斷地供給 ，或者先被供給一預定量以做淸洩，並且於犧牲金屬層形 成並爲沉積金屬層取代後週期性地以預定的量供給。在此 ，沉積金屬層被取代後所供給之淸洩氣體的供給時間與數 _6_. 本紙張尺度適用中Λ家標準（CNS ) A4規格（210X297公釐） ----------^------1Τ------^ (請先閱讀背面之注意事項再本頁) · ， 經濟部中央樣準局貝工消费合作社印装 403991__B7___ 五、發明説明（★) 量，宜大於其他步驟。 絕緣膜宜爲氧化物膜(si〇2)或含有氧化物膜之複合物 膜，以及導電層爲以雜質摻雜之矽或金屬所形成。 沉積金屬層之金屬最好爲由鈦、鉅、锆、鈴、鈷、鉬 、鎢、鎳以及鉑等所組成之族群中擇一。當沉積金屬爲鈦 時，最好使用TiCl4作爲金屬鹵素化合物氣體。再者，當 沉積金屬爲鉑時，最好藉由溶解氯化鉑(Cl6H6Pt)或PtCl2於 水(H20)或乙醇並將Cl6H6Pt或PtCl2汽化所獲得的氣體， 來做爲金屬鹵素化合物氣體。 爲達成第二個目的，在使用一選擇性金屬層形成法之 形成半導體裝置電容器的方法中，一曝露出半導體基板源 極區的接觸孔被形成，其係藉由形成諸如氧化物膜(Si02) 或包含有氧化物膜的複合物物膜等絕緣膜於半導體基板上 ’並將該絕緣膜做佈局圖案而得。一導電層係由塡充接觸 孔並覆蓋絕緣膜之摻雜雜質的多晶矽或金屬所形成。一連 結至接觸孔的導電層佈局圖案，係由佈局圖案化或化學機 械拋光該導電層而形成。該半導體基板置入腔室中，且氫 氣(H2)與矽烷(SiH4)之混合物的淸洩氣體供給至腔室中。藉 著將對於絕緣膜與導電層乃選擇性沉積的犧牲金屬源氣體 供給至腔室中，一犧牲金屬層僅形成於導電層上。在此， 該犧牲金屬源氣體若非氫化二甲基鋁(DMAH : (CH3)2A1H) ，則爲二甲基乙胺鋁烷(DMEAA : (CH3)2C2H5N:A1H3)。其 次’藉由供給具有鹵素親和力較犧牲金屬層中之金屬原子 的鹵素親和力爲低之金屬鹵化物氣體至腔室，該犧牲金屬 _ 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閲讀背面之注意事項再^<本頁) 訂 A7 B7 403991 五、發明説明（t ) 層被沉積金屬層所取代。最後，一介電膜形成於沉積金屬 層上，而一較高電極則形成於該介電膜上。 根據本發明之一較佳實施例，形成一半球形晶粒於導 電佈局圖案表面上的步驟，可被包含於導電層佈局圖案形 成後。 淸洩氣體最好不斷地被供給，或者先被供給一預定量 以做淸洩，並且於犧牲金屬層形成並爲沉積金屬層取代後 週期性地以預定的量供給。在此，沉積金屬層被取代後所 供給之淸洩氣體的供給時間與數量，宜大於其他步驟的供 給。 再者，根據本發明之較佳實施例，使沉積金屬層矽化 的步驟，可進一步包括於形成沉積金屬層的步驟之後。 爲達成第三個目的，在使用選擇性金屬層形成法塡充 接觸孔的方法中，一諸如氧化物膜(si〇2)或包括有氧化物 膜之複合物膜等的絕緣膜，形成於半導體基板上。暴露出 摻雜雜質多晶矽或諸如TiN等金屬之較低膜之接觸孔，藉 由將絕緣膜佈局圖案化而形成。接觸孔形成其上之半導體 基板被置入腔室中，且氫氣(H2)與矽烷(SiH4)之混合物的淸 洩氣體被供給至腔室中。一犧牲金屬層係由僅位於於較低 膜上的鋁(A1)所組成，其藉由將對於絕緣膜與較低膜有選 擇性沉積的犧牲金屬源氣體供給至腔室中而得。在此，該 犧牲金屬源氣體若非氫化二甲基鋁(DMAH : (CH3)2A1H), 則爲二甲基乙胺鋁烷(DMEAA : (CH3)2C2H5N:A1H3)。其次 ，藉由供給具有鹵素親和力較犧牲金屬層中之金屬原子的 8 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公釐） ----------装------、玎------m (請先閱讀背面之注意事項再本頁) · ， 經濟部中央標準局爲工消费合作社印装 403991 _b7____ 五、發明説明（f ) 齒素親和力爲低之金屬鹵化物氣體至腔室，該犧牲金屬層 被沉積金屬層所取代。最後，一塡充接觸孔的導電層被形 成。 根據本發明之一較佳實施例，淸洩氣體不斷地被供給 ，或者先被供給一預定量以做淸洩，並且於犧牲金屬層形 成並爲沉積金屬層取代後週期性地以預定的量供給。在此 ，沉積金屬層被取代後所供給之淸洩氣體的供給時間與數 量，宜大於其他步驟的供給。 再者，在形成諸如TiN層等阻障層於沉積金屬層上的 步驟，最好進一步包含於以沉積金屬層取代犧牲金屬層的 步驟之後。 根據本發明，在製造半導體裝置的過程中，一在500 °C或更低溫度所選擇性地形成之特定金屬，應用於用以形 成電容器之較低電極的過程中，因而可於無嚴重製程困難 下形成電容器之金屬較低電極。再者，當歐姆層形成於接 觸孔的底部表面時，基於侵蝕所造成的特性劣化與薄膜剝 離將可避免，並同時增加梯級覆蓋的能力。 經濟部中央橾準局員工消費合作社印製 ----------装— (請先閲讀背面之注意事項再本頁) 圖式之簡略說明 本發明之上述目的與優點’將藉著詳細地說明較佳實 施例並參考附圖而變得更淸楚，其中： 圖1係舉例說明根據本發明之一用以形成選擇性金屬 層之方法的流程圖； 圖2A與2B係根據本發明之用以形成一選擇性金屬層 9____ 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X；Z97公釐） 經濟部中央樣準局員工消費合作社印製 A7 ___B7____ 五、發明説明（rj ) 之方法的氣體流動圖； 圖3係舉例說明根據本發明之一種使用該選擇性金屬 層形成法而形成電容器之方法的流程圖； 圖4A至4F係舉例說明根據本發明之第一個實施例， 使用形成選擇性金屬層之製程而形成電容器之方法的剖面 圖， 圖5A至5F係舉例說明根據本發明之第二個實施例， 使用形成選擇性金屬層之製程而形成電容器之方法的剖面 圖； 圖6A至6C係舉例說明根據本發明之第三個實施例， 使用形成選擇性金屬層之製程而形成電容器之方法的剖面 圖， 圖7係圖示根據本發明之使用選擇性金屬層形成法塡 充接觸孔之方法的流程圖；以及 圖8A至8E係舉例說明根據本發明之第四個實施例， 使用選擇性金屬層形成法的接觸孔塡充法之剖面圖。 較佳實施例之說明 參考圖1，首先，在步驟1〇〇中，一絕緣膜與一導電 層形成其上的半導體基板被置入半導體製造裝置的腔室中 。在此，該絕緣膜係不吸附被沉積金屬而形成選擇性金屬 層之氧化物膜（Si02)，或氧化物膜的複合物膜.。該導電層 係由諸如氮化鈦（TiN)等金屬或摻雜以具有氫端自由基 (hydrogen termination radical)之雜質的多晶砂所形成，而 10 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公H " ---------^------tT------^ (請先閱讀背面之注意事項再4又本頁) - - 經濟部中央標隼局貝工消費合作社印裝 403991 五、發明説明（8 ) 鋁A1將可輕易地且選擇性地沉積於其上。其次，在步驟 11〇中’作爲淸洩氣體之混合有氫氣％與矽烷SiH4之氣體 ’被供給至腔室中以淸除腔室之內部。在此，淸洩氣體可 利用下列二種方法供給。第一種方法，淸洩氣體可從—開 始就不斷地以預定量供給。第二種方法，在供給犧牲金屬 源氣體或金屬鹵化物氣體後將淸洩氣體供給至腔室，以淸 除腔室’並且於沉積一犧牲金屬層之步驟12〇與以一沉積 金屬層取代犧牲金屬層的步驟140之後，一預定量的淸洩 氣體可被週期性地供給。 在步驟120中，一由鋁(A1)所做的犧牲金屬層，係藉 由供給作爲犧牲金屬源氣體的氫化二甲基鋁（DMAH : (CH3)2A1H)或二甲基乙胺鋁烷（DMEAA : (CH3)2C2H5N:A1H3)至腔室中，而形成於導電層的表面上。 在此’爲何犧牲金屬層由鋁所製作的原因，係因鋁具有諸 如Cl、Br、F或I等鹵素族元素與最高的吉柏斯自由能 (Gibbs free energy)，以及銘的各種前驅物已經開發出來。 用於鋁沉積的前驅物包括有：氫化二異丁基鋁((C4H9)2A1H) 、三異丁基鋁（(C4H9)3A1)、三乙基鋁（(C2H5)3A1)、三甲基 鋁（(CH3)3A1)、三甲胺鋁烷（A1H3N(CH3)3)、氫化二甲基鋁 ((CH3)2A1H) ' 以及二甲基乙胺鋁烷（(CH3)2C2H5N:A1H3)。 氫化二甲基鋁（(CH3)2A1H)(此後簡稱爲“DMAH”）以及二 甲基乙胺鋁烷（(CH3)2C2H5N:A1H3)(此後簡稱爲“DMEAA” )，並不被沉積於諸如氧化物膜（Si〇2)等絕緣膜上，但其 僅選擇性地被沉積於諸如TiN等金屬或被摻雜以具有氫 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ----------f------#------練、 (請先閱讀背面之注意事項再^^、本頁) · - 經濟部中央搮準局貝工消費合作社印裝 403991 五、發明説明（？） (H2)端自由基雜質之矽上。亦即，DMAH以及DMEAA並 不被沉積於腔室中之半導體基板絕緣膜上，但僅選擇性地 被沉積於導電層上。 其次，在步驟Π0中，一淸洩氣體被供給至腔室中， 其中該腔室具有犧牲金屬層被選擇性地形成其上之半導體 基板，以將犧牲金屬源氣體由腔室淸洩掉。 其次，在步驟140中，TiCl4被更換爲A1C1X，而犧牲 金屬層的鋁被取代爲鈦所做的沉積金屬層，其係藉由半導 體基板與被供給至腔室之包含有沉積用之金屬之金屬鹵化 物氣體的TiCU反應而得。在此，金屬鹵化物氣體中的金 屬，具有較犧牲金屬層中的金屬原子爲弱的鹵素親和力， 戶斤以犧牲金屬層的金屬原子與金屬鹵化物氣體反應。亦即 ，TiCl4的吉柏斯自由能在427°C(700K)時爲678.3kJ/mol， 其係高於大部份金屬鹵化物的吉柏斯自由能；然而，A1C16 的吉柏斯自由能爲1121_9kJ/m〇l’高於TiCM的吉柏斯自 由能，所以犧牲金屬層的金屬原子與金屬鹵化物氣體反應 。因此，犧牲金屬層的鋁原子由導電層的表面分離，並與 具有較高親和力的氯(C1)反應’而變成氣態的A1C1X。再者 ，由TiCl4所分解出的鈦(Ti)被沉積於鋁原子所離開之導電 層表面的空缺位置。當具有較小吉柏斯自由能（亦即犧牲 金屬與鹵素原子之間的親和力）的金屬鹵化物氣體’供給 至具有犧牲金屬層形成其上之半導體基板的腔室中時，一 金屬層將可選擇性地被形成。如上述所形成的沉積金屬層 將可使用鈦、钽、锆、給、鈷、鉬、鎢、鎳或鉑等。 _ \2__ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I I I I n n I I 線 (請先閲讀背面之注意事項再填r本頁) _ 經濟部中央標準局男工消费合作社印製 A7 403991 87 五、發明説明（rc ) 再此，當沉積金屬爲鈦時，TiCl4係被使用爲金屬鹵化 物氣體；而當沉積金屬爲鉑時，藉由溶解以並汽化氯化鉑 (Cl6H6Pt)或PtCl2於水(H20)或乙醇所獲得的氣體，來用做 金屬鹵化物氣體。再者，當沉積金屬爲鈷時，若非氯化鈷Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives *. 403991 V. Description of the Invention (I) Background of the Invention 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to the formation of A method for selecting a metal layer, and a method for forming a contact hole between a capacitor of a semiconductor device and a semiconductor using the same. 2. Description of Related Technology Since semiconductor devices have become highly integrated and complicated, a metal layer must be selectively formed when manufacturing semiconductor devices. In the fabrication of capacitors for semiconductor devices, a lower electrode is formed using a metal rather than polycrystalline silicon to achieve a high capacitance, thereby obtaining a metal-insulator-silicon (MIS) or metal-insulator-metal (MIM) structure. Alternatively, in the process of filling the contact holes, an 'ohmic layer' is formed on the bottom of a minute contact hole having a high aspect ratio. The above two processes have many difficulties. In the process of manufacturing capacitors with lower metal electrodes, it is very difficult to selectively deposit a metal layer on a hemispherical crystal without patterning the layout of the metal layer. Hemispherical grain (HSG) polycrystalline stone on the lower electrode. This technology is currently unknown. Furthermore, in order to use PZT (Pb (Zr, Ti) 03) or BST (BaSrTi03) with a perovskite structure as the high dielectric film of the capacitor, when the dielectric film is deposited, it is preferable to use a film that does not oxidize and Platinum (Pt) with superior leakage current properties, rather than existing polycrystalline silicon electrodes. However, when a metal layer such as a platinum film is deposited by a blanket method instead of a selective method, etching becomes difficult. That is, when the platinum film formed by the blanket method uses chlorine gas (Cl2) as an etchant for dry etching, the 4 paper sheets produced are in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) (please first Read the notes on the back and read 4 / read this page again)-Binding and ordering A7 B7 inafl-Qt 5. Description of the invention (:!) The PtClx etching by-product produced is a non-volatile conductive polymer. Therefore, a process of removing PtClx by wet etching must be additionally performed. In the wet etching process, since some of the lower platinum electrodes will be etched together, it will be difficult to perform a repetitive process in a dynamic random access memory (DRAM) process that requires fine layout patterns. In addition, an ohmic layer will be formed at the bottom of the contact hole, which is formed by plasma enhanced chemical vapor deposition (PECVD) or a shovel to form a highly conductive metal such as titanium with a high melting point. However, when an ohmic layer is formed by sputtering, step coverage is poor. The plasma-enhanced chemical vapor deposition is not suitable for practical applications, because the leakage current will increase due to a high deposition temperature of 600 ° C or higher, so the electrical properties of semiconductor devices will deteriorate. In addition, if such as titanium (Ti ) And other ohmic layers are formed by sputtering, and a barrier layer such as a titanium nitride (TiN) layer is formed on the ohmic layer by chemical vapor deposition (CVD), the ohmic layer may be eroded, and the ohmic layer The interface with the barrier layer will peel off. If the barrier layer (TiN) is formed on the titanium (Ti) ohmic layer by a shovel, the interface between the ohmic layer and the barrier layer will not peel off. However, when tungsten is formed into a piUg layer of rhenium-filled contact by CVD in a subsequent process, the problem of peeling will occur. Therefore, a method of selectively forming a metal layer at a temperature of 500 ° C or lower, which does not deteriorate the electrical properties of the semiconductor device, is required. However, at present, it is extremely difficult to implement the technology in a process for forming a lower electrode of a capacitor and an ohmic layer for forming a contact hole. 5 This paper size applies to Chinese national standards (CNS > Α4 size (210 × 297 mm) --------- installation— (please read the precautions on the back before reading this page ^ Γ) Ministry of Economic Affairs) Central Bureau of Standards Shellfish Consumer Cooperative Printing Printed by the Central Bureau of Standards Shellfish Consumer Cooperative Du Print _ 403991 B7____ 5. Description of the Invention ($) To solve the above problems, one of the objects of the present invention is to provide a A method for forming a selective metal layer, whereby a sacrificial metal layer selectively deposited at a temperature of 500 ° C or lower is replaced by the deposited metal layer. This is to sacrifice the sacrificial metal layer with a halogen which has a higher affinity than the sacrificial metal. The halogen affinity of the metal atoms in the layer is achieved by a low metal halogen compound gas reaction. Another object of the present invention is to provide a method for forming a semiconductor device capacitor using a selective metal layer formation method. Another object of the present invention Is to provide a method for filling contact holes using a selective metal layer forming method. Therefore, in order to achieve the first objective, in the selective metal layer forming method, a The semiconductor substrate on which the film and a conductive layer are formed is placed in a chamber, and a purge gas of a mixture of hydrogen and silane is supplied into the chamber. By providing the insulating film and the conductive layer, A sacrificial metal source gas is selectively deposited into the chamber, and a sacrificial metal layer is formed only on the conductive layer. If the sacrificial metal source gas is not dimethyl aluminum hydride (DMAH: (CH3) 2A1H), it is dimethylethyl Aminealane (DMEAA: (CH3) 2C2H5N: A1H3). Finally, by supplying a metal halide gas having a lower halogen affinity than that of the metal atoms in the sacrificial metal layer to the chamber, the sacrificial metal layer is deposited The metal layer is replaced. According to a preferred embodiment of the present invention, the vent gas is continuously supplied, or a predetermined amount is first supplied for venting, and periodically after the formation of the sacrificial metal layer and the replacement of the deposited metal layer The ground is supplied in a predetermined amount. Here, the supply time and number of the blow-by gas supplied after the deposited metal layer is replaced_6_. This paper size is applicable to the Λ family standard (CNS) A4 specification (210X297 mm)- -------- ^- ---- 1Τ ------ ^ (Please read the notes on the back first and then on this page) · ， Printed by Shellfish Consumer Cooperative of Central Prototype Bureau of the Ministry of Economic Affairs 403991__B7___ 5. The amount of invention description (★) should be greater than Other steps: The insulating film is preferably an oxide film (SiO2) or a composite film containing an oxide film, and the conductive layer is formed of silicon or metal doped with impurities. The metal for depositing the metal layer is preferably titanium. , Giant, zirconium, boron, cobalt, molybdenum, tungsten, nickel, and platinum. When the deposition metal is titanium, it is best to use TiCl4 as the metal halogen compound gas. Furthermore, when the deposition metal is platinum In this case, the metal halide gas is preferably obtained by dissolving platinum chloride (Cl6H6Pt) or PtCl2 in water (H20) or ethanol and vaporizing Cl6H6Pt or PtCl2. To achieve the second object, in a method for forming a semiconductor device capacitor using a selective metal layer forming method, a contact hole exposing a source region of a semiconductor substrate is formed by forming a contact hole such as an oxide film (Si02 ) Or an insulating film such as a composite film containing an oxide film on a semiconductor substrate 'and obtained by using the insulating film as a layout pattern. A conductive layer is formed of polycrystalline silicon or metal that is doped with impurities and filled with contact holes and covered with an insulating film. A conductive layer layout pattern connected to the contact hole is formed by layout patterning or chemical mechanical polishing of the conductive layer. The semiconductor substrate is placed in a chamber, and a purge gas of a mixture of hydrogen gas (H2) and silane (SiH4) is supplied into the chamber. By supplying a sacrificial metal source gas that is selectively deposited for the insulating film and the conductive layer into the chamber, a sacrificial metal layer is formed only on the conductive layer. Here, if the sacrificial metal source gas is not dimethyl aluminum hydride (DMAH: (CH3) 2A1H), it is dimethylethylamine aluminoxane (DMEAA: (CH3) 2C2H5N: A1H3). Secondly, by supplying a metal halide gas with a halogen affinity lower than that of the metal atoms in the sacrificial metal layer to the chamber, the sacrificial metal _ 7 This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 (Mm) (Please read the precautions on the back before ^ < this page) Order A7 B7 403991 V. Description of the invention (t) The layer is replaced by a deposited metal layer. Finally, a dielectric film is formed on the deposited metal layer, and a higher electrode is formed on the dielectric film. According to a preferred embodiment of the present invention, the step of forming hemispherical crystal grains on the surface of the conductive layout pattern may be included after the conductive layer layout pattern is formed. The purge gas is preferably continuously supplied, or a predetermined amount is first supplied for purge, and is periodically supplied in a predetermined amount after the sacrificial metal layer is formed and replaced by the deposited metal layer. Here, the supply time and quantity of the purge gas supplied after the deposition metal layer is replaced should preferably be greater than the supply in other steps. Furthermore, according to a preferred embodiment of the present invention, the step of silicifying the deposited metal layer may further include the step of forming the deposited metal layer. In order to achieve the third object, in a method of filling a contact hole using a selective metal layer forming method, an insulating film such as an oxide film (SiO2) or a composite film including an oxide film is formed on On a semiconductor substrate. The contact holes of the lower film doped with polycrystalline silicon or a metal such as TiN are exposed by patterning the insulating film layout. The semiconductor substrate on which the contact hole is formed is placed in the chamber, and a purge gas of a mixture of hydrogen (H2) and silane (SiH4) is supplied into the chamber. A sacrificial metal layer is composed of aluminum (A1) located only on the lower film, and is obtained by supplying a sacrificial metal source gas selectively deposited to the insulating film and the lower film into the chamber. Here, if the sacrificial metal source gas is not dimethylaluminum hydride (DMAH: (CH3) 2A1H), it is dimethylethylamine alumane (DMEAA: (CH3) 2C2H5N: A1H3). Secondly, by supplying 8 paper sizes with halogen affinity that is lower than the metal atoms in the sacrificial metal layer, the Chinese National Standard (CNS) A4 specification (210X297 mm) is applied. -、 玎 ------ m (Please read the notes on the back first and then this page) · ， Printed by the Central Bureau of Standards of the Ministry of Economic Affairs for the Industrial and Consumer Cooperatives 403991 _b7____ 5. Description of the invention (f) The affinity of the tooth is low Metal halide gas to the chamber, the sacrificial metal layer is replaced by a deposited metal layer. Finally, a conductive layer filled with contact holes is formed. According to a preferred embodiment of the present invention, the purge gas is continuously supplied, or a predetermined amount is first supplied for purge, and periodically after the sacrificial metal layer is formed and replaced by the deposited metal layer, the predetermined amount supply. Here, the supply time and amount of the bleed gas supplied after the deposited metal layer is replaced should be greater than the supply in other steps. Furthermore, the step of forming a barrier layer such as a TiN layer on the deposited metal layer is preferably further included after the step of replacing the sacrificial metal layer with a deposited metal layer. According to the present invention, in the process of manufacturing a semiconductor device, a specific metal selectively formed at a temperature of 500 ° C or lower is applied to a process for forming a lower electrode of a capacitor, and thus can be used without serious processes. The metal lower electrode of the capacitor is formed under difficulty. Furthermore, when the ohmic layer is formed on the bottom surface of the contact hole, the deterioration of characteristics and peeling of the film due to erosion can be avoided, and at the same time, the ability of step coverage can be increased. Printed by the Consumers' Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs of the People's Republic of China ————————— (Please read the precautions on the back before this page) A brief illustration of the above-mentioned objects and advantages of the present invention will be borrowed The preferred embodiment will be explained in more detail with reference to the accompanying drawings, in which: FIG. 1 is a flowchart illustrating a method for forming a selective metal layer according to one of the present invention; FIGS. 2A and 2B are based on The present invention is used to form a selective metal layer 9____ This paper size is applicable to the Chinese National Standard (CNS) A4 (210X; Z97 mm) Printed by the Consumer Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs A7 _B7____ 5. Description of the invention ( rj) method; FIG. 3 is a flowchart illustrating a method for forming a capacitor using the selective metal layer forming method according to the present invention; and FIGS. 4A to 4F are examples illustrating the first method according to the present invention. Example, a cross-sectional view of a method for forming a capacitor using a process for forming a selective metal layer, and FIGS. 5A to 5F illustrate a method for forming a selective metal layer according to a second embodiment of the present invention. 6A to 6C are cross-sectional views illustrating a method of forming a capacitor using a process for forming a selective metal layer according to a third embodiment of the present invention, and FIG. 7 is a diagram illustrating a method according to the present invention. A flowchart of a method for filling a contact hole using the selective metal layer forming method of the invention; and FIGS. 8A to 8E illustrate a contact hole filling method using the selective metal layer forming method according to a fourth embodiment of the present invention; Section view. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, first, in step 100, a semiconductor substrate on which an insulating film and a conductive layer are formed is placed in a cavity of a semiconductor manufacturing apparatus. Here, the insulating film is not an oxide film (Si02) or a composite film of an oxide film that forms a selective metal layer by adsorbing the deposited metal. The conductive layer is formed of a metal such as titanium nitride (TiN) or polycrystalline sand doped with impurities having a hydrogen termination radical, and 10 paper sizes are applicable to the Chinese National Standard (CNS) A4 specifications (210X297 male H " --------- ^ ------ tT ------ ^ (please read the precautions on the back before 4 and this page)--Ministry of Economy Printed by the Central Bureau of Standardization, Shellfish Consumer Cooperative Co., Ltd. 403991 V. Description of the invention (8) Aluminum A1 can be easily and selectively deposited thereon. Secondly, in step 110, hydrogen is used as a bleed gas mixture with hydrogen% The gas 'with silane SiH4' is supplied to the chamber to purge the interior of the chamber. Here, the purge gas can be supplied using the following two methods. The first method, purge gas can be continuously used from the beginning. Predetermined supply. The second method is to supply a bleed gas to the chamber after the sacrificial metal source gas or metal halide gas is supplied, to eliminate the chamber, and to deposit a sacrificial metal layer in steps 12 and 1 After the step 140 of depositing a metal layer to replace the sacrificial metal layer, a predetermined amount of purge gas It is supplied periodically. In step 120, a sacrificial metal layer made of aluminum (A1) is supplied by supplying dimethylaluminum hydride (DMAH: (CH3) 2A1H) or dimethyl aluminum as a source metal of the sacrificial metal. Methyl ethyl aluminoxane (DMEAA: (CH3) 2C2H5N: A1H3) into the cavity and formed on the surface of the conductive layer. Here's why the sacrificed metal layer is made of aluminum because aluminum has properties such as Cl, Br, F or I and other halogen group elements and the highest Gibbs free energy (Gibbs free energy), as well as various precursors have been developed. The precursors for aluminum deposition include: diisobutyl aluminum hydride ( (C4H9) 2A1H), triisobutylaluminum ((C4H9) 3A1), triethylaluminum ((C2H5) 3A1), trimethylaluminum ((CH3) 3A1), trimethylamine alumane (A1H3N (CH3) 3 ), Dimethylaluminum hydride ((CH3) 2A1H) 'and dimethylethylamine aluminoxane ((CH3) 2C2H5N: A1H3). Dimethyl aluminum hydride ((CH3) 2A1H) (hereinafter referred to as "DMAH") And dimethyl ethyl aluminoxane ((CH3) 2C2H5N: A1H3) (hereinafter simply referred to as "DMEAA") is not deposited on an insulating film such as an oxide film (SiO2), but it is only selectively Sank For metals such as TiN or doped to have a hydrogen paper size, applicable Chinese National Standard (CNS) A4 specification (210X297 mm) ---------- f ------ # --- --- Exercise, (Please read the precautions on the back before ^^, this page) ·-Printed by the Shellfish Consumer Cooperative of the Central Procurement Bureau of the Ministry of Economic Affairs 403991 5. Description of the invention (? ) On silicon with (H2) terminal free radical impurities. That is, DMAH and DMEAA are not deposited on the semiconductor substrate insulating film in the chamber, but are selectively deposited only on the conductive layer. Secondly, in step Π0, a purge gas is supplied to the chamber, wherein the chamber has a semiconductor substrate on which a sacrificial metal layer is selectively formed, so as to purge the sacrificial metal source gas from the chamber. Secondly, in step 140, TiCl4 is replaced with A1C1X, and the sacrificial metal layer is replaced with titanium. The deposited metal layer is formed by a semiconductor substrate and a metal containing a metal for deposition supplied to the chamber. It is obtained by reaction of TiCU of metal halide gas. Here, the metal in the metal halide gas has a weaker halogen affinity than the metal atoms in the sacrificial metal layer, and the metal atom of the sacrificial metal layer reacts with the metal halide gas. That is, the Gibbs free energy of TiCl4 is 678.3kJ / mol at 427 ° C (700K), which is higher than the Gibbs free energy of most metal halides; however, the Gibbs free energy of A1C16 It is 1121_9kJ / mol ′ higher than the Gibbs free energy of TiCM, so the metal atoms of the sacrificial metal layer react with the metal halide gas. Therefore, the aluminum atom of the sacrificial metal layer is separated from the surface of the conductive layer and reacts with chlorine (C1) having a higher affinity 'to become a gaseous A1C1X. Furthermore, titanium (Ti) decomposed from TiCl4 is deposited at a vacant position on the surface of the conductive layer where the aluminum atoms leave. When a metal halide gas having a smaller Gibbs free energy (that is, the affinity between a sacrificial metal and a halogen atom) is supplied to a chamber having a semiconductor substrate on which a sacrificial metal layer is formed, a metal layer will Can be selectively formed. The deposited metal layer formed as described above will use titanium, tantalum, zirconium, zinc, cobalt, molybdenum, tungsten, nickel, or platinum. _ \ 2__ This paper size applies to China National Standard (CNS) A4 (210X297 mm) IIII nn II line (please read the precautions on the back before filling this page) _ Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Male Workers Consumer Cooperative A7 403991 87 V. Description of the Invention (rc) Here again, when the deposited metal is titanium, TiCl4 is used as a metal halide gas; and when the deposited metal is platinum, platinum chloride (Cl6H6Pt) is dissolved and vaporized. Or PtCl2 gas obtained from water (H20) or ethanol to be used as metal halide gas. Furthermore, when the deposited metal is cobalt, if it is not cobalt chloride,

CoCl2、氟化鈷CoF2，則爲碘化鈷CoI2被用爲金屬鹵化物 氣體。在此’因爲含鉑之金屬鹵化物一氯化鉑（Cl6H6Pt)或CoCl2, cobalt fluoride CoF2, and cobalt iodide CoI2 are used as metal halide gas. Here ’s because the platinum-containing metal halide monoplatinum chloride (Cl6H6Pt) or

PtCl2爲固態，所以其必須被溶解於溶劑並汽化後方可使用 。因爲鉑與其他金屬比較下係活性較低者，所以其與鹵素 原子具有較低的親和力。因此，當鉑與諸如鋁等犧牲金屬 層反應時，其可輕易地被沉積。 當被沉積的金屬爲鉬時，若非雙環戊二烯二氯化鉬 ((C5H5)2MoC12)、環戊二烯四氯化鉬（c5h5MoC14)、氟化鉬PtCl2 is solid, so it must be dissolved in a solvent and vaporized before it can be used. Because platinum is less active than other metals, it has a lower affinity for halogen atoms. Therefore, when platinum reacts with a sacrificial metal layer such as aluminum, it can be easily deposited. When the deposited metal is molybdenum, if it is not dicyclopentadiene molybdenum dichloride ((C5H5) 2MoC12), cyclopentadiene molybdenum tetrachloride (c5h5MoC14), molybdenum fluoride

MoF6、氯化鉬MoC13/MoC15，則爲碘化鉬MoI2，被用爲金 屬鹵化物氣體。當所沉積的金屬爲鎳時，若非 [(C6H5)2PCH2CH2CH2P(C6H5)2]NiCl2(氯化 1，2-雙(二苯基膦) 丙烷鎳）、[(C6H5)3P]2NiBr2(溴化雙（三苯基膦）鎳）、 [(CiHshPhNiClX氯化雙（三苯基膦）鎮）、[Ni(NH3)6]Cl2(氯 化六氨鎳）、[Ni(NH3)6]I2(碘化六氨鎳）、NiBr/NiBr2(溴化鎳 )、NiCh(氯化鎳）、NiF2(氯化鎳），則爲Nil2(碘化鎳），被 用爲金屬鹵化物氣體。當沉積金屬爲鎢時，若非雙環戊二 烯二氯化鎢(C5H5)2WC12、溴化鎢 WBr/W2Br/W2Br5、氯化 鎢WCU/WCU，則爲氟化鎢WF6，被用爲金屬鹵化物氣體 〇 作爲參考’表1至5顯示在絕對溫度700K(427t：)時 _ 13 本紙张尺度適用中國國家標準（CNS ) A4規格（210X297公釐) ----------裝— (請先閱讀背面之註意事項再^<本頁)MoF6 and MoC13 / MoC15 are molybdenum iodide MoI2 and are used as metal halide gas. When the deposited metal is nickel, if it is not [(C6H5) 2PCH2CH2CH2P (C6H5) 2] NiCl2 (1,2-bis (diphenylphosphine) propane chloride nickel), [(C6H5) 3P] 2NiBr2 (brominated dibromide (Triphenylphosphine) nickel), [(CiHshPhNiClX bis (triphenylphosphine) chloride), [Ni (NH3) 6] Cl2 (nickel hexaammonium chloride), [Ni (NH3) 6] I2 (iodine Hexammine), NiBr / NiBr2 (nickel bromide), NiCh (nickel chloride), NiF2 (nickel chloride), then Nil2 (nickel iodide), are used as metal halide gas. When the deposited metal is tungsten, if it is not dicyclopentadiene tungsten dichloride (C5H5) 2WC12, tungsten bromide WBr / W2Br / W2Br5, tungsten chloride WCU / WCU, it is tungsten fluoride WF6, and it is used as a metal halide. Gas 0 as a reference 'Tables 1 to 5 show when the absolute temperature is 700K (427t :) _ 13 This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) ---------- installed- (Please read the notes on the back before ^ < this page)

•1T 線 403991五、發明説明（丨丨） A7 7 Β ，多種金屬鹵化物氣體之吉柏斯自由能。 經濟部中央標準局員工消費合作杜印製 [表1] 在427°c時之各種含C1氣體化合物的吉柏斯自由能 化合物 吉柏斯自 由能 (kJ/mol) 化合物 吉柏斯自 由能 (kJ/mol) 化合物 吉柏斯自 由能 (kJ/mol) A12C16 -1121.9 HfCl3 -626.7 BeCl2 -373.1 ThCl4 -895.8 EuC13 -621.6 BC13 -367.7 UC15 -811.9 YbCl3 -621.5 SiCl3 -365.7 HfCU -804.7 K2C12 -609.8 SIICI4 -362.3 ZrCl4 -777.6 Rb2Cl2 -607.6 InCl3 -335.8 LaCl3 -708.9 Li2Cl2 -597.8 AlCh -305.5 PrCl3 -706.9 SiCl4 -569.6 TaCl3 -300.1 Ill2Cl6 -703.7 AICI3 -550.1 GeCl3 -299.8 CeCl3 -699.5 Fe2Cl6 -526.8 MnCl2 -286.4 NdCl3 -696.6 BaCl2 -524.3 WC15 -285.6 Be2Cl4 -692.6 SrCl2 -498.1 CsCl -276.7 T1CI4 -678.3 TaCl4 -497.5 ZnCl2 -273.5 GdCl3 -674.3 CaCl2 -489.1 WC14 -267.6 TbCl3 -668.1 PbCl4 -462.1 Ti2Cl2 -259.8 H0CI3 -659.7 VaCl4 -447.2 GaCl2 -258.4 ErCl3 -651.7 GeCU -410.8 SbCl5 -249.9 Cs2Cl2 -644.1 MgCl2 -407.8 CU3CI3 -242.9 TmCl3 -641.5 Fe2Cl4 -406.5 PC13 -242.3 TaCl5 -636.6 GaCl3 -388.6 FeCl3 -240.6 (請先閱讀背面之注意事項再^C本頁) •髮· 、-β 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） 403991 經濟部中央標準局員工消費合作社印製 五 、發明説明（) [表2] 在427°C時之各福 1含碘i氣體化合物的吉柏斯自由 能 化合物 吉柏斯自 由能 (kJ/mol) 化合物 吉柏斯自 由能 (kJ/mol) 化合物 吉柏斯自 由能 (kJ/mol) Thl4 -512 Zrl4 -409 Til4 -320 Α^Ιό -510 Hfl4 -405 Pbl4 -266 K2I2 -480 Dyl^ -402 Mgl2 -239 Lal3 -457 ΤΠΙΙ3 -399 Cul -237 ΡΠ3 -448 Gdh -388 Csl -220 Cel3 -442 Bal2 -380 Tal5 -202 Ndl3 -438 UI4 -377 Sil4 -150 Li2I2 -427 Srl2 -353 HI -11.8 Erl3 -410 Cal2 -338 • - [表3] 在427°C時之各S 1含溴Br氣體化合物的吉柏斯自E 白能 - 化合物 吉柏斯自 由能 (kJ/mol) 化合物 吉柏斯自 由能 (kJ/mol) 化合物 吉柏斯自 由能 (kJ/mol) Α12Βγ6 -860 HoBr3 -567 CaBr2 -435 Mg2Br4 -764 ΕγΒγ3 -566 PbBr4 -428 ThBr4 -743 TmBr3 -563 TaBrs -424 HfBr4 -639 TbBr3 -559 EuBr2 -413 ZrBr4 -627 DyBr3 -559 SiBr4 -387 LaBr3 -621 GdBr3 -551 CU3Br3 -187 CeBr3 -616 Li2Br2 -534 WBr6 -139 PrBr3 -612 TiBr4 -527 HBr -58.6 UBr4 -602 Na2Br2 -510 . _ NdBr3 -598 SrBr2 -453 - - 15 (請先閲讀背面之注意事項再r_vv本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -裝_• 1T line 403991 V. Description of the invention (丨 丨) A7 7 Β, Gibbs free energy of a variety of metal halide gases. Printed by the Consumer Co-operation Department of the Central Bureau of Standards of the Ministry of Economic Affairs [Table 1] Gibbs Free Energy Compounds (KJ / mol) of various C1 gas compounds at 427 ° C kJ / mol) Compound Gibbs Free Energy (kJ / mol) A12C16 -1121.9 HfCl3 -626.7 BeCl2 -373.1 ThCl4 -895.8 EuC13 -621.6 BC13 -367.7 UC15 -811.9 YbCl3 -621.5 SiCl3 -365.7 HfCU -804.7 K2C12 -609.8 SIICI4- 362.3 ZrCl4 -777.6 Rb2Cl2 -607.6 InCl3 -335.8 LaCl3 -708.9 Li2Cl2 -597.8 AlCh -305.5 PrCl3 -706.9 SiCl4 -569.6 TaCl3 -300.1 Ill2Cl6 -703.7 AICI3 -550.1 GeCl3 -299.8 CeCl3 -699.5 Fe2Cl6 -526.8 NClCl2 -286.9 -524.3 WC15 -285.6 Be2Cl4 -692.6 SrCl2 -498.1 CsCl -276.7 T1CI4 -678.3 TaCl4 -497.5 ZnCl2 -273.5 GdCl3 -674.3 CaCl2 -489.1 WC14 -267.6 TbCl3 -668.1 PbCl4 -462.1 Ti2Cl2 -259.8 H0CI3 -659.7 ErCl3 -651.7 GeCU -410.8 SbCl5 -249.9 Cs2Cl2 -644.1 MgCl2 -407.8 CU3CI3 -242.9 TmCl3 -641.5 Fe2Cl4 -406.5 PC13 -242.3 TaCl5 -636.6 GaCl3 -388.6 FeCl3 -2 40.6 (Please read the precautions on the back before ^ C page) • Send ·, -β This paper size applies to China National Standard (CNS) Α4 specification (210 × 297 mm) 403991 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Explanation of the invention () [Table 2] Gibbs free energy compound of each iodine i-containing gas compound at 427 ° C Gibbs free energy (kJ / mol) Gibbs free energy (kJ / mol) Compound Gibbs free energy (kJ / mol) Thl4 -512 Zrl4 -409 Til4 -320 Α ^ Ιό -510 Hfl4 -405 Pbl4 -266 K2I2 -480 Dyl ^ -402 Mgl2 -239 Lal3 -457 ΤΠΙΙ3 -399 Cul -237 ΠΠ3 -448 Gdh -388 Csl -220 Cel3 -442 Bal2 -380 Tal5 -202 Ndl3 -438 UI4 -377 Sil4 -150 Li2I2 -427 Srl2 -353 HI -11.8 Erl3 -410 Cal2 -338 •-[Table 3] Gibbs from S 1 bromine-containing Br gas compounds at 427 ° C from E White Energy-Compound Gibbs Free Energy (kJ / mol) Compound Gibbs Free Energy (kJ / mol) Compound Gibbs Free Energy (kJ / mol) Α12Βγ6 -860 HoBr3 -567 CaBr2 -435 Mg2Br4 -764 ΕγΒγ3 -566 PbBr4 -428 ThBr4 -743 TmBr 3 -563 TaBrs -424 HfBr4 -639 TbBr3 -559 EuBr2 -413 ZrBr4 -627 DyBr3 -559 SiBr4 -387 LaBr3 -621 GdBr3 -551 CU3Br3 -187 CeBr3 -616 Li2Br2 -534 WBr6 -139 PrBr3 -612 TiBr4 -527 HBr- 58.6 UBr4 -602 Na2Br2 -510. _ NdBr3 -598 SrBr2 -453--15 (Please read the notes on the back before r_vv this page) This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm)- Outfit_

*1T 線 403991 A7* 1T line 403991 A7

B 五、發明説明（/)) [表4] 在427°C時之各福 1含氟(F)氣 體化合物的吉柏斯自由能 化合物 吉柏斯自 由能 (kJ/mol) 化合物 吉柏斯自 由能 (kJ/mol) 化合物 吉柏斯自 由能 (kJ/mol) AI2F6 -2439 HfF4 -1592 Li3F3 -1457 uf6 -1953 ZrF4 -1587 PrF3 -1231 TaF6 -1687 S2FlO -1581 AsF5 -1080 ThF4 -1687 SiF4 -1515 CuF2 -287.3 Mg2F4 -1624 wf6 -1513 HF -277.1 NbF5 -1607 TiF4 -1467 - - [表5]在427°C時之各種含鉑(Pt)氣體化合物的吉柏斯自由能 化合物 吉柏斯自 由能 (kJ/mol) 化合物 吉柏斯自 由能 (kJ/mol) 化合物 吉柏斯自 由能 (kJ/mol) PtCl2 -78.6 PtCl3 -105.9 PtCl4 -141.9 PtBr2 +29.2 PtBr3 +27.3 PtBr4 -38.2 Ptl4 +62.8 - - - - (請先閲讀背面之注意事項再f本頁) -8 最後，在步驟150中，諸如鈦、鉅、锆、給、鈷、鉬 、鎢、鎳或鉑等金屬層，藉著使用金屬鹵化物氣體之取代 法形成後，一淸洩氣體被供給至腔室。在此，淸洩氣體的 供給時間與數量較形成犧牲金屬層之步驟與其他步驟中爲 多。因此，諸如吸附於絕緣膜而非犧牲金屬層等部份之 丁^^金屬鹵化物氣體，將被去吸附(desorb)並淸洩掉。 圖2A與2B係根據本發明之選擇性金屬層形成製程之 氣體流動圖，其中Y軸標示氣體的供給狀態，而X軸則標 示時間。圖2A係混合有氫氣(H2)與矽烷(Sm4)之淸洩氣體 16 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） Μ 經濟部中央揉準局員工消费合作社印策 403991_87___ 五、發明説明（β ) 被週期性地供給時的氣體流動圖。圖2B係淸洩氣體自啓 始即被連續供給之氣體流量圖。當淸洩氣體如圖2A所示 之週期性供給時，一淸洩氣體150恰於金屬鹵化物氣體被 供給後，其被以較長的時間與較大的數量供給，以避免金 屬鹵化物氣體被吸附於絕緣膜中，並自絕緣膜中充分使金 屬鹵化物氣體去吸附。爲更簡化，一淸洩氣體110首先被 供給，然後一犧牲金屬源氣體12〇被供給，以形成一犧牲 金屬層。當一淸洩氣體被週期性地供給時，一淸洩氣體 130被供給至腔室，以淸除殘留的犧牲金屬源氣體。再者 ，包含有要沉積之金屬的金屬鹵化物氣體被供給，而將一 犧牲金屬層以一沉積金屬層取代。此時，犧牲金屬鋁與鹵 素原子的化合物氣體仍殘留於腔室中，而此係再度藉由供 給淸洩氣體150至腔室而將其淸除至腔室外。此製程被設 定爲一個循環，而當該循環重複時，所沉積金屬的厚度將 可輕易地被控制，而梯級覆蓋的問題可被解決。 使用選擇件金靥層形成法形成半遵體裝置之電容器的 施 經濟部中央樣準局貝工消费合作社印製 (請先閱讀背面之注意事項再參^本頁) 圖3係舉例說明根據本發明之一種使用該選擇性金屬 層形成法而形成電容器之方法流程圖。 參考圖3，一諸如電晶體之較低結構係被形成，而一 做爲中間層介電質（ILD)的絕緣膜，係使用一層氧化物 膜或一層氧化物膜的複合物膜而形成。在步驟300中，暴 露出電晶體之源極區域的接觸孔，係藉著在絕緣膜上執行 光蝕印而形成。可隨意選擇地，在步驟310中，一歐姆層 ________ 17 本紙浪尺度適用中國國家棣準（CNS ) A4規格（210X Μ"/公釐） 經濟部中央標準局員工消费合作社印裝 403991 A7 B7 五、發明説明（/Ο 與阻障層可使用諸如鈦(Ti)或氮化鈦(TIN)等材料而形成， 以改良接觸孔與塡充材料之間的導電性，並避免擴散。其 次’一覆蓋在絕緣膜表面的導電層’係藉由使用較低電極 用之導電材料塡充接觸孔而形成’例如一諸如TiN之金屬 材料以及摻雜雜質的多晶砍。在此’摻雜於多晶矽中的雜 質最好具有氫端自由基’以允許一犧牲金屬層能被選擇性 地形成於後續的製程中。其次’在步驟32〇中’用做連接 至接觸孔的較低電極之導電層佈局圖案’係將導電層佈局 圖案化而形成。該導電層佈局圖案可於形成僅塡充接觸孔 內部的插塞層之後而形成；或藉由同時沉積與佈局圖案化 一導電層，以塡充接觸孔的內部而形成。在此，形成半球 形晶粒（HSG)於導電層佈局圖案上之步驟330，可被選 擇性地執行，以增加較低電極的表面積。其次，在步驟 340中，具有半球形晶粒的半導體基板被導入半導體製造 設備的腔室中，而一淸洩氣體將如圖2A與2B所示不斷地 或週期性地被供給。作爲犧牲金屬源氣體之DMAH ((CH3)2A1H)或 DMEAA ((CH3)2C2H5N:A1H3)被供給至腔室 中。然後，在步驟350中，爲鋁層之犧牲金屬層選擇性地 僅被形成於導電層上。在步驟360中，諸如TiCl4、氯化鉑 (Cl6H6Pt)或PtCl2等含有要沉積的金屬之金屬鹵化物氣體， 係被溶解於水(H20)或乙醇中然後汽化之，而蒸汽被供給以 使用取代法形成由鈦或鉑所組成的一沉積金屬層。其次， 在步驟365中，一矽化物層可藉由在沉積金屬層上進行一 道熱處理而被選擇性地形成。在步驟370中，一氮化物膜 本紙张尺度適用中國國家橾準（CNS ) A4規格（210X 297公釐） ^-n I I n .. I I I I I I I— n 訂 I I 線 (請先閲讀背面之注意事項再^本頁) _ 403991___B7____一 五、發明説明（Μ) 可使用氨氣電薬或快速熱氮化（rapid thermal nitridation， RTN)而被選擇性地形成。在步驟375中，一氧化物膜可藉 由在氧氣氛中執行一道熱處理而被選擇性地形成》其次， 氮化物膜與氧化物膜可被用爲電容器的介電膜。 在此，當Ti被用做第一層沉積金屬層時，則TiN係被 形成爲氮化物膜，而圖1所示之選擇性金屬層形成製程被 重複，因而於步驟373中形成由鉑所組成之第二層沉積金 屬層。步驟373係可隨意選擇的。 其後，在步驟380中，介電膜係被沉積於所得結構上 。該介電膜可爲一氧化物膜與氮化物膜的一複合物膜，或 可由Ta205、Ti02、Zr02、Al2〇3以及Nb205所組成的族群-中所選擇的一單原子金屬氧化物，諸如A1N之一單原子金 靥氮化物，或由 SrTi03 ' PZT (Pb(Zr，Ti)03)與 BST (BaSrTi03)所組成的族群中所選擇的一多原子金屬氧化物 所形成。最後，在步驟390中，一較高電極被形成於介電 膜形成其上的半導體基板上，其係使用多晶矽或諸如TiN 、TiAIN或TiSiN等金屬。 第一實施例 經濟部中央樣準局負工消费合作社印製 (請先閱讀背面之注意事項再^Γ本頁) 圖4A至4F係舉例說明根據本發明之第一個實施例， 使用選擇性金屬層形成法形成電容器之方法剖面圖。 參考圖4A，一諸如電晶體之較低結構（未表示於圖中 )係被形成於一半導體基板400上，而一層氧化物膜或一 .層氧化物膜的複合物膜係做爲中間層介電質（ILD) 402， 被形成於所得結構上。暴露出電晶體源極區域的接觸孔 __ _19__ 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X29*7公釐） 經濟部中央橾準局負工消费合作社印裝 403991_b7___ 五、發明説明（（Ί ) 404，係將中間層介電質4〇2佈局圖案化而形成。被摻雜以 雜質並具有氫端自由基的多晶矽，係被沉積於接觸孔404 形成其中的半導體基板上’且所沉積的多晶矽被佈局圖案 化，因而形成一連接至接觸孔的較低電極導電層佈局圖案 406。 參考圖4B，一諸如鈦或鉑之沉積金屬層408，係使用 如圖1所示之選擇性金屬層沉積法而形成於所得結構上。 在此，一種用以形成半球形晶粒的方法將可在沉積金屬層 形成前，被選擇性地執行於導電層佈局圖案406上，以增 加電容器之較低電極的表面積。因此，根據本發明，由於 選擇性金屬層沉積，一金屬可於不將諸如HSG型較低電極 之較低電極佈局圖案化，而被沉積於HSG表面上。 參考圖4C，一氮化物膜410係藉由氮化法或使用氨氣 電漿(NH3電漿）的快速熱氮化法（RTN)，而被形成於沉 積金屬層408形成其上的半導體基板上。氮化物膜410可 避免在後續製程之介電膜被沉積時，劣化電容量的氧化現 象形成於較低電極與介電膜間的界面。 參考圖4D，一諸如氧化鈦(Ti02)之氧化物膜412，係 藉由執行一道在氧氣氛中的熱處理而形成於所得結構上。 氮化物膜410與氧化物膜412係可被用爲介電膜。 參考圖4E，介電膜414係使用由Ta205、Ti02、Zr02 、A1203以及Nb205所組成的族群中所選擇的一單原子金屬 氧化物，諸如A1N之一單原子金屬氮化物，或由SrTi03、 PZT (Pb(Zr，Ti)03)與BST (BaSrTi03)所組成的族群中所選 20 _ 本紙張尺度適用中國國家標準（CNS ) A4規格（210乂29*7公釐） ---------^------IX------^----------------- (請先閲讀背面之注意事項再本頁) ________________ - I ----- .— .— II ---H - --------- - - - 403991,._^_______ 五、發明説明（π ) 擇的一多原子金屬氧化物，而形成於所得表面上。 參考圖4F，一多晶矽或金屬之較高電極416，係被形 成於介電膜414形成其上之半導體基板上，因而形成具有 矽-絕緣體-金屬（SIM)或金屬-絕緣體-金屬（MIM)之結 構的半導體裝置電容器。 若半導體裝置之電容器係以上述之方法形成，則一光 蝕印製程將可省略，因爲較低電極被形成後之佈局圖案化 係非所需。特別地是，在具有HSG之較低電極上做佈局圖 案係非所需，所以較低電極可以金屬形成，而解決許多由 蝕刻所引起的問題。 第二實施例 圖5A至5F係舉例說明根據本發明之第二個實施例， 使用選擇性金屬層形成法以形成電容器之方法剖面圖。 因爲圖5A以及圖5B所示之製程係與第一實施例中所 示者相同，所以這些製程的說明將被省略以避免重複。在 此，爲可易於瞭解的緣故，參考數字與第一實施例中者相 當。 經濟部中央橾準局員工消費合作社印製 (請先閱讀背面之注意事項再本頁) 參考圖5C，一爲選擇性金屬層之沉積金屬層508，係 藉由在沉積金屬層508形成其上之半導體基板上執行矽化 ，而改變爲諸如TiSix的矽化物層510。 參考圖5D，一氮化物層512係使用氨氣電漿或執行快 速熱氮化，而被形成於矽化物層510形成其上之半導體基 板上。 參考圖5E，一介電膜514可被形成於氮化物膜510形 ___21___ 本紙伕尺度適用中國國家標準（CNS ) A4規格（2丨0X297公ϋ — 經濟部中央標準局貝工消费合作社印裝 403991_B7___ 五、發明説明（6) 成其上之半導體基板上。在此，介電膜514可爲一氧化物 膜與一氮化物膜之一複合物膜，或爲由Ta205、Ti02、 Zr02、Al2〇3以及Nb205所組成的族群中所選擇的—單原子 金屬氧化物’諸如A1N之一單原子金屬氮化物，或由 SrTi03、PZT (Pb(Zr，Ti)03)與 BST (BaSrTi03)所組成的族群 中所選擇的一多原子金屬氧化物所形成。 參考圖5F，一多晶矽或金屬之較高電極516係被形成 於介電膜形成其上之半導體基板上，因而形成SIM或MIM 結構的電容器。 第三窗施例 圖6A至6C係舉例說明根據本發明之第三個實施例， 使用選擇性金屬層形成法以形成電容器之方法的剖面圖。 本實施例可使用選擇性金屬層沉積製程二次，以避免 在一鉑膜被選擇性地沉積於電容器較低電極上方時，一高 阻抗矽化鉑(PtSix)之形成。 參考圖6A，一諸如電晶體之較低結構（未表示於圖中 )係被形成於一半導體基板600上方，而使用一氧化物膜 或一氧化物膜之複合物膜的中間層介電質（ILD) 602係被 形成於所得結構上。暴露出電晶體之源極區域的接觸孔， 係被形成於半導體基板600上。一塡充接觸孔之插塞層 604，係使用多晶矽而形成。連接至插塞層604之電容器較 低電極導電層的氮化鈦(TiN)，係以化學氣相沉積（CVD) 或物理氣相沉積做毯覆式沉積(blanket-deposited)。該電容 器較低電極導電層係做佈局圖案，以形成一電容器較低電 ___22 ___ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ^ I I I n I I I I I I II 訂H 線 • r - , : (請先閲讀背面之注意事項再填足本頁) 403991 經濟部中央標準局負工消費合作社印装 五、發明説明（N) 極導電膜佈局圖案606。其次，一鈾膜608係使用如圖1 所示之選擇性金屬層形成法而被形成於TiN導電膜佈局圖 案606之表面上。 爲鉑膜608所覆蓋之電容器較低電極導電膜佈局圖案 606，亦可藉由下列之經改良的方法形成。在暴露出電晶體 之源極區域的接觸孔形成後，用以塡充接觸孔之插塞層 604係由摻雜雜質且具有氫端自由基之多晶矽所形成。鈦 係藉由圖1之選擇性金屬層形成法，而被選擇性地沉積於 所暴露出之插塞層604的表面上，因而形成一平面型較低 電極導電膜佈局圖案606。該鈦導電膜佈局圖案606使用 氨氣電漿或快速熱氮化（RTN)進行氮化，以形成TiN於· 所得結構上。之後，鉑膜608係以圖1之選擇性金屬層形 成法而形成，因而形成由鈾膜所形成之電容器較低電極。 參考圖6B，一介電膜610係被沉積於鉑膜608上。在 此，介電膜610可爲一氧化物膜與一氮化物膜之一複合物 膜，或爲由Ta205、Ti02、Zr02、A1203以及Nb205所組成 的族群中所選擇的一單原子金屬氧化物，諸如AIN之一單 原子金屬氮化物，或由SrTi03、PZT (Pb(Zr,Ti)03)與BST (BaSrTi03)所組成的族群中所選擇的一多原子金屬氧化物 〇 參考圖6C，一電容器較高電極612係使用多晶矽或諸 如鉑等金屬，而被形成於介電膜610形成其上之半導體基 板上，因而使用根據本發明之第三實施例的選擇性金屬層 形成法，完成半導體裝置之電容器的形成。 23 ----------穿-- (請先閱讀背面之注意事項再πν本頁) -*B. V. Description of the invention (/)) [Table 4] Gibbs free energy compounds of fluorine (F) gas compounds at each temperature at 427 ° C Gibbs free energy (kJ / mol) compounds Gibbs Free Energy (kJ / mol) Compound Gibbs Free Energy (kJ / mol) AI2F6 -2439 HfF4 -1592 Li3F3 -1457 uf6 -1953 ZrF4 -1587 PrF3 -1231 TaF6 -1687 S2FlO -1581 AsF5 -1080 ThF4 -1687 SiF4- 1515 CuF2 -287.3 Mg2F4 -1624 wf6 -1513 HF -277.1 NbF5 -1607 TiF4 -1467--[Table 5] Gibbs free energy compounds of various platinum-containing (Pt) gas compounds at 427 ° C Gibbs free Energy (kJ / mol) Compound Gibbs Free Energy (kJ / mol) Compound Gibbs Free Energy (kJ / mol) PtCl2 -78.6 PtCl3 -105.9 PtCl4 -141.9 PtBr2 +29.2 PtBr3 +27.3 PtBr4 -38.2 Ptl4 +62.8- ---(Please read the notes on the back before f this page) -8 Finally, in step 150, metal layers such as titanium, giant, zirconium, cobalt, molybdenum, tungsten, nickel or platinum are used. After the metal halide gas substitution method is formed, a purge gas is supplied to the chamber. Here, the supply time and quantity of the purge gas are longer than those in the step of forming the sacrificial metal layer and other steps. Therefore, the metal halide gas, such as that adsorbed on the insulating film instead of the sacrificial metal layer, will be desorbed and released. 2A and 2B are gas flow diagrams of a selective metal layer forming process according to the present invention, in which a Y-axis indicates a gas supply state, and an X-axis indicates time. Figure 2A is a bleed gas mixed with hydrogen (H2) and silane (Sm4). 16 This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm). V. Description of the invention (β) Gas flow diagram when periodically supplied. Fig. 2B is a flow diagram of the gas continuously supplied from the beginning. When the bleed gas is periodically supplied as shown in FIG. 2A, a bleed gas 150 is supplied just after the metal halide gas is supplied, and it is supplied for a longer time and in a larger amount to avoid the metal halide gas. It is adsorbed in the insulating film, and sufficiently desorbs the metal halide gas from the insulating film. For simplicity, a purge gas 110 is supplied first, and then a sacrificial metal source gas 120 is supplied to form a sacrificial metal layer. When a purge gas is supplied periodically, a purge gas 130 is supplied to the chamber to eliminate the remaining sacrificial metal source gas. Furthermore, a metal halide gas containing the metal to be deposited is supplied, and a sacrificial metal layer is replaced with a deposited metal layer. At this time, the compound gas of the sacrificial metal aluminum and the halogen atom still remains in the chamber, and this is again purged out of the chamber by supplying the purge gas 150 to the chamber. This process is set as a cycle, and when the cycle is repeated, the thickness of the deposited metal can be easily controlled, and the problem of step coverage can be solved. Printed by the Central Prototype Bureau of the Ministry of Economic Affairs of the Ministry of Economics and the Ministry of Economics, using the optional gold layer formation method to print capacitors (read the precautions on the back before seeing this page). Figure 3 illustrates an example based on this A flowchart of a method for forming a capacitor using the selective metal layer forming method is invented. Referring to FIG. 3, a lower structure such as a transistor is formed, and an insulating film as an interlayer dielectric (ILD) is formed using an oxide film or a composite film of an oxide film. In step 300, the contact hole exposing the source region of the transistor is formed by performing photoetching on the insulating film. Optionally, in step 310, an ohmic layer ________ 17 The paper scale is applicable to China National Standards (CNS) A4 specifications (210X M " / mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 403991 A7 B7 5. Description of the invention (/ 0 and the barrier layer can be formed using materials such as titanium (Ti) or titanium nitride (TIN) to improve the conductivity between the contact hole and the filling material and avoid diffusion. Secondly, ' A conductive layer covering the surface of an insulating film is formed by filling a contact hole with a conductive material for a lower electrode, such as a metal material such as TiN and a polycrystalline chip doped with impurities. Impurities in polycrystalline silicon preferably have hydrogen-terminated radicals to allow a sacrificial metal layer to be selectively formed in subsequent processes. Secondly, in step 32, it is used as the conductivity of the lower electrode connected to the contact hole. The layer layout pattern is formed by patterning a conductive layer layout. The conductive layer layout pattern can be formed after forming a plug layer that only fills the inside of the contact hole; or patterning a conductive layer by simultaneously depositing and layout Is formed by filling the inside of the contact hole. Here, the step 330 of forming hemispherical grains (HSG) on the conductive layer layout pattern can be selectively performed to increase the surface area of the lower electrode. Second, in In step 340, the semiconductor substrate having hemispherical grains is introduced into the chamber of the semiconductor manufacturing equipment, and a purge gas is continuously or periodically supplied as shown in FIGS. 2A and 2B. As a sacrificial metal source gas, DMAH ((CH3) 2A1H) or DMEAA ((CH3) 2C2H5N: A1H3) is supplied into the chamber. Then, in step 350, a sacrificial metal layer, which is an aluminum layer, is selectively formed only on the conductive layer. In In step 360, a metal halide gas such as TiCl4, platinum chloride (Cl6H6Pt), or PtCl2 containing the metal to be deposited is dissolved in water (H20) or ethanol and then vaporized, and the steam is supplied to use the substitution method A deposited metal layer composed of titanium or platinum is formed. Second, in step 365, a silicide layer may be selectively formed by performing a heat treatment on the deposited metal layer. In step 370, a nitride is formed. Film paper size Applicable to China National Standard (CNS) A4 specification (210X 297mm) ^ -n II n .. IIIIIII— n order II line (please read the precautions on the back before ^ this page) _ 403991___B7____15 Description of the invention (M) can be selectively formed using ammonia gas electrolysis or rapid thermal nitridation (RTN). In step 375, an oxide film can be selected by performing a heat treatment in an oxygen atmosphere. "Naturally formed" Secondly, the nitride film and the oxide film can be used as a dielectric film of a capacitor. Here, when Ti is used as the first deposited metal layer, the TiN system is formed as a nitride film, and the selective metal layer forming process shown in FIG. 1 is repeated. Therefore, in step 373, a platinum layer is formed. A second layer consisting of a deposited metal layer. Step 373 is optional. Thereafter, in step 380, a dielectric film is deposited on the resulting structure. The dielectric film may be a composite film of an oxide film and a nitride film, or a monoatomic metal oxide selected from the group consisting of Ta205, Ti02, Zr02, Al203 and Nb205, such as A1N is a monoatomic gold hafnium nitride or a polyatomic metal oxide selected from the group consisting of SrTi03 'PZT (Pb (Zr, Ti) 03) and BST (BaSrTi03). Finally, in step 390, a higher electrode is formed on the semiconductor substrate on which the dielectric film is formed, using polycrystalline silicon or a metal such as TiN, TiAIN, or TiSiN. First Embodiment Printed by the Central Procurement Bureau of the Ministry of Economic Affairs and Consumer Cooperatives (please read the precautions on the back before this page) Figures 4A to 4F illustrate the first embodiment of the present invention, using selective Sectional view of a method for forming a capacitor by a metal layer forming method. Referring to FIG. 4A, a lower structure (not shown) such as a transistor is formed on a semiconductor substrate 400, and an oxide film or a composite film of an oxide film is used as an intermediate layer. A dielectric (ILD) 402 is formed on the resulting structure. The contact hole in the source region of the transistor is exposed __ _19__ This paper size is applicable to China National Standard (CNS) A4 (210X29 * 7 mm) Printed on the Office of the Central Government Standards Bureau, Ministry of Economic Affairs and Consumer Cooperatives 403991_b7___ 5. Description of the invention ((Ί) 404 is formed by patterning the interlayer dielectric 402 layout. Polycrystalline silicon doped with impurities and having hydrogen terminal radicals is deposited on the semiconductor substrate in which the contact hole 404 is formed ' And the deposited polycrystalline silicon is patterned, thereby forming a lower electrode conductive layer layout pattern 406 connected to the contact hole. Referring to FIG. 4B, a deposited metal layer 408 such as titanium or platinum is used as shown in FIG. A selective metal layer deposition method is formed on the resulting structure. Here, a method for forming hemispherical grains can be selectively performed on the conductive layer layout pattern 406 before the formation of the deposited metal layer to increase Surface area of the lower electrode of the capacitor. Therefore, according to the present invention, due to the selective metal layer deposition, a metal can be used without patterning a lower electrode layout such as an HSG type lower electrode It is deposited on the surface of HSG. Referring to FIG. 4C, a nitride film 410 is formed on the deposited metal by a nitriding method or a rapid thermal nitriding method (RTN) using an ammonia plasma (NH3 plasma). A layer 408 is formed on the semiconductor substrate thereon. The nitride film 410 can prevent the oxidation phenomenon that deteriorates the capacitance from being formed at the interface between the lower electrode and the dielectric film when the dielectric film is deposited in a subsequent process. Referring to FIG. 4D, An oxide film 412, such as titanium oxide (Ti02), is formed on the resulting structure by performing a heat treatment in an oxygen atmosphere. The nitride film 410 and the oxide film 412 can be used as a dielectric film. Reference 4E, the dielectric film 414 is a monoatomic metal oxide selected from the group consisting of Ta205, Ti02, Zr02, A1203, and Nb205, such as a monoatomic metal nitride of A1N, or SrTi03, PZT ( Pb (Zr, Ti) 03) and BST (BaSrTi03) selected from the group of 20 _ This paper size applies to China National Standard (CNS) A4 size (210 乂 29 * 7mm) ------- -^ ------ IX ------ ^ ----------------- (Please read the notes on the back before this page) ________________-I ----- .— .— II --- H-------------403991, ._ ^ _______ V. Description of the invention (π) Selective polyatomic metal oxidation 4F, a polycrystalline silicon or metal higher electrode 416 is formed on a semiconductor substrate on which a dielectric film 414 is formed, thereby forming a silicon-insulator-metal (SIM) Or metal-insulator-metal (MIM) semiconductor device capacitors. If the capacitor of the semiconductor device is formed by the above method, a photolithography process can be omitted because the patterning of the layout after the lower electrode is formed is not required. In particular, it is not necessary to make a layout pattern on the lower electrode with HSG, so the lower electrode can be formed of metal, and it solves many problems caused by etching. Second Embodiment FIGS. 5A to 5F are cross-sectional views illustrating a method for forming a capacitor using a selective metal layer forming method according to a second embodiment of the present invention. Since the processes shown in Figs. 5A and 5B are the same as those shown in the first embodiment, the description of these processes will be omitted to avoid repetition. Here, for ease of understanding, the reference numerals correspond to those in the first embodiment. Printed by the Consumer Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs (please read the precautions on the back and then this page). Refer to Figure 5C, a selective metal layer is deposited on the metal layer 508, which is formed on the deposited metal layer 508 The silicon substrate is subjected to silicidation and changed to a silicide layer 510 such as TiSix. Referring to FIG. 5D, a nitride layer 512 is formed on a semiconductor substrate on which a silicide layer 510 is formed using an ammonia gas plasma or performing rapid thermal nitridation. Referring to FIG. 5E, a dielectric film 514 can be formed in the shape of a nitride film 510. ___21___ This paper is compliant with the Chinese National Standard (CNS) A4 specification (2 丨 0X297 cm) — printed by the Central Laboratories of the Ministry of Economic Affairs, Shellfish Consumer Cooperative. 403991_B7___ 5. Description of the invention (6) on a semiconductor substrate formed thereon. Here, the dielectric film 514 may be a composite film of an oxide film and a nitride film, or a film composed of Ta205, Ti02, Zr02, Al2 〇3 and selected from the group consisting of Nb205-monoatomic metal oxides such as a monoatomic metal nitride of A1N, or composed of SrTi03, PZT (Pb (Zr, Ti) 03) and BST (BaSrTi03) 5F, a polycrystalline silicon or metal higher electrode 516 is formed on a semiconductor substrate on which a dielectric film is formed, thereby forming a SIM or MIM structure. Capacitor. Third Window Embodiment FIGS. 6A to 6C are cross-sectional views illustrating a method for forming a capacitor using a selective metal layer forming method according to a third embodiment of the present invention. This embodiment may use selective metal layer deposition. system The process is repeated twice to avoid the formation of a high-resistance platinum silicide (PtSix) when a platinum film is selectively deposited over the lower electrode of the capacitor. Referring to FIG. 6A, a lower structure such as a transistor (not shown in FIG. (In the figure) is formed over a semiconductor substrate 600, and an interlayer dielectric (ILD) 602 using an oxide film or a composite film of an oxide film is formed on the resulting structure. The transistor is exposed. The contact hole in the source region is formed on the semiconductor substrate 600. A plug layer 604 filling the contact hole is formed using polycrystalline silicon. Nitriding of the lower electrode conductive layer of the capacitor connected to the plug layer 604 Titanium (TiN) is blanket-deposited by chemical vapor deposition (CVD) or physical vapor deposition. The conductive layer of the lower electrode of the capacitor is used as a layout pattern to form a capacitor with a lower power. __22 ___ This paper size applies Chinese National Standard (CNS) A4 (210X297mm) ^ III n IIIIII II H line • r-,: (Please read the notes on the back before filling this page) 403991 Central of the Ministry of Economic Affairs Standard negative 5. Printed by a consumer cooperative. 5. Description of the invention (N) conductive film layout pattern 606. Second, a uranium film 608 is formed on the surface of the TiN conductive film layout pattern 606 using the selective metal layer formation method shown in FIG. 1. The conductive film layout pattern 606 for the lower electrode of the capacitor covered by the platinum film 608 can also be formed by the following improved method. After the contact hole that exposes the source region of the transistor is formed, it is used for charging The plug layer 604 of the contact hole is formed of polycrystalline silicon doped with impurities and having hydrogen terminal radicals. Titanium is selectively deposited on the surface of the exposed plug layer 604 by the selective metal layer forming method of FIG. 1, thereby forming a flat lower conductive film layout pattern 606. The titanium conductive film layout pattern 606 is nitrided using an ammonia gas plasma or rapid thermal nitridation (RTN) to form TiN on the resulting structure. Thereafter, the platinum film 608 is formed by the selective metal layer forming method shown in FIG. 1, thereby forming a capacitor lower electrode formed of a uranium film. Referring to FIG. 6B, a dielectric film 610 is deposited on the platinum film 608. Here, the dielectric film 610 may be a composite film of an oxide film and a nitride film, or a monoatomic metal oxide selected from the group consisting of Ta205, Ti02, Zr02, A1203, and Nb205. A monoatomic metal nitride such as AIN, or a polyatomic metal oxide selected from the group consisting of SrTi03, PZT (Pb (Zr, Ti) 03) and BST (BaSrTi03). Referring to FIG. 6C, a The capacitor higher electrode 612 is formed on a semiconductor substrate on which a dielectric film 610 is formed using polycrystalline silicon or a metal such as platinum. Therefore, the selective metal layer forming method according to the third embodiment of the present invention is used to complete the semiconductor. Formation of device capacitors. 23 ---------- Wear-(Please read the precautions on the back before πν this page)-*

I 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 經濟部中央標準局貝工消费合作社印製 403991_ b7___ 五、發明説明（y) 使用潠擇件金鼷層形成法之接觸孔塡充法 圖7係圖示根據本發明之使用選擇性金屬層形成法塡 充接觸孔之方法流程圖。 參考圖7，在步驟700中，使用中間層介電質（ILD) ，一絕緣膜係被沉積於諸如電晶體位元線等較低結構形成 其上之半導體基板上，且暴露出較低膜之接觸孔係藉由將 中間層介電質佈局圖案化而形成。在此，該ILD係一層氧 化物膜或一層氧化物膜之複合物膜，而該較低膜係由氮化 鈦或摻雜雜質並具有氫端的多晶矽所組成。此將允許來自 犧牲金屬源氣體之犧牲金屬在後續製程中的較低膜上選擇 性沉積。再者，該接觸孔可爲直接連接至半導體基板之電 容器較低電極接觸孔，或一金屬接觸孔。其次，在步驟 710、720以及730中，一諸如鈦(Ti)等材料之沉積金屬層 係使用圖1所示之選擇性金屬層形成法，而被形成於接觸 孔底部上。在塡充接觸孔之製程中，由諸如鈦(Ti)等導電 材料所形成之沉積金屬層係被使用爲歐姆層。其次，在步 驟740中，一諸如氮化鈦(TiN)的阻障層，係藉由RTN或 使用氨氣電漿之氮化法，而可選擇地形成於爲沉積金屬層 之歐姆層上。在步驟750中，一插塞層係由位於阻障層上 的鋁(A1)以及鎢(W)所形成。在步驟760中，一連接至插塞 層的導電層被形成，因而完成接觸孔的塡充。在此，在無 特別形成插塞層的情況下，一用以塡充接觸孔的導電層可 被直接地形成於阻障層或歐姆層上。 在步驟740中，該阻障層可藉由毯覆式化學氣相沉積 _24__ 冢紙張尺度適用中ΪΪ家標準（CNS ) A4規格（210X297公釐） — .— I— II 訂 線 (請先閲讀背面之注意事項再本頁) · 403991 A7 _____B7 五、發明説明（θ) 或濺鍍法形成，並做佈局圖案，而非以RTN或使用氨氣電 漿之氮化法爲之。 第四窨施例 圖8A至8E係舉例說明根據本發明之第四個實施例， 使用選擇性金屬層形成法的接觸孔塡充法之剖面圖。 參考圖8A，一諸如氧化物膜或氧化物膜之複合物膜的 絕緣膜802，係被形成於一半導體基板80〇上，且一暴露 出較低膜的接觸孔804，係藉由將絕緣膜8〇2佈局圖案化 而形成。在此’接觸孔804可以是連接至半導體基板的電 容器較低電極接觸孔，或形成於金屬交互連結製程中的金 屬接觸孔。 參考圖8B ’ 一諸如鈦(Ti)等材料之沉積金屬層，係使 用圖1之選擇性金屬層形成法而被形成於接觸孔804形成 其上的半導體基板上。該沉積金屬層作爲在塡充接觸孔的 製程中，用以改良較低膜與塡充接觸孔之導電材料間之導 電性的歐姆層806。 經濟部中央橾準局貝工消费合作社印裝 (請先閲讀背面之注意事項再填X本頁) 參考圖8C，一諸如氮化鈦(TiN)層之避免雜質擴散的 阻障層808，係可選擇地被形成於歐姆層806沉積其上的 半導體基板上。該阻障層可藉由使用氨氣電漿的氮化法、 RTN或毯覆式沉積而形成。 參考圖8D，在塡充接觸孔時，覆蓋半導體基板表面之 一導電層810,係被沉積於阻障層808形成其上的半導體 基板上，因而完成使用根據本發明之第四實施例之選擇性 金屬層形成法之接觸孔塡充製程。 _ _25_ 本紙張尺度適用中國國家標準（CNS ) A4規格ΰΐ〇Χ297公釐) ^ 403991___B7 五、發明説明（>]) ' 圖8E係圖8D之改良的剖面圖。在此，—插塞層812 係由位於阻障層808形成其上的半導體基板上之鎢(w)或 鋁(A1)所形成。其次，該插塞層812係藉由回蝕或化學機 械拋光（CMP)，而將除了接觸孔內部以外的區域移除。 該導電層810然後被形成與插塞層812接觸。 因此，根據本發明，一相對爲薄的歐姆層可在500。〇 或更低的溫度下被形成於具有高的高寬比之接觸孔內，且 無剝離或侵蝕之問題。此舉使得無須一道諸如回蝕製程之 用以控制歐姆層厚度的製程。 根據如上述之本發明’因爲一諸如鈦(Ti)或鉑（pt)等 材料之金屬層，係於500°C或更低的溫度下被選擇性地形 成’所以在形成半導體裝置之電容器的製程中，一較低電 極將可輕易地以金屬而非多晶砂來形成。因此，當較低電 極由鈦或鉑形成時，產生於先前技術中的許多問題將可被 解決。再者，在用以形成一歐姆層於接觸孔底部上的製程 中’具有適當厚度的歐姆層係於低溫下僅被選擇性地形成 於接觸孔的底部，因而塡充該接觸孔，而同時避免諸如剝 離或侵蝕等缺陷》 本發明並非爲上述之實施例所限制，並且淸楚地是在 本發明之技術精神內的各種改良係可爲熟習本技藝之人士 所爲之。 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χ 297公釐）I This paper size applies to Chinese National Standard (CNS) A4 specification (210 × 297 mm) Printed by Shellfish Consumer Cooperative of Central Standards Bureau of the Ministry of Economic Affairs 403991_ b7___ V. Description of the invention (y) Contact hole using the optional gold layer method Filling Method FIG. 7 is a flowchart illustrating a method of filling a contact hole using a selective metal layer forming method according to the present invention. Referring to FIG. 7, in step 700, using an interlayer dielectric (ILD), an insulating film is deposited on a semiconductor substrate having a lower structure such as a transistor bit line formed thereon, and the lower film is exposed. The contact holes are formed by patterning the interlayer dielectric layout. Here, the ILD is an oxide film or a composite film of an oxide film, and the lower film is composed of titanium nitride or polycrystalline silicon doped with impurities and having a hydrogen terminal. This will allow the sacrificial metal from the sacrificial metal source gas to be selectively deposited on lower films in subsequent processes. Furthermore, the contact hole may be a lower electrode contact hole of a capacitor directly connected to a semiconductor substrate, or a metal contact hole. Next, in steps 710, 720, and 730, a deposited metal layer such as titanium (Ti) is formed on the bottom of the contact hole using the selective metal layer forming method shown in FIG. In the process of filling a contact hole, a deposited metal layer formed of a conductive material such as titanium (Ti) is used as an ohmic layer. Second, in step 740, a barrier layer such as titanium nitride (TiN) is selectively formed on the ohmic layer for depositing a metal layer by RTN or a nitriding method using an ammonia plasma. In step 750, a plug layer is formed of aluminum (A1) and tungsten (W) on the barrier layer. In step 760, a conductive layer connected to the plug layer is formed, thereby filling the contact hole. Here, without forming a plug layer in particular, a conductive layer for filling the contact hole can be directly formed on the barrier layer or the ohmic layer. In step 740, the barrier layer can be applied by blanket chemical vapor deposition _24__ gravel paper scale to apply the China Standard (CNS) A4 specification (210X297 mm) —. — I — II order (please first (Please read the notes on the back page) 403991 A7 _____B7 V. Description of the invention (θ) or sputtering method, and layout pattern, not RTN or nitriding method using ammonia plasma. Fourth Embodiment Example FIGS. 8A to 8E are cross-sectional views illustrating a contact hole filling method using a selective metal layer forming method according to a fourth embodiment of the present invention. Referring to FIG. 8A, an insulating film 802 such as an oxide film or a composite film of an oxide film is formed on a semiconductor substrate 80 and a contact hole 804 exposing a lower film is formed by insulating the The film 802 is formed by patterning the layout. Here, the 'contact hole 804 may be a lower electrode contact hole of a capacitor connected to a semiconductor substrate, or a metal contact hole formed in a metal interconnection process. Referring to FIG. 8B ', a deposited metal layer of a material such as titanium (Ti) is formed on the semiconductor substrate on which the contact hole 804 is formed using the selective metal layer forming method of FIG. The deposited metal layer is used as an ohmic layer 806 to improve the conductivity between the lower film and the conductive material of the pseudo-filled contact hole in the process of the pseudo-filled contact hole. Printed by the Central Laboratories of the Ministry of Economic Affairs, Shellfish Consumer Cooperative (please read the precautions on the back before filling the X page). Referring to FIG. 8C, a barrier layer 808, such as a titanium nitride (TiN) layer, to prevent impurity diffusion Optionally formed on a semiconductor substrate on which the ohmic layer 806 is deposited. The barrier layer may be formed by a nitriding method using an ammonia gas plasma, RTN, or blanket deposition. Referring to FIG. 8D, when a contact hole is filled, a conductive layer 810 covering the surface of the semiconductor substrate is deposited on the semiconductor substrate on which the barrier layer 808 is formed, and thus the selection according to the fourth embodiment of the present invention is completed. The filling process of the contact hole is performed by the method of forming a flexible metal layer. _ _25_ This paper size applies Chinese National Standard (CNS) A4 (297 × 297 mm) ^ 403991___B7 V. Description of the invention (>]) 'Figure 8E is a modified sectional view of Figure 8D. Here, the plug layer 812 is formed of tungsten (w) or aluminum (A1) on a semiconductor substrate on which the barrier layer 808 is formed. Second, the plug layer 812 removes areas other than the inside of the contact hole by etch back or chemical mechanical polishing (CMP). This conductive layer 810 is then formed in contact with the plug layer 812. Therefore, according to the present invention, a relatively thin ohmic layer may be 500 Å. It is formed in contact holes having a high aspect ratio at a temperature of 〇 or lower, without problems of peeling or erosion. This eliminates the need for a process such as an etch-back process to control the thickness of the ohmic layer. According to the present invention as described above, 'Because a metal layer of a material such as titanium (Ti) or platinum (pt) is selectively formed at a temperature of 500 ° C or lower', In the manufacturing process, a lower electrode can easily be formed from metal instead of polycrystalline sand. Therefore, when the lower electrode is formed of titanium or platinum, many problems arising from the prior art can be solved. Furthermore, in the process for forming an ohmic layer on the bottom of the contact hole, an ohmic layer having an appropriate thickness is only selectively formed on the bottom of the contact hole at a low temperature, so the contact hole is filled while simultaneously Avoiding Defects such as Peeling or Erosion "The present invention is not limited to the above-mentioned embodiments, and it is clear that various improvements within the technical spirit of the present invention can be made by those skilled in the art. This paper size is applicable to China National Standard (CNS) A4 (210 × 297 mm)

Claims (1)

403991 申請專利範i403991 Patent application 經濟部t央揉牟局男工消費合作社印製 1.一種選擇性金屬層形成法，包括的步驟爲： 將一絕緣膜與一導電層形成其上之半導體基板置入腔 室中’並供給一淸洩氣體至腔室中； 藉由提供對於絕緣膜與導電層乃選擇性沉積之犧牲金 屬源氣體至腔室中，而將犧牲金屬層僅形成於導電層上； 以及 藉由供給具有鹵素親和力較犧牲金屬層中之金屬原子 的鹵素親和力爲低之金屬鹵化物氣體至腔室，而以一沉積 金屬層取代該犧牲金屬層。 2·如申請專利範圍第1項之選擇性金屬層形成法，其 中該絕緣膜爲氧化物膜(Si02)或含有氧化物膜之複合物膜 〇 3·如申請專利範圍第1項之選擇性金屬層形成法，其 中該導電層爲以雜質摻雜之矽或金屬所形成。 4. 如申請專利範圍第3項之選擇性金屬層形成法，其 中以雜質摻雜之矽具有氫端自由基。 5. 如申請專利範圍第3項之選擇性金屬層形成法，其 中該金屬爲TiN。 6. 如申請專利範圍第1項之選擇性金屬層形成法，其 中該淸洩氣體係氫氣與矽烷之混合物。 7. 如申請專利範圍第1項之選擇性金屬層形成法，其 中該淸洩氣體不斷地被供給，或者先供給一預定量以做淸 ί曳’並且週期性地以預定的量供給於犧牲金屬層被形成並 爲沉積金屬層取代之後。 本紙張尺度逋用中國國家標隼（CNS > M規格（2丨〇><297公釐） I n I I ^—1 II —訂 II 線 -' (請先閱讀背面之注意事項再t本買) Λ8 B8 C8 D8 403991 夂' 申請專利範圍 8. 一種使用選擇性金屬層形成法來形成半導體裝置之 電容器的方法，包括的步驟爲： (a) 形成一曝露出半導體基板源極區的接觸孔，其係藉 由形成一絕緣膜於半導體基板上並將該絕緣膜佈局圖案化 而得： (b) 形成一塡充該接觸孔並覆蓋該絕緣膜之導電層； (c) 形成一連結至接觸孔的導電層佈局圖案，其係藉由 加工該導電層而得； (d) 將該半導體基板置入腔室中，且將淸洩氣體供給至 腔室中； (e) 將一犧牲金屬層僅形成於導電層上，其係藉著將對 於絕緣膜與導電層乃選擇性沉積的犧牲金屬源氣體供給至 腔室中而得； (f) 藉由供給具有鹵素親和力較犧牲金屬層中之金屬原 子的鹵素親和力爲低之金屬鹵化物氣體至腔室，而以一沉 積金屬層取代該犧牲金屬層； (g) 形成一介電膜於沉積金屬層上；以及 (h) 形成一較高電極於該介電膜上。 9. 如申請專利範圍第8項之使用選擇性金屬層形成法 來形成半導體裝置之電容器的方法’其中該絕緣膜爲氧化 物膜(Si〇2)或含有氧化物膜之複合物膜。 10. 如申請專利範圍第8項之使用選擇性金屬層形成法 來形成半導體裝置之電容器的方法’其中步驟(b)中之導電 層由雜質摻雜之多晶矽或氮化鈦(TiN)所形成。 2 本紙張尺度適用中國國家標準（CNS〉A4規格（210X297公釐） ---------^------iT------.^ (請先閲讀背面之注意事項再v纟•本頁) ' 經濟部中央橾率局貝工消費合作社印製 403991 Λ8 B8 C8 D8 經濟部中央梂準局貞工消费合作社印製 六、申請專利範圍 11.如申請專利範圍第10項之使用選擇性金屬層形成 法來形成半導體裝置之電容器的方法，其中以雜質摻雜之 多晶矽具有氫端自由基。 12·如申請專利範圍第8項之使用選擇性金屬層形成法 來形成半導體裝置之電容器的方法，其中步驟(d)中之淸洩 氣體係氫氣(Hi)與砂院(SiH4)之混合物。 13.如申請專利範圍第8項之使用選擇性金屬層形成法 來形成半導體裝置之電容器的方法，其中步驟(d)中之淸洩 氣體係不斷地被供給，或者先供給一預定量以做清洩，並 且被週期性地以預定的量供給於犧牲金屬層被形成並爲沉 積金屬層取代之後。 14_如申請專利範圍第8項之使用選擇性金屬層形成法 來形成半導體裝置之電容器的方法，進一步包括在形成沉 積金屬層之步驟(f)後，將沉積金屬層矽化的步驟。 15. —種使用選擇性金屬層形成法塡充接觸孔的方法， 包括的步驟爲： (1) 形成一絕緣膜於半導體基板上，並藉由將該絕緣膜 佈局圖案化而形成一暴露出較低膜之接觸孔； (2) 將接觸孔形成其上之半導體基板置入腔室中，且將 淸洩氣體供給至腔室中； (3) 將一犧牲金屬層僅形成於較低膜上，其係藉由將對 於絕緣膜與較低膜乃選擇性沉積的犧牲金屬源氣體供給至 腔室中而得； (4) 藉由供給具有鹵素親和力較犧牲金屬層中之金屬原 _ 3 (請先閲讀背面之注意事項再爽寫本頁) t 丁 % 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標隼局貞工消费合作社印簟 Λ 8 . Βδ 403991___S_ 六、申請專利範圍 子的鹵素親和力爲低之金屬鹵化物氣體至腔室，而以一沉 積金屬層取代該犧牲金屬層；以及 (5)形成一塡充接觸孔的導電層。 16. 如申請專利範圍第15項之使用選擇性金屬層形成 法塡充接觸孔之方法，其中步驟（1)中之絕緣膜爲氧化物膜 (Si02)或含有氧化物膜之複合物膜。 17. 如申請專利範圍第15項之使用選擇性金屬層形成 法塡充接觸孔之方法，其中步驟（1)中之較低膜，係以雜質 摻雜並具有氫端自由基之矽或氮化鈦(TiN)所形成。 18·如申請專利範圍第I5項之使用選擇性金屬層形成 法塡充接觸孔之方法，其中步驟(2)中之淸洩氣體係氫氣 (H2)與矽烷(SiH4)之混合物。 19. 如申請專利範圍第15項之使用選擇性金屬層形成 法塡充接觸孔之方法，其中步驟(2)中之淸洩氣體係不斷地 被供給，或者先供給一預定量以做淸洩，並且被週期性地 以預定的量供給於犧牲金屬層被形成並爲沉積金屬層取代 之後。 20. 如申請專利範圍第15項之使用選擇性金屬層形成 法塡充接觸孔之方法，進一步包括在以沉積金屬層取代犧 牲金屬層之步驟(4)之後，將一阻障層形成於沉積金屬層上 的步驟。 _ 4 本紙張AA逋用中家樣準（CNS ) A4J^ ( 210X297公# ) I— i I I I .1T線 . _ (請先閱讀背面之注意事項再續1本頁)Printed by the Men ’s Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs 1. A selective metal layer forming method includes the steps of: placing an insulating film and a semiconductor substrate on which a conductive layer is formed into a chamber, and supplying the same Bleed gas into the chamber; by providing a sacrificial metal source gas which is selectively deposited for the insulating film and the conductive layer into the chamber, the sacrificial metal layer is formed only on the conductive layer; and by supplying a halogen A metal halide gas having a lower affinity than a halogen atom of a metal atom in the sacrificial metal layer is introduced into the chamber, and the sacrificial metal layer is replaced by a deposited metal layer. 2. The selective metal layer forming method according to item 1 of the scope of patent application, wherein the insulating film is an oxide film (Si02) or a composite film containing an oxide film. 03. The selectivity according to item 1 of the scope of patent application A metal layer forming method, wherein the conductive layer is formed of silicon or metal doped with impurities. 4. The selective metal layer forming method according to item 3 of the patent application, wherein the impurity-doped silicon has hydrogen terminal radicals. 5. The selective metal layer forming method according to item 3 of the patent application, wherein the metal is TiN. 6. The selective metal layer forming method according to item 1 of the patent application scope, wherein the tritium gassing system is a mixture of hydrogen and silane. 7. The selective metal layer forming method according to the scope of patent application, wherein the bleed gas is continuously supplied, or a predetermined amount is first supplied to be used for sacrifice, and the sacrificial gas is periodically supplied to the sacrifice in a predetermined amount. After the metal layer is formed and replaced by a deposited metal layer. This paper uses Chinese National Standards (CNS > M Specifications (2 丨 〇 > < 297mm) I n II ^ —1 II —Order II Line- '(Please read the precautions on the back before t (Buy this) Λ8 B8 C8 D8 403991 夂 'Application for patent scope 8. A method for forming a capacitor of a semiconductor device using a selective metal layer formation method, comprising the steps of: (a) forming a semiconductor substrate which exposes a source region of a semiconductor substrate A contact hole is obtained by forming an insulating film on a semiconductor substrate and patterning the layout of the insulating film: (b) forming a conductive layer filling the contact hole and covering the insulating film; (c) forming a The layout pattern of the conductive layer connected to the contact hole is obtained by processing the conductive layer; (d) placing the semiconductor substrate into the chamber, and supplying bleed gas into the chamber; (e) placing a The sacrificial metal layer is formed only on the conductive layer, which is obtained by supplying a sacrificial metal source gas that is selectively deposited for the insulating film and the conductive layer into the chamber; (f) by supplying a sacrificial metal having a halogen affinity Halogen atom of metal atom in layer A metal halide gas having a low force to the chamber, and the sacrificial metal layer is replaced by a deposited metal layer; (g) forming a dielectric film on the deposited metal layer; and (h) forming a higher electrode on the dielectric 9. A method for forming a capacitor of a semiconductor device using a selective metal layer formation method as described in item 8 of the scope of the patent application, wherein the insulating film is an oxide film (SiO2) or a compound containing an oxide film. 10. A method for forming a capacitor of a semiconductor device using a selective metal layer formation method as described in item 8 of the scope of patent application, wherein the conductive layer in step (b) is polycrystalline silicon or titanium nitride (TiN) doped with impurities. ). 2 This paper size applies to Chinese national standards (CNS> A4 size (210X297 mm) --------- ^ ------ iT ------. ^ (Please first (Please read the notes on the back again v 再 this page) '' Printed by the Central Labor Department of the Ministry of Economic Affairs, printed by the Shellfish Consumer Cooperative 403991 Λ8 B8 C8 D8 Formed using the selective metal layer formation method in the scope of patent application No. 10 A method for a capacitor of a semiconductor device, wherein polycrystalline silicon doped with an impurity has a hydrogen terminal radical. 12. A method for forming a capacitor of a semiconductor device using a selective metal layer forming method as described in item 8 of the patent application, wherein step (d ), A mixture of hydrogen (Hi) and sand (SiH4) in the purge gas system. 13. A method for forming a capacitor of a semiconductor device using a selective metal layer forming method as described in item 8 of the patent application, wherein step (d) The Zhongzhi purge gas system is continuously supplied, or a predetermined amount is first supplied for purge, and is periodically supplied in a predetermined amount after the sacrificial metal layer is formed and replaced by the deposited metal layer. 14_ The method for forming a capacitor of a semiconductor device using the selective metal layer forming method according to item 8 of the patent application scope, further comprising a step of silicifying the deposited metal layer after the step (f) of forming the deposited metal layer. 15. A method of filling a contact hole using a selective metal layer forming method, comprising the steps of: (1) forming an insulating film on a semiconductor substrate, and forming an exposed film by patterning the insulating film layout; The contact hole of the lower film; (2) The semiconductor substrate on which the contact hole is formed is placed in the chamber, and the bleed gas is supplied into the chamber; (3) A sacrificial metal layer is formed only in the lower film On the other hand, it is obtained by supplying a sacrificial metal source gas which is selectively deposited for the insulating film and the lower film into the chamber; (4) By supplying a halogen source having a higher affinity than the metal source in the sacrificial metal layer_ 3 (Please read the notes on the back before writing this page) t Ding% This paper size is applicable to the Chinese National Standard (CNS) A4 (210X297 mm). The seal of the Zhengong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy Λ 8. Βδ 403991___S_ Sixth, the scope of patent application is low metal halide gas to the chamber, and a sacrificial metal layer is used to replace the sacrificial metal layer; and (5) a conductive layer filled with contact holes is formed. 16. The method of filling a contact hole using the selective metal layer forming method according to item 15 of the application, wherein the insulating film in step (1) is an oxide film (Si02) or a composite film containing an oxide film. 17. The method of filling a contact hole using a selective metal layer forming method as claimed in item 15 of the scope of patent application, wherein the lower film in step (1) is silicon or nitrogen doped with impurities and having hydrogen terminal free radicals. Formed by titanium (TiN). 18. A method for filling a contact hole using a selective metal layer forming method according to item I5 of the scope of patent application, wherein the mixture of hydrogen (H2) and silane (SiH4) in the purge gas system in step (2). 19. For example, the method of filling a contact hole using a selective metal layer forming method using a selective metal layer forming method, wherein the purge gas system in step (2) is continuously supplied, or a predetermined amount is first supplied for purge gas, And it is periodically supplied in a predetermined amount after the sacrificial metal layer is formed and replaced by the deposited metal layer. 20. The method of filling a contact hole by using a selective metal layer forming method according to item 15 of the scope of patent application, further comprising forming a barrier layer on the deposition after step (4) of replacing the sacrificial metal layer with a deposited metal layer. Steps on the metal layer. _ 4 This paper is AA (CNS) A4J ^ (210X297 公 #) I— i I I I .1T line. _ (Please read the precautions on the back before continuing on this page)
TW87116247A 1998-06-16 1998-09-30 Method of forming selective metal layer and method of forming capacitor and filling contact hole using the same TW403991B (en)

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