JPS63140525A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63140525A JPS63140525A JP28751386A JP28751386A JPS63140525A JP S63140525 A JPS63140525 A JP S63140525A JP 28751386 A JP28751386 A JP 28751386A JP 28751386 A JP28751386 A JP 28751386A JP S63140525 A JPS63140525 A JP S63140525A
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- point metal
- silicon
- high melting
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000010408 film Substances 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 37
- 238000002844 melting Methods 0.000 claims abstract description 36
- 230000008018 melting Effects 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000010703 silicon Substances 0.000 claims abstract description 28
- 238000006243 chemical reaction Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000010409 thin film Substances 0.000 claims abstract description 14
- 150000004820 halides Chemical class 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052786 argon Inorganic materials 0.000 abstract description 4
- 230000001603 reducing effect Effects 0.000 abstract description 4
- 239000011261 inert gas Substances 0.000 abstract description 3
- 230000005669 field effect Effects 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 238000006467 substitution reaction Methods 0.000 abstract 1
- 229910021332 silicide Inorganic materials 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 229910021341 titanium silicide Inorganic materials 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 230000001934 delay Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 230000035484 reaction time Effects 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 2
- 239000003085 diluting agent Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 229910015255 MoF6 Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 229910001507 metal halide Inorganic materials 0.000 description 1
- 150000005309 metal halides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- RLCOZMCCEKDUPY-UHFFFAOYSA-H molybdenum hexafluoride Chemical compound F[Mo](F)(F)(F)(F)F RLCOZMCCEKDUPY-UHFFFAOYSA-H 0.000 description 1
- 238000006722 reduction reaction Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 150000003609 titanium compounds Chemical class 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は半導体装置の製造方法に関し、特には高融点金
属膜を導電材とする半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device using a high melting point metal film as a conductive material.
〈従来の技術〉
近年、半導体装置特にMO5LSIにおいてはハターン
の微細化、高密度化が進み、それに伴って電極や配線が
もつ抵抗の定めに生じる信号伝搬の遅延が大きな問題に
なっている。<Prior Art> In recent years, semiconductor devices, particularly MO5LSIs, have become increasingly finer and more densely packed, and as a result delays in signal propagation caused by determining the resistance of electrodes and wiring have become a major problem.
このような問題に対して例えばゲート電極においては、
従来から広く用いられている多結晶シリコンの低抵抗化
を図るべく、抵抗値の低い高融点金属或いは高融点金属
シリサイドを用いることが試みられている。実用化され
ている25SDRAM製品の中にも、モリブデンシリサ
イド或いはタングステンシリサイドと多結晶シリコンの
2層構造等が採用されている。For example, in gate electrodes,
In order to lower the resistance of polycrystalline silicon, which has been widely used in the past, attempts have been made to use refractory metals or refractory metal silicides with low resistance values. Among the 25SDRAM products that are in practical use, a two-layer structure of molybdenum silicide or tungsten silicide and polycrystalline silicon is adopted.
上記高融点金属膜を有する2層構造ゲート電極の製造プ
ロセスとしては、基板シリコンの表面を約200〜85
0λの深さで熱酸化し、該酸化膜上に続いて減圧CVD
法を用いて多結晶シリコンを2000λ程度堆積する。In the manufacturing process of the two-layer gate electrode having the above-mentioned high melting point metal film, the surface of the substrate silicon is
Thermal oxidation is performed at a depth of 0λ, followed by low pressure CVD on the oxide film.
Polycrystalline silicon is deposited to a thickness of about 2000λ using the method.
次に上記多結晶シリコンにリン或いは砒素等の不純物を
ドーピングして導電性を出現させた後、タングステンシ
リサイド或いはモリブデンシリサイド’kcVD性成い
はスパッタリング法によって3000λ程度の膜厚に形
成する。その後ゲート電極形状になるように上記多結晶
シリコンと高融点金属シリサイドをRIE(React
ive Ion Etching )Kよってエツ
チングする方法がある。Next, the polycrystalline silicon is doped with impurities such as phosphorus or arsenic to make it conductive, and then tungsten silicide or molybdenum silicide is formed to a thickness of about 3000λ by kcVD or sputtering. After that, the polycrystalline silicon and high-melting point metal silicide are processed by RIE (React) to form the gate electrode shape.
ive Ion Etching) There is a method of etching.
更に上記製造方法とは別に、最近では酸化膜上に形成し
た多結晶シリコン上にチタンをスパッタリング法で形成
し、700〜900℃で熱処理することによって多結晶
シリコンの一部をチタンシリサイド化して多結晶シリコ
ンとチタンシリサイドの2層構造をもつゲート電極を形
成する方法も提案されてhる。Furthermore, apart from the above manufacturing method, recently titanium is formed on polycrystalline silicon formed on an oxide film by a sputtering method, and a part of the polycrystalline silicon is turned into titanium silicide by heat treatment at 700 to 900°C. A method of forming a gate electrode having a two-layer structure of crystalline silicon and titanium silicide has also been proposed.
〈発明が解決しようとする問題点〉 処で高融点金属及び高融点金属シリサイドは。<Problem that the invention seeks to solve> Where are high melting point metals and high melting point metal silicides?
次表に示す比抵抗値(μΩ・備)を有しており、従って
前者のような方法によりゲート電極を形成した場合、高
融点金属シリサイド膜の抵抗は高融点金属膜に比べて非
常に大きな値をもち、信号伝搬の高速化の目的は達成し
得ない。It has the specific resistance value (μΩ) shown in the table below. Therefore, when a gate electrode is formed by the former method, the resistance of the high-melting point metal silicide film is much higher than that of the high-melting point metal film. The purpose of speeding up signal propagation cannot be achieved.
また積層され之シリサイド膜と多結晶シリコン膜を同時
に精度よ〈パターニングすることが難しく、実際の製品
においてゲート長が変化し、トランジスタ特性の安定性
や再現性に問題の生じる慣れがあった。更に多結晶シリ
コンとシリサイドの熱膨張係数においても次表の如く差
が太きく、また積層界面に生成した自然酸化膜の影響等
でシリサイド層が剥がれ易く信頼性に問題があっ念。Furthermore, it is difficult to accurately pattern the laminated silicide film and polycrystalline silicon film at the same time, and the gate length changes in the actual product, causing problems in the stability and reproducibility of transistor characteristics. Furthermore, there is a large difference in the coefficient of thermal expansion between polycrystalline silicon and silicide, as shown in the table below, and the silicide layer is likely to peel off due to the natural oxide film that forms at the laminated interface, causing reliability problems.
後者のチタンシリサイドを形成するゲート電極作成方法
では、ターゲットとなるチタンの純度が低く、Ni 、
Cr 、Fe等の不純物が多く含まれ。In the latter gate electrode production method that forms titanium silicide, the purity of the titanium target is low, and Ni,
Contains many impurities such as Cr and Fe.
半導体装置の信頼性に問題を生じる原因になっている。This causes problems in the reliability of semiconductor devices.
またチタン化合物はフッ酸に溶解する性質があるため、
現行の製造プロセスで用いられているフッ酸洗浄工程を
採用することができず、新たな洗浄方法及び洗浄ライン
が必要になる。更に熱膨張率の点ではチタンシリサイド
がシリコンに比べて大きいため半導体基板自体が反り易
くなり、パターン精度が低下し、製造プロセスの継続が
難しくなる等の問題があり、いずれの製造方法も高密度
集積回路装置の製造に充分なものとはいえなかった。In addition, titanium compounds have the property of dissolving in hydrofluoric acid, so
The hydrofluoric acid cleaning process used in current manufacturing processes cannot be used, and a new cleaning method and cleaning line will be required. Furthermore, since titanium silicide has a higher coefficient of thermal expansion than silicon, there are problems such as the semiconductor substrate itself becoming warped, reducing pattern accuracy, and making it difficult to continue the manufacturing process. It could not be said that it was sufficient for manufacturing integrated circuit devices.
く問題点を解決する之めの手段〉
本発明は上記従来方法の欠点を除去し、高融点金属膜を
導電材とする半導体装置の製造方法を提供するもので、
多結晶シリコンや非晶質シリコン薄膜等の少なくともシ
リコンを含む薄膜層について、該薄膜層を予め所望形状
にパターニングした後、高融点金属のハロゲン化物乞含
む雰囲気中で加熱処理して化学反応させることにより、
シリコンを高融点金属に置き換えて高融点金属膜を導電
材とする半導体装置を製造する。Means for Solving the Problems The present invention eliminates the drawbacks of the above conventional methods and provides a method for manufacturing a semiconductor device using a high melting point metal film as a conductive material.
For a thin film layer containing at least silicon, such as a polycrystalline silicon or amorphous silicon thin film, the thin film layer is patterned in advance into a desired shape, and then heated in an atmosphere containing a high melting point metal halide to cause a chemical reaction. According to
A semiconductor device is manufactured in which silicon is replaced with a high melting point metal and the high melting point metal film is used as a conductive material.
く作 用〉
半導体基板上の導電体は、多結易シリコン薄膜等の比較
的高い抵抗値を示す材料のみではなく、シリコンを化学
変化により置き換えた低抵抗値の高融点金属を用りて構
成することができ、微細加工による高抵抗化を防ぎ集積
回路の信号伝搬の遅延を防ぐことができる。また導電体
は、シリコンを含む薄膜?予め所望形状にパターニング
した後に高融点金属に置換えるため、多層構造をエツチ
ングする工程に比べて同材質層のエツチング処理で済む
。The conductor on the semiconductor substrate is not only made of a material with relatively high resistance, such as a polycrystalline silicon thin film, but also made of a low-resistance, high-melting-point metal that replaces silicon through chemical change. This makes it possible to prevent high resistance due to microfabrication and prevent delays in signal propagation in integrated circuits. Also, is the conductor a thin film containing silicon? Since the metal is replaced with a high melting point metal after being patterned into a desired shape in advance, etching of layers of the same material is sufficient, compared to the process of etching a multilayer structure.
〈実施例〉
まずシリコン(Si)’に高融点金属(W、Mo)に置
き換えるための具体的な化学反応の例を次式%式%(1
)
第1図は、上記(1)式の反応においてアルゴンを稀釈
ガスとしてWF、i供給し、圧力1 torrの下で反
応させた場合にシリコンが消費されて高融点金属(W)
ic置き換わる際の、シリコン消費量或いは形成される
W膜厚と反応時間との関係を示す。図九ら判るように反
応温度300℃では初期時にW膜が100〜200人成
長するもののその後膜成長はほとんど停止する。一方4
00℃では反応開始後10分でW膜厚は5000人にも
達し速や−75,にW膜の成長が行われる。従って反応
温度としては400℃以上が望ましい。<Example> First, an example of a specific chemical reaction for replacing silicon (Si)' with a high melting point metal (W, Mo) is given by the following formula % formula % (1
) Figure 1 shows that in the reaction of equation (1) above, when argon is supplied as a diluent gas and the reaction is carried out under a pressure of 1 torr, silicon is consumed and the high melting point metal (W) is
The relationship between silicon consumption or formed W film thickness and reaction time when IC is replaced is shown. As can be seen from FIG. 9, at a reaction temperature of 300° C., 100 to 200 W films grow at the initial stage, but the film growth almost stops thereafter. On the other hand 4
At 00°C, the W film thickness reaches 5,000 layers in 10 minutes from the start of the reaction, and the W film grows at a rate of -75°C. Therefore, the reaction temperature is preferably 400°C or higher.
第2図は、上記式+211c示す如く高融点金属がMO
からなる場合の、反応時間とシリコン膜消費量及びMO
膜成長厚の関係を示している。未反応においても、雰囲
気を約400℃に保持し、圧力1 torrで行った結
果である。Figure 2 shows that the high melting point metal is MO as shown in the above formula +211c.
Reaction time, silicon film consumption, and MO
It shows the relationship between film growth thickness. Even in the unreacted state, the atmosphere was maintained at about 400° C. and the pressure was 1 torr.
(実施例1)
次に上記化学反応を用いてMO5電界効果トランジスタ
のゲート電極を作成する工程を挙げて説明する。(Example 1) Next, a process for creating a gate electrode of an MO5 field effect transistor using the above chemical reaction will be described.
第3図falにおrて、シリコン基板lの表面を熱酸化
して200〜800λ程度の膜厚全有するゲート酸化膜
2を形成する。上記ゲート酸化膜2上に減圧CVD法を
用いて3000〜4000人の膜厚をもつ多結晶シリコ
ン模3を形成する。該多結晶シリコン膜3はゲート電極
、素子間配線等に対応して所望形状にエツチングを施こ
し、第3図(bK示す如くシリコン基板l上に露出シリ
コンを有する残留薄膜領域を形成する。上記残留多結晶
X/
シリコン薄膜3にMO8)ランジスタの\−ス。In FIG. 3 fal, the surface of the silicon substrate 1 is thermally oxidized to form a gate oxide film 2 having a total thickness of about 200 to 800 λ. A polycrystalline silicon pattern 3 having a thickness of 3,000 to 4,000 wafers is formed on the gate oxide film 2 using a low pressure CVD method. The polycrystalline silicon film 3 is etched into a desired shape corresponding to gate electrodes, inter-device wiring, etc., to form a residual thin film region having exposed silicon on the silicon substrate 1 as shown in FIG. 3 (bK). Residual polycrystalline
ドレイン領域等と共にリン或いは砒素等の不純物をイオ
ン注入して導電性を持たせる。尚該多結晶シリコン3の
導電化は、後述する多結晶シリコン3を高融点金属に置
き換える工程において、シリコンが完全に高融点金属に
置換わる場合は多結晶シリコンに導電性をもたせる必要
はない。しかし完全17i:置き換えることは難しく、
また完全に置き換えた場合には高融点金属と酸化膜が密
着性の点で必ずしも良好とはいえない。従って本実施例
の如く、シリコン成分に導電性をもたせてゲート酸化膜
上に残存させることが望ましh0
上記残留多結晶シリコン薄膜3企有するシリコン基板i
、アルゴン等の不活性ガスを稀釈ガスとしてWFs k
供給した炉内に設置する。炉内を温度約400℃圧力約
1 torr 7C保持し之雰囲気で表面が露出した残
留薄1漠3を加慈し1次式で示す還元反応を起こさせる
。Impurities such as phosphorus or arsenic are ion-implanted into the drain region and the like to impart conductivity. Note that it is not necessary to make the polycrystalline silicon 3 conductive if silicon is completely replaced with a high melting point metal in the step of replacing the polycrystalline silicon 3 with a high melting point metal, which will be described later. However, complete 17i: difficult to replace,
Furthermore, when completely replaced, the adhesion between the high melting point metal and the oxide film is not necessarily good. Therefore, as in this embodiment, it is desirable to make the silicon component conductive and leave it on the gate oxide film.
, WFs k using an inert gas such as argon as a diluent gas.
Install it in the supplied furnace. The temperature in the furnace is maintained at about 400° C. and the pressure is about 1 torr and 7 C, and the residual thin film 3 whose surface is exposed is treated in this atmosphere to cause a reduction reaction shown by the linear equation.
2 W F 6 + 8 S i→2 W + 35
i F a上記反応によってシリコンはハロゲン化物と
なって基板から飛び散り1代って高融点金属膜が形成さ
れる。炉内の温度を高め保持時間を長期化することによ
って高融点金属膜の膜厚は厚くなり、第3図fclに示
すように表面の多結晶シリコン3が順次高融点金属膜4
に置き換った2層構造からなるゲート電極が形成され、
更に反応を進めることにより第3図fdlに示す如くほ
ぼ完全に高融点金属膜に置き換ったゲート電極が形成さ
れる。2 W F 6 + 8 Si → 2 W + 35
i F a By the above reaction, silicon becomes a halide and scatters from the substrate, forming a high melting point metal film. By increasing the temperature in the furnace and prolonging the holding time, the thickness of the high melting point metal film becomes thicker, and as shown in FIG.
A gate electrode consisting of a two-layer structure replaced with is formed,
By further advancing the reaction, a gate electrode almost completely replaced by the high melting point metal film is formed as shown in FIG. 3fdl.
第3図(む)の如く芯部に多結晶シリコンが残った電i
構造でも多結晶シリコンのみ力・らなる電極に比べて抵
抗値は著しく低減される。Electrical i with polycrystalline silicon remaining in the core as shown in Figure 3 (m)
Even in terms of structure, the resistance value is significantly reduced compared to electrodes made solely of polycrystalline silicon.
(実施例2)
未発明金、シリコン半導体基板にオーミックコンタクト
する電極を形成する場合に適用した実施例を説明する。(Example 2) An example applied to forming an electrode in ohmic contact with an uninvented gold or silicon semiconductor substrate will be described.
@4図(alF!”おhて、シリコン基板110表面に
熱酸化或いはCVD法によって酸化膜12を形成する。@Figure 4 (alF!) Then, an oxide film 12 is formed on the surface of the silicon substrate 110 by thermal oxidation or CVD.
該酸化膜12に対して電気的接続する念めのコンタクト
ホール18′lr、エツチング等によって形成しシリコ
ン基板11の表面を露出させる。コンタクトホール18
を形成した半導体基板表面にCVD法によって第4図(
blの如く基板全面に多結晶シリコン14を形成しホー
ル13を充填する。A preliminary contact hole 18'lr for electrical connection to the oxide film 12 is formed by etching or the like to expose the surface of the silicon substrate 11. contact hole 18
Figure 4 (
Polycrystalline silicon 14 is formed on the entire surface of the substrate as shown in bl, and the holes 13 are filled.
次にホール1B’Z充填している多結晶シリコン以外の
多結晶シリコンをRIE法等で除去し、第4図IC)の
ように少なくともコンタクトホール18を多結晶シリコ
ン14で充填する。上記半導体基板llkアルゴンで稀
釈したWF6 ガス雰囲気中にセットし、約400℃圧
力I LOrrの下で化学反応を起こさせ、多結晶シリ
コン14’に高融点金属15に置き換えて、シリコン基
板にオーミックコンタクトした高融点金属膜力1らなる
電極を形成する(第4図(dl ) 0
高融点金属がM。である場合は1Moの特性として水素
による還元作用が弱いため、稀釈ガスは不活性ガスの代
りに水素ガスを用いても実施するることかできる。Next, polycrystalline silicon other than the polycrystalline silicon filling hole 1B'Z is removed by RIE or the like, and at least contact hole 18 is filled with polycrystalline silicon 14 as shown in FIG. 4IC). The above semiconductor substrate Ilk is set in a WF6 gas atmosphere diluted with argon, a chemical reaction is caused under a pressure of about 400°C, and the polycrystalline silicon 14' is replaced with a high melting point metal 15, making ohmic contact with the silicon substrate. (Fig. 4 (dl)) 0 When the high melting point metal is M, the reducing action by hydrogen is weak as a characteristic of 1Mo, so the dilution gas is an inert gas. Alternatively, hydrogen gas may be used.
第5図は上記工程を経て、多結晶シリコン(Si)をモ
リブデン(Mo)K置き換えることにより形成し念配線
の抵抗と雰囲気(390℃、 l torr。FIG. 5 shows the resistance and atmosphere (390° C., 1 torr) of the wire formed by replacing polycrystalline silicon (Si) with molybdenum (Mo) K through the above steps.
MoF6/H2=0.07 、800 secm )保
持時間との関係を示す図である。同図から明ら73為な
ようにモリブデン層が成長する前の多結晶シリコン状態
では35QKΩを示した抵抗値が、M o F 6の雰
囲気に約30分同晒すことによって6にΩに低下してい
る。(MoF6/H2=0.07, 800 sec) is a diagram showing the relationship with retention time. As is clear from the figure, the resistance value, which was 35QKΩ in the polycrystalline silicon state before the molybdenum layer grows, decreased to 6Ω by being exposed to the M o F 6 atmosphere for about 30 minutes. ing.
く効 果〉
以上本発明によれば、低い抵抗値をもつ高融点金属膜を
半導体基板上の導電部分に用いt半導体装置を作成する
ことができ、微細化、高集積化した半導体装置について
も、信号伝撮の遅延を防ぐことができる。また所望形状
をもつ高融点金属膜を形成する際に、予めパターニング
した領域に含まれたシリコンを置き換えて高融点金属膜
とするため、高融点金属膜をエツチングする必要がなく
製造工程に対する負担が著しく軽減される。Effects> As described above, according to the present invention, it is possible to create a semiconductor device by using a high melting point metal film with a low resistance value as a conductive part on a semiconductor substrate, and it is also possible to create a semiconductor device that is miniaturized and highly integrated. , it is possible to prevent delays in signal transmission. In addition, when forming a high melting point metal film with a desired shape, the silicon contained in the pre-patterned area is replaced with a high melting point metal film, so there is no need to etch the high melting point metal film, reducing the burden on the manufacturing process. significantly reduced.
第1図は未発明を説明するためのSi 、Wの膜厚変化
量と時開関係図、第2図は未発明を説明するためのSi
、Moの膜厚変化量と時間関係図。
第3図及び第4図は本発明による半導体装置の製造工程
を示す断面図、第5図は反応時間と抵抗値の時間変化を
示す図である。
1.11:シリコン基板。
2.12二酸化膜。
3.14:多結晶シリコン、
4.15:高融点金属膜
代理人 弁理士 杉 山 毅 至(他1名)第1゜′べ
時閉〔力
@べぎ閏〔j
第2図
(c) (C)第3図
第4区
OIQ 2o 30形べ時閉
(発)
第5図Fig. 1 is a diagram showing the change in film thickness of Si and W and time-varying relationship to explain the uninvented state, and Fig. 2 is a diagram of the time-slope relationship between the film thickness of Si and W to explain the uninvented state.
, Mo film thickness change amount and time relationship diagram. 3 and 4 are cross-sectional views showing the manufacturing process of the semiconductor device according to the present invention, and FIG. 5 is a diagram showing the reaction time and the change in resistance value over time. 1.11: Silicon substrate. 2.12 Dioxide film. 3.14: Polycrystalline silicon, 4.15: High-melting point metal film Representative Patent attorney Takeshi Sugiyama (and 1 other person) 1st time closing [Force @begi] Figure 2 (c) (C) Figure 3
Ward 4 OIQ 2o Type 30 Closed (departure) Figure 5
Claims (1)
ーニングする工程と、 高融点金属のハロゲン化物を含む加熱雰囲気に上記残留
薄膜層を設置する工程と、 残留薄膜層を上記雰囲気に保持して化学反応により上記
シリコンを高融点金属に置換する工程とを備えてなるこ
とを特徴とする半導体装置の製造方法。 2)前記薄膜層は絶縁層上に堆積させた多結晶シリコン
からなり、該多結晶シリコンを化学反応により高融点金
属に置換してなることを特徴とする請求の範囲第1項記
載の半導体装置の製造方法。 3)前記薄膜層は、半導体基板層上に堆積した絶縁膜に
形成された開孔を埋める多結晶シリコンからなり、該多
結晶シリコンを化学反応により高融点金属に置換して電
極を形成することを特徴とする請求の範囲第1項記載の
半導体装置の製造方法。[Claims] 1) A step of patterning the deposited thin film layer containing silicon into a desired shape; A step of placing the remaining thin film layer in a heated atmosphere containing a halide of a high melting point metal; A method for manufacturing a semiconductor device, comprising the step of substituting the silicon with a high melting point metal through a chemical reaction while maintaining the semiconductor device in the atmosphere. 2) The semiconductor device according to claim 1, wherein the thin film layer is made of polycrystalline silicon deposited on an insulating layer, and the polycrystalline silicon is replaced with a high melting point metal through a chemical reaction. manufacturing method. 3) The thin film layer is made of polycrystalline silicon that fills the openings formed in the insulating film deposited on the semiconductor substrate layer, and the polycrystalline silicon is replaced with a high melting point metal through a chemical reaction to form an electrode. A method for manufacturing a semiconductor device according to claim 1, characterized in that:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28751386A JPS63140525A (en) | 1986-12-02 | 1986-12-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28751386A JPS63140525A (en) | 1986-12-02 | 1986-12-02 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63140525A true JPS63140525A (en) | 1988-06-13 |
Family
ID=17718314
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28751386A Pending JPS63140525A (en) | 1986-12-02 | 1986-12-02 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63140525A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2338594A (en) * | 1998-06-16 | 1999-12-22 | Samsung Electronics Co Ltd | A method of forming a selective metal layer |
US6372598B2 (en) | 1998-06-16 | 2002-04-16 | Samsung Electronics Co., Ltd. | Method of forming selective metal layer and method of forming capacitor and filling contact hole using the same |
CN114005872A (en) * | 2020-07-28 | 2022-02-01 | 美光科技公司 | Integrated assembly and method of forming an integrated assembly |
-
1986
- 1986-12-02 JP JP28751386A patent/JPS63140525A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2338594A (en) * | 1998-06-16 | 1999-12-22 | Samsung Electronics Co Ltd | A method of forming a selective metal layer |
US6372598B2 (en) | 1998-06-16 | 2002-04-16 | Samsung Electronics Co., Ltd. | Method of forming selective metal layer and method of forming capacitor and filling contact hole using the same |
CN114005872A (en) * | 2020-07-28 | 2022-02-01 | 美光科技公司 | Integrated assembly and method of forming an integrated assembly |
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