JPH02178922A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To maintain high selectivity to enable film formation by performing the patterning to open a scribe region too on a semiconductor substrate, and then exposing a conductor layer at the part to grow a conductive film, and next forming an insulating layer so that it may cover only the scribe region, and then growing a conductive film on a conductor layer. CONSTITUTION:Since an insulating layer 4 is formed at a scribe region 2, a conductive film 5 grows only at a conductor layer 3 and does not grow in the scribe region 2. For this reason, the surface of the scribe region can be smoothed, and it does not cause hindrance at the time of alignment in manufacturing processes after this. Also, since only the part of the conductor layer 3 is selectively grown, the selective growth area of the conductive film 5 is small, and the conductive film 5 never exfoliates. Hereby high selectivity can be obtained.

Description

[Detailed Description of the Invention] [Summary] Regarding a method of forming a conductive film on a semiconductor substrate by selective CVD method, the purpose is to form a conductive film while maintaining high selectivity. A step F in which a conductor layer is exposed and formed in a portion where a conductive film is to be grown later by patterning to open the region, and a step F in which an insulating layer is formed so as to cover the scribe region without covering the conductor layer. , and a step of growing a conductive film on the conductor layer by selective vapor deposition.

[Industrial application field]

The present invention uses selective CVD (vapor phase epitaxy) for semiconductor substrates.
The present invention relates to a method of forming a conductive film by a method.

In recent years, the scale of semiconductor devices, especially semiconductor integrated circuits, has been rapidly increasing, and there is a strong desire to improve the degree of integration.

For this reason, microfabrication technology centered on photolithography is being actively developed, but as a result, the aspect ratio of contact holes and peer holes becomes too large.
This is the wiring layer 0FI formed by sputtering method.
This has resulted in poor sub-coverage and reduced performance, reliability and manufacturing yield. .

Therefore, as one of the means to solve this problem, recently,
2. Description of the Related Art Practical development of a so-called selective CVD technique, which selectively embeds metal or metal silicide by vapor phase growth only on the surface of a conductor exposed in a contact hole or via ball, is underway. In addition to filling holes as described above, this selective CVD method can also be used to selectively grow a thin conductive film on a silicon layer or silicide layer formed on a substrate to lower resistance, and to reduce the resistance of aluminum alloy wiring. It is known that the technique is used by selectively growing wires to cover them in order to improve reliability such as prevention.

In this j:una selective CVD method, it is necessary to form a film with selectivity J:<.

(Conventional technology) FIG. 14 is a diagram illustrating an example of a conventional film forming method.

In the same figure <A), semiconductor substrate (silicon substrate) 71
Field oxidation II! J72. Channel stop layer 73. Goo 1 to oxide film 7/4. Goo 1 ~ Electrode 75. A source diffusion layer 76s and a drain diffusion layer 76o are formed, and then an insulating layer to be an interlayer insulating film is grown and etched according to the contact hole pattern 78 to form an interlayer insulating film 77. 1. During this etching, Area ill where no element is formed on the semiconductor substrate 71! (7 scribe areas) are provided, and these areas are used to perform spectrum analysis of the plasma emission intensity, and by detecting changes in the emission intensity, the contact hole pattern 78 is prevented from being excessively etched. The end point of etching is being detected. In this case, the scribe area 79 requires a certain amount of area.

Next, in FIG. 3B, a tangent-type conductive film 80 is grown by selective CVD, and a conductive film 81 is also grown in the seven scribe regions. Therefore, if such a conductive film 81 remains in the scribe area 79, it will cause a problem when cutting into chips in a later process.
), a mask 82 is provided and the conductive film 81 is removed by etching. In this case, since the conductive film 81 is removed by etching, it is not possible to obtain a high selectivity with respect to the substrate 71, resulting in unevenness 83 on the surface.
is removed, and an aluminum wiring pattern or the like is provided on the conductive film 80.

FIG. 15 shows a diagram illustrating another example of the conventional film forming method, in which the same parts as in FIG. 14 are designated by the same numbers.

In FIG. 15 (A>), an insulating layer to be an interlayer insulating film is grown and etched according to the contact small pattern 78 to form an interlayer insulating film 86.
A scribe area as shown in Figure 4 is not provided. Next, in the same figure (B), a conductive film 80 is grown by selective CVD method, but in this case, since there is no scribe area, the conductive film 80
Other than that, no conductive film is formed.

Subsequently, in the same figure (C), a mask 84 is provided, a part of the insulating film 86 is removed by etching, and a region 85 is formed (pull 1).
In this case as well, if the insulating film 86 remains on the region 85, problems will occur when cutting into chips in a later step, so a region 85 where the insulating film 86 does not remain is provided. In this case, since the insulating film 86 is removed by etching, the substrate 7
Since a sufficient selection ratio with respect to 1.1 can be obtained, unevenness as shown in FIG. Thereafter, the mask 84 is removed, and an aluminum wiring pattern or the like is provided on the conductive film 80.

On the other hand, there is a process technology that selectively grows a silicon layer or a conductive film formed on a substrate to lower the resistance. Remove the film by etching.

[Problem to be solved by the invention]

In the conventional example shown in FIG. 14, when removing the conductive film 81 grown in the scribe region [79] by etching,
Since it is not possible to obtain a high selectivity between the substrate 71 and the substrate 71,
This results in overetching, resulting in unevenness 83 as shown in FIG. 14(C). For this reason, there was a problem in that alignment was difficult in the one-step manufacturing process. 1
In addition, since the scribe area 79 is opened for detecting the end point of etching, the conductive film 8 is also formed in this area.
1 grows. That is, in addition to the conductive film 80, the conductive film 81 grows even in unnecessary parts.

In this way, if the area for selective growth is large, the film will easily peel off due to the stress, and the by-products of the growth reaction will increase, making it easier for the conductive film 80 to grow on the insulating film 77. There were problems such as decreased performance. These problems impose significant restrictions on the process conditions of the selective CVD method, and in some cases, the selective growth cannot be used practically.1 On the other hand, as shown in FIG. The conventional example does not have the above-mentioned problems, but when forming the contact ball pattern 78, the scribe area as shown in FIG. There are problems such as excessive overetching of the pattern 78, which makes it impossible to stably manufacture semiconductor devices.

An object of the present invention is to provide a method for manufacturing a semiconductor device that can form a film while maintaining high selectivity.

[Means to solve the problem]

FIG. 1 shows a diagram of the principle of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a scribe region (opened to detect the etching end point when exposing and forming the conductor layer 3), 3 is a conductor layer, 4 is an insulating layer, and 5 is a conductor. It is a membrane.

The above problem is caused by the scribe area t8! on the semiconductor substrate 1!
a step of patterning to open the conductor layer 2 and exposing the conductor layer 3 in a portion where the conductive film 5 is to be grown later;
The step of forming the insulating layer 4 so as to cover the scribe region 2 without covering the conductor layer 3 is characterized by including the step of growing the conductive film 5 on the conductor layer 3 by selective vapor deposition. 1. [Operation] In the present invention, since the insulating layer 4 is formed in the scribe region 2, the conductive film 5 grows only on the conductor layer 3, and does not grow in the scribe region 2. does not grow 1. For this reason, the surface of the scribe area can be smoothed, unlike the conventional case where the conductive film that has grown in the scribe area must be removed, and there is no problem with alignment in the subsequent manufacturing process. 5゜Also, since selective growth occurs only in the portion of the conductor layer 3, the selective growth area of the conductive film is smaller than in the conventional example, and the conductive film does not peel off, achieving high selectivity. I can do it.

In particular, when the insulating layer 4 is an oxide film formed by implanting oxygen ions using a resist with openings only in the scribe region 2 and applying heat treatment, the process up to forming the insulating layer 4 is relatively simple. be.

In addition, a step of forming an oxide film on the scribe region 2 and the conductor layer 3, which is a wiring pattern containing an aluminum base metal and silicon, by low-temperature oxidation of the insulating layer 4, and a step of forming an oxide film on the conductor layer 3, The L culm that is removed by chlorine-based plasma can be applied to a multilayer wiring pattern structure.

Furthermore, when the insulating layer 4 is made of a heat-resistant resin, it is easier to maintain the etching selectivity between the resin and the interlayer insulating film, compared to when an inorganic insulating film is used as the absolute R layer 4. The insulating layer 4 can be easily removed by etching. In addition, this method requires fewer steps up to the formation of the insulating layer 4 compared to a method in which an inorganic insulating film is formed.

〔Example〕

FIG. 2 shows a manufacturing process diagram of the first embodiment of the present invention. In FIG. A gate electrode 16D is formed, and then an insulating layer that becomes an interlayer insulating film is grown and is pierced according to the contact hole pattern 18 to form an interlayer insulating film 17.
form. In this case as well, as shown in Fig. 14, as in the conventional example,
One scribe area is opened and the etching end point of contacts 1 to hole patterns 18 is detected.

Next, in the same figure (B), an inorganic insulating film 20 is formed on the entire surface, a resist pattern 21 is formed so as to cover the scribe area 19, and this is done, leaving only the inorganic insulating film 20 covering the scribe area 19. Remove the inorganic insulating film (broken line) other than the above. In this case, as the inorganic insulating film 20,
In order to suppress the loss of the underlying interlayer insulating film 17 as much as possible when removing the coating, it is preferable to form the film as thinly as possible within a range that maintains selectivity depending on the film quality. Also, the material of the inorganic insulating film 20 is 5OG (spin-repellent glass), which has a fast etching speed, and PS.
It is preferable to use a CVDII film of G (phosphorus glass) tongue or a sputtered oxide film.

Next, the resist pattern 21 is removed, and the substrate is immersed in, for example, a hydrogen nitride (+-I F >aqueous solution) to remove the natural oxide film (particularly that within the contact hole pattern 18), and then dried at a low temperature. Next, as shown in the same figure (C),
Contact (Hehole pattern 18) is made by selective CVD method.
A conductive film 22 is embedded therein.

In this case, although growth nuclei are formed on the surface of the silicon exposed by the contact hole pattern 18 and the conductive film 22 is formed, since the scribe region 19 is covered with the inorganic insulating film 20, this portion is conductive. The membrane does not grow.

For example, when using tungsten (W>) as a conductor,
Tungsten hexanotide (WF6) is used as the main raw material gas, and hydrogen (Hz) or monosilane (S!l'', +) is used as the reducing agent. Growth temperature is 250℃~40℃
0°C is preferred.

In this case, if the CVD method is performed in an atmosphere of ten reducing gas (tungsten hexafluoride<WFs) after forming the inorganic insulating film 20, tungsten (W) will be deposited on the inorganic insulating film 20.
is growing! (2) The tungsten conductive film 22 was desired to grow only on the exposed portion of the semiconductor substrate 11, that is, the selectivity was maintained.

This selectivity was the same for growth on silylides and aluminum alloys, which will be described later. The maintenance of such selectivity has been experimentally confirmed and is IC;
It can be sufficiently beaten considering that it is obtained from processes such as adsorption of the raw material gas on each surface, contribution to the reduction reaction on each surface, and contribution of reduction reaction by-products.

Next, in FIG. 2D, a wiring pattern 23 made of aluminum (AL) alloy is formed on the conductive film 22-t. The inorganic insulating film 20 is removed at the same time as the peer hole or wire bonding window is opened in the next step. In this case, it can be removed before the wiring pattern 23 is formed, but generally the adhesion between the tungsten (W) in the contact ball pattern 18 and the insulating film 17 is not very good, so isotropic etching such as wet etching is performed. Therefore, anisotropic etching is suitable for this purpose.When removing the inorganic insulating film 20, the insulating film 20 and the substrate 11 are removed.
Since a sufficient selectivity ratio can be achieved with respect to the above, the surface does not have any unevenness.

In this way, in the present invention, the inorganic insulating film 20 is provided so as to cover the scribe region 19 ('J, scribe region 1
Since the conductive film is prevented from growing in the area 9, there is no unevenness in the scribe area when removing the conductive film as in the conventional example shown in FIG. 14 (and the area of the conductive film selectively grown is Since it is smaller than the conventional example shown in FIG. 14, there is no risk of the conductive film peeling off, and the film can be formed with high selectivity.Furthermore, since the scribe region 19 is provided to form the contact hole pattern 18, Compared to the conventional example shown in FIG. 15, the end point of etching can be detected more reliably and stable production can be achieved.

FIG. 3 shows a manufacturing process diagram of a second embodiment of the present invention. 1st
The steps up to the steps shown in FIG. 2(A) of the embodiment are the same. The surface of the silicon exposed by forming the contact ball pattern 18 is thermally oxidized, and an oxide film 2 is formed at the bottom of the contact hole pattern 18 as shown in FIG. 3(A).
4. An oxide film 25 is formed in the scribe region 19. In this case, an oxide film of 24°2 is formed not by thermal oxidation but by low-temperature oxidation.
It is also possible to form a 5. This low-temperature oxidation can be performed, for example, by exposing the substrate to microwave-excited F)CE(02) plasma.

Next, a resist batten 26 is formed to cover the oxide layer 25.

Next, the oxide film 24 is removed using the resist pattern 26, and the resist pattern 26 is removed, leaving the oxide film 25 as shown in FIG. A conductive film 27 is embedded in 18 . In this case, since the scribe region 19 is covered with the oxide film 25, no conductive film will grow in this portion. In the subsequent steps, a wiring pattern is formed and the oxide film 25 is removed, as in the first embodiment. The effect is similar to that of the first embodiment.

FIG. 4 shows a manufacturing process diagram of a third embodiment of the present invention. 1st
The two culms shown in FIG. 2 (A) of the example are the same.

As shown in FIG. 4A, a resist pattern 28 having openings only in the scribe region 19 is formed. Here, two oxygen ions are implanted to form a layer 30 having a composition close to silicon oxide (S!Oz) on the surface of the scribe region 19 where the resist pattern 28 is not present.

The resist pattern 28 is then removed, followed by a heat treatment to convert the layer 30 to silicon oxide@30-. Next, as shown in FIG. 3B, a conductive film 31 is formed using the silicon oxide layer 30- as a mask. In this case, the steps up to forming the insulating layer in the scribe area are simpler than those in the first and second embodiments.

FIG. 5 shows a manufacturing process diagram of a fourth embodiment of the present invention. This product has a two-layered wiring pattern.

The steps shown in FIGS. 2(A) to 2(D) of the first embodiment are the same. In Fig. 5 (A>), the interlayer insulating film 3 is
After growing the material 2, it is removed by etching to form an opening for the turn scribe region 34 of the first layer (wiring) 1. At this time, the inorganic insulating film 20 in the scribe region 34 is removed. The opening in the scribe area 1i134 is used to detect the etching end point of the peer hole pattern 33. Next, in the same figure (B), an inorganic insulating film 35 is grown on the entire surface, a resist pattern 36 covering the scribe area 34 is formed, and the insulating film 35 is etched. After removing the resist pattern 36 and performing appropriate pretreatment (removal of the natural oxide film within the peer hole button 33), a conductive layer 11 is formed in the peer hole 33 by selective CVD.
Embed i137. At this time, since the conductive film 35 is formed in the scribe region 34, no conductive film is formed here. Next, as shown in FIG. 3D, a second layer of aluminum alloy wiring battens 38 is formed on the l-electric film 37. The effect is similar to that of the first embodiment.

FIG. 6 shows a manufacturing process diagram of a fifth embodiment of the present invention. The steps up to the step shown in FIG. 5(A) of the fourth embodiment are the same,
In this state, low-temperature oxidation (from room temperature to several hundred degrees Celsius) is performed to form a via ball pattern 3 as shown in FIG.
An oxide film 39 is formed on the wiring pattern 23 exposed at 3, and an oxide film 40 is formed on the scribe region 34. Next, only the oxide film 39 within the peer hole pattern 33 is removed by chlorine-based plasmon etching, as shown in FIG. 3B. In this case, if the selectivity is sufficient, the Regime 1 pattern is not necessary as shown in "-", but if the selectivity is insufficient, resist pattern /1.1 is supplemented on the oxide film /10. It would be nice if it was set up.

Next, in FIG. 4C, a conductive film 42 is grown by selective CVD. In this case, since the oxide film 40 is formed in the scribe region 34, the conductive film is not formed in this portion, as in the previous embodiments.

FIG. 7 shows a manufacturing process diagram of the sixth embodiment of the present invention. This is a silicone layer or silicone layer formed on a substrate.
A selectively grown film is applied to the noid layer to lower the resistance. In the same figure (A), a field oxide film 52. Forming an electrode 55 on the film 54.Goo 1, and then
A four-node hole 56 made of an insulating film is formed on both side walls of the hole electrode 55, and a source diffusion layer 57s and a drain diffusion layer 57o are formed. , +j when removing the etching to form the hole 56, the scribe area 58 is used to detect the end point of the etching.

Next, in the same figure (B), an inorganic insulating film 59 is grown on the entire surface, and a resist pattern 60 is formed in a similar manner to cover the scribe area 58, leaving the inorganic insulating film 59 only on the scribe area 58. Etching sea urchins. Next, after removing the pattern 60 and performing an appropriate pretreatment (removal of natural oxide film), a selective CVD method is performed.
Then, a conductive film 61 is grown. In this case as well, since the insulating film 59 is formed in the scribe region 58, no conductive film is formed in this portion. Thereafter, the device is manufactured using a normal MOS device manufacturing process. Note that in this case, there is no particular need to remove the insulating film 59.

FIG. 8 does not show a manufacturing process diagram of the seventh embodiment of the present invention. This method covers the wiring pattern with a selectively grown film to prevent disconnection of the wiring pattern.

In the same figure (A), an interlayer insulating film 63 is formed on a semiconductor substrate 62''-, a hole pattern 64 is formed in the contact 1, and a wiring pattern 65 is formed. At this point, the scribe area Vi66 is used to detect the end point of one tweezing of the contact mill hole pattern 64.

Next, in the same figure (B), an inorganic insulating film 67 is grown on the entire surface, and a pattern 68 is formed so as to cover the scribe region 66, leaving the conductive film 67 only in the scribe region 66. - Tsuchingzuru.

Next, after removing the resist pattern 68 and performing an appropriate pretreatment, a conductive film 69 is grown on the surface of the wiring pattern 65 by selective CVD (1).Hereafter, the MOS device is manufactured using a normal MOS device manufacturing process.

FIG. 9 shows a manufacturing process diagram of the eighth embodiment of the present invention, in which the same parts as in FIG. 2 are given the same numbers. This is the case using polyimide. The process shown in FIG. 9(A) is the same as that shown in FIG. 2(Δ) of the first embodiment. In the same figure (B), a resin pattern 90 with a thickness of 3″3 (1) is used to cover the scribe area 19 (in consideration of the humidity of the next selected CVD method, a heat-resistant porin, for example, polyimide is used here). suitable).

Next, as a pretreatment, for example, hydrogen fluoride (+-(F)
After removing the natural oxide film by immersing the substrate in an aqueous solution and drying it at low temperature, recontact 1 to small pattern 1 using selective CVD method.
8 is filled with a conductive film 22. Next, the resin pattern 90 is removed by ashing, and a wiring pattern 23 is formed on the conductive film 22, as shown in FIG. This also has the same effect as the first embodiment.

In this case, after forming the resin pattern 90, CVD is performed in an atmosphere of tungsten hexafluoride<WFs)+reducing gas.
When the method is performed, tungsten (
W) is growth t! The tungsten conductive film 22 was grown only on the exposed portion of the semiconductor substrate 11 (that is, the selectivity was maintained). This selectivity was the same for growth on siliguide and aluminum ram alloys, which will be described later. 1
This kind of selectivity has been experimentally confirmed, but the selectivity depends on the adsorption of the raw material gas onto each surface and the reduction reaction on each surface. It can be fully understood if you consider that it is obtained from processes such as the addition of by-products.

On the other hand, in this experiment, the growth humidity was 300°C to 400°C and 1. : Polyimide, which is a heat-resistant resin, was used as the a1 resin pattern 90, but disilane <5 was used as the reducing agent.
i2Hs)1)! It is known that the growth temperature can be lowered by using the original gas. Therefore, similar selective growth is possible using resin patterns with other structures depending on the growth temperature (similar to polyimide). It can be inferred that

Incidentally, if the resin pattern 90 is not provided as an insulating material formed in the scribe area as described above, it would be impossible to provide the resin pattern 90 as an insulating material in the scribe area. It is somewhat difficult to determine which selectivity ratio to select for the interlayer 5RII!i!17 when etching away the resist pattern 21 using the resist pattern 21, but in the eighth embodiment shown in FIG.
This is because since it is a resin pattern, it is easy to obtain a selectivity with respect to the interlayer insulating film 17. Further, the eighth embodiment requires fewer steps up to forming the insulating material (resin pattern 90) than the first embodiment.

FIG. 10 shows the manufacture of the ninth embodiment of the present invention. In the same figure, the same parts as in FIGS. FIG. 9 of Example <A)-<
The steps up to D> are the same. In FIG. 10 (A), an interlayer insulating film 32° via ball pattern 33 and scribe region tt34 are formed. Next, in FIG. 10 (B), a polyimide resin pattern 91 is formed to cover the scribe region IJ! 34. After forming and then surface treatment, the same figure (C)
, the via hole pattern 33 is formed by selective CVD method.
A conductive film 37 is embedded in the area. Subsequently, after removing the resin batten 90, a second layer wiring pattern 38 is formed on the conductive film 37, as shown in FIG.

FIG. 11 shows a manufacturing process diagram of the tenth embodiment of the present invention,
In the same figure, the same parts as in FIG. 7 are given the same numbers and their explanations are omitted. As shown in Figure (B), a polyimide resin pattern 92 is formed to cover the scribe area 58. Next, after surface treatment, as shown in Figure (C), one electrical film 61 is formed by selective CVD. Hereinafter, it is manufactured using a normal MOS device manufacturing process.

FIG. 12 shows a manufacturing process diagram of the eleventh embodiment of the present invention, in which the same parts as in FIG. 5, the steps up to the steps shown in FIG. 8(A) of the seventh embodiment are the same. 5. In FIG. 8(B), a polyimide resin pattern 93 is formed to cover the scribe area 66, Next, as shown in FIG. 1C, a conductive film 69 is formed on the surface of the wiring pattern 65 by selective CVD.
Manufactured using a normal MOS device manufacturing process. .

In addition, in each of the above-mentioned examples, only the scribe area was shown as the area to be covered outside the device formation area, but
- If the substrate is exposed at the 8th edge, for example as shown in FIG. (If the selective growth area is large, the conductive film will be easily peeled off, and the by-products of the growth reaction will increase, resulting in a decrease in selectivity.) It is advisable to cover the area with insulating material.

In addition, when growing a conductive film of 1 tungsten, tungsten hexafluoride (WF6) can be used as the main raw material gas, and higher order silanes such as disilane (Si2Ha) can be used as a reducing agent. The property is monosilane (S
Since the growth temperature is higher than that using iH7I), the thickness of the inorganic insulating film (Figs. 2, 5, 7, and 8) can be made thinner, while the growth temperature is Since the temperature can be lowered than when monosilane (Sit-1+) is used, a wider range of materials can be used as the resin pattern (FIGS. 9 to 12).

Furthermore, molybdenum (MO) and titanium (Ti>) can be considered as the conductive film other than tungsten (W), and it is also possible to selectively grow silicides of these metals.

Furthermore, although the above-described embodiments are applied to the manufacture of MOS devices, the present invention is not limited thereto, but is equally applicable to bipolar devices and pi-CMOS devices.

〔Effect of the invention〕

As explained above, according to the present invention, since the insulating layer is formed in the scribe area and the conductive film is grown, the surface of the scribe area can be made smooth, and alignment will not be hindered in the subsequent manufacturing process. Moreover, the selective growth area of the conductive film becomes small, the conductive film does not peel off, and high selectivity can be obtained.

As a result, a fine and stable connection structure can be obtained, and a high-performance device with low parasitic resistance and a highly reliable wiring pattern structure can be obtained.

[Brief explanation of the drawing]

Figure 1 is a diagram of the principle of the present invention, Figures 2 to 12 are manufacturing process diagrams of the first to 11th embodiments of the present invention, respectively, and Figure 13 explains that the periphery of the wafer is also covered with an insulating material. 14 and 15 are conventional manufacturing process diagrams for each side. In the figure, 1.11, 51.62 are semiconductor substrates, 2.19, 34. ．． 58, 66.95 are scribe regions, 3 is an exposed conductor layer, 4 is an insulating layer, 5.22, 27.31.37, 42, 61.69 are conductive films, 16s, 57s are source diffusion layers, 16o , 57o is a drain diffusion layer, 17.32.63 is an interlayer insulating film, 18.64 is a contact ball pattern, 20.35,
59.67 is an inorganic insulating film, 21.26, 28, 36, 4
1, 60.68 are resist patterns, 23.38.65 are wiring patterns, 24.25, 39.40 are oxide films, 29 are oxygen ions, 30- are silicon oxide layers, 33 are peer hole patterns, 52 55 is a field oxide film, 55 is a gate electrode, 56 is a side wall, 90.91, 92.93 is a resin pattern, and 94 is a wafer peripheral area. Patent applicant Fujitsu Co., Ltd. Agent Patent attorney Tadashi Ito

Claims (6)

[Claims] (1) A step of patterning a semiconductor substrate (1) to open a scribe region (2) and exposing a conductive layer (3) in a portion where a conductive film (5) is to be grown later; The scribe area (2) does not cover the conductor layer (3).
a step of forming an insulating layer (4) so as to cover the conductive layer (5) on the conductive layer (3) by selective vapor deposition;
1. A method for manufacturing a semiconductor device, the method comprising: growing a semiconductor device. (2) The insulating layer (4) includes the scribe area (2)
2. The method of manufacturing a semiconductor device according to claim 1, wherein the oxide film is formed by implanting oxygen ions using a resist that has only openings and applying heat treatment. (3) The insulating layer (4) is formed by forming an oxide film on the scribe area (2) and the conductive layer (3) by low-temperature oxidation, and forming an oxide film on the conductive layer (3). 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of removing the semiconductor device. (4) The conductive layer (3) is a wiring pattern containing aluminum alloy and silicon, and the process of removing the oxide film formed on the conductive layer (3) is by using chlorine-based plasma. 4. The method of manufacturing a semiconductor device according to claim 3. (5) The method of manufacturing a semiconductor device according to claim 1, wherein the insulating layer (4) is made of a heat-resistant resin. (6) The insulating layer (4) is connected to the scribe area (2).
6. The method of manufacturing a semiconductor device according to claim 1, further comprising forming the semiconductor substrate (1) on a peripheral portion of the wafer.