JPH0461219A - Semiconductor device, its manufacture and alignment method - Google Patents

Abstract

PURPOSE:To easily confirm the position of a master mark for mask alignment use and to realize a high-density wiring operation by a method wherein an opening which exposes the surface of a substratum and a stepped part which does not expose the surface are formed in an insulating film, a conductive material is deposited selectively inside the opening, a conductive thin film is formed on the insulating film and an alignment operation is executed by utilizing the stepped part. CONSTITUTION:A gate oxide film 5 and an interlayer insulating film 7 are etched or the like; a contact hole 8 as an opening formed so as to expose the upper part of a diffusion layer 6 is formed. In addition, a master mark part 9 as a stepped part is formed in a prescribed region in the interlayer insulating film 7 and a field oxide film 4 at its lower side. A first wiring layer 10 by selectively depositing a conductive material such as Al or the like by a CVD method is formed inside said contact hole 8. A second wiring layer 11 as a conductor layer by depositing a conductive material by a nonselective deposition method is formed on the first wiring layer 10 and the interlayer insulating film 7 and at the inside of the master mark part 9. A recessed part 11 a as a stepped part corresponding to the recessed shape by the interlayer insulating film 7 and the master mark part 9 is formed in the second wiring layer 11. The recessed part 11a is used as a mark for automatic mask alignment use when the second wiring layer 11 is patterned.

Description

[Detailed description of the invention]

[Field of Industrial Application] The present invention relates to semiconductor integrated circuit devices such as first memory photoelectric conversion devices and signal processing devices that are installed in various electronic devices, their manufacturing methods, and alignment methods, and particularly relates to alignment structures of semiconductor devices. The present invention relates to a semiconductor device having characteristics, a manufacturing method thereof, and an alignment method. [Prior Art] In a conventional 1' conductor device, the wiring layer is buttered,
When forming the mask, automatic mask alignment (auto attachment) using a pre-prepared recess at a predetermined position t◇ is used as a mark.
Improve the accuracy of buttering. I try to do that. For example, in a conventional semiconductor device having a CMOS transistor, a parent mark portion (concave portion) is formed by etching an oxide film at a predetermined position on the surface of the substrate.
After forming a metal film, a metal film is coated on the entire surface of the base including the parent mark part, and a recess corresponding to the shape of the parent mark part is formed in a part of the metal film as shown in FIG. I was there. A laser beam is irradiated into the recess formed in this way, and the detection f-ta obtained by detecting the reflection is used. AA (Te1.
Using processing data from an image processing method such as ``evision alignment'', automatic mask alignment was applied to the metal film described above. [Problems to be Solved by the Invention] However, in such conventional semiconductor devices, the metal film described in For example, when forming a C1 wiring layer using a metal film selective deposition technique such as the CVU method, when trying to obtain the required film thickness, the selective deposition and long bamboo that are the characteristics of this technology automatically The metal alloy deposited on and around the parent mark used for mask fitting becomes flattened, and a recess corresponding to the parent mark described above is formed in the automatic mask. It became difficult to confirm the parent mark, which is essential for mask alignment, and the accuracy of mask alignment was reduced as shown in Table 1.
There was a drawback of <low -■-. . The present invention solves the technical problem described in 1. It is easy to check the (☆) position of the parent mark using the mask r1, and
I? The purpose of the present invention is to provide an alignment method for semiconductor devices capable of 11i1 interconnection and their manufacture;

[There is. Means for Solving Problem 1] In the method for aligning a semiconductor device of the present invention, a conductive thin film is formed on the surface of a conductive base via an insulating film. forming an opening in the insulating film that exposes the ground surface; forming a stepped portion in the insulating film that exposes the ground surface; and forming a step in the opening that exposes the ground surface. and at least two steps of forming the conductive thin film on the insulating film, and performing alignment using the stepped portion. It is something to do. 4. The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which a wiring layer is provided on a conductive 1. ground surface 1 via an insulating film. step 7 of forming a step portion in which the base surface is not exposed in the insulating film; step 7 of forming a step portion in which the base surface is not exposed; and step 7 of selectively depositing a conductive material wheel 1 in the opening a step of forming a conductive thin film for forming the wiring layer on at least the insulating film; and a step of patterning the conductive thin film to form the wiring layer. That is. Furthermore, in the semiconductor device of the present invention, in a semiconductor device in which a conductive layer is formed on a base surface J of a conductive material with an insulating film interposed therebetween, an open hole formed in the insulating film and exposed on the ground surface is provided. a conductor formed therein, a step portion formed in the insulating film and not exposed on the base surface, and the insulating film.
The conductor layer is characterized in that the conductor layer is provided with a step corresponding to the step portion. 1 Effect] In the present invention, a new CVD5:i: selective metal deposition technique is used, so a conductive material is selectively deposited only in the openings where the N-conductive 1-ground surface is exposed. A conductor can be formed by By forming a conductive layer using a non-selective deposition method on the stepped portion formed on the conductor and the insulating film on the underlying surface, the resulting conductive layer has the stepped portion. It is possible to form a part that corresponds to the shape.By using this part as a mark for mask alignment, it is possible to pattern and mark the conductive layer by using automatic alignment. desired 1
[It is difficult to form a one-line pattern faithfully. ['Bold Examples] The present invention will be described in detail below with reference to the drawings. FIG. 1 shows a cliff conductor arrangement as a preferred embodiment of the present invention. In FIG. 1, numeral 1 is MO
S Functions of transistors, bipolar transistors, etc. 1
This is a semiconductor substrate that serves as a conductive base made of silicon or the like on which a semiconductor substrate is formed. A thick field oxide film 4 and a predetermined region of the main semiconductor substrate
A gate oxide film 5 having a small thickness is formed. In this game (semiconductor substrate on the "side" of the predetermined region of the oxide film 5),
A diffusion layer 5 is provided. Further, an interlayer insulating film 'l is formed with a predetermined thickness on the field oxide film 4 and gate oxide film 5. On the other side, a contact hole 8 is formed by etching the gate oxide film 5 and the interlayer insulating film 7 to expose the upper part of the diffusion layer 6. Further, in a predetermined region of the glabellar insulating film 7 and the field oxide film 4 below it, a parent mark as a stepped portion is formed by etching from the - face of the glabellar insulating film 7 to the inside of the field oxide film 4. A section 9 is provided. There is a layer interlayer inside the contact hole 8 mentioned above. A conductive material 1 such as A42 is selectively deposited using a special CVD method, which will be described in detail later, so that the 10 sides of the membrane 7 and the blood are formed. 1 wiring layer 10 has been formed.A conductive material is deposited in this first ff11° line layer lO, the soil of the interlayer insulating film 'r, and the inside of the parent mark part 9 by a non-selective deposition method. A second wiring layer 11 is formed as a deposited conductive layer 2. In a semiconductor device having such a wiring structure, an interlayer The insulating film 7 and the parent mark portion 9 correspond to the concave shape 4.7 and have a step difference,
A recess 11a is formed. This recess number 11a is used as a mark for use in an automatic mask when patterning the second wiring layer 11. This talented conductor outfit @&Joil is the above-mentioned parent mark part ≦3
Since the recess 1.1a can be formed accurately at the position of , this recess 11a can be used as a mark and the butter as stated in Proposition 1! It is possible to form interconnections using the same method. Therefore, since the first layer is not damaged due to patterning, high-density wiring is also possible. The metal used for electrode extraction and wiring is A.
n, An-5i, An-Cmyu, AffSi-・TiA
Alloys containing Aff such as n, An-5i-Cu, etc.
Cu, Mo, W, or (6 gold) can be used.Especially, when filling the inside of the contact/tact hole for electrode extraction 1, it is preferable to use the Ajll!-CVD method described later. C.I. As an insulating film, then CVI
) method and sputtering method (41 types of inorganic materials such as silicon oxide film, silicon nitride film, PSG (silicate glass) film, BPSG (borophosphorus silicone glass) film, and polyimide film. The first material is preferably used.For forming the wiring layer on the insulating film 1, CVD
After forming a metal layer on the entire surface of the insulating film by a method such as a method or a sputtering method, it may be patterned into a predetermined wiring shape (by photolithography), or a predetermined portion of the surface of the insulating film may be exposed to plasma in advance. Modified with 1,
The metal may be selectively deposited only on the modified surface area. At least 40 mm as a step for the alignment mark.
It is preferable that there is a level difference of about 0 people by an amount J-. stomach. It is more preferable (2, or 50[) great favors.' (Formation))2) The film forming method suitable for forming the electrode according to the present invention will be explained below. This method is a film forming method suitable for burying a conductive material into the opening in order to form an electrode having the above-mentioned structure. Using aluminum hydride gas and hydrogen gas, it is deposited on an electron-donating substrate by a surface reaction to form a layer (hereinafter referred to as 1"l!, -cVlj). In particular, monomethylaluminum, ::ram hydride (MMAH), or dimedylaluminum hydride (DMAHI) is used as the raw material gas, and the substrate surface is heated with a stiff mixed gas using H. gas as the reaction gas. It is possible to deposit a good quality A°C film.
During selective deposition of Aβ, it is preferable to maintain the surface temperature of the substrate at 1-450τ′ below the decomposition temperature of the alkyl aluminum hydride by indirect heating or indirect heating.
more preferably;) 60X'□ or more and 440°C or less. Heat the substrate to the above temperature range as much as possible.
Although there are direct heating and indirect heating, in particular, if the substrate is kept at a temperature of 1-7 degrees by direct heating, a high-quality AI film can be formed at a high piecing rate. For example, if the substrate surface temperature during Ap film formation is set to 260"C to 440C, which is a more preferable temperature range, 300 people.
A high quality film can be obtained at a deposition rate higher than that of resistance heating at 5,000 people/min. Examples of this method of direct heating (J, energy from 1,000 tons of heating is transferred to the p-contact substrate and heats the substrate itself) include lamp heating using a halogen lamp, a xenon lamp, or the like. 4. The method of indirect heating is resistance heating, in which one is installed in the space for forming the deposited film to support the substrate on which the deposited film is to be formed, and a heating element etc. is provided on the substrate support member. It is possible to do this by using
If the CVD method is applied to a substrate in which surface portions of Aβ and V coexist, a single crystal of Jfi will be formed with good selectivity only in the substrate surface portion of electrons, molecules, and sex. The material is excellent in all the properties desired as an electrode/wiring material.In other words, it achieves a reduction in the probability of hillock occurrence and a reduction in the probability of alloy spike occurrence. High-quality AQ can be selectively formed on the surface of any N' conductor or conductor, and ■
Since Afi has excellent crystallinity, it is considered that formation of alloy spikes due to eutectic reactions with silicon, etc., is hardly observed or is extremely rare. Conventionally, it has been considered that the material is employed as an electrode of a semiconductor device. It is possible to obtain effects that were not expected with conventional technology, which goes beyond the concept of one electrode. As shown in J- below, the surface of 13 electrons, for example, the insulating core 1, is deposited in the opening where the surface of the semiconductor substrate is exposed.
He explained that Aff has a single-crystal structure, but according to this AJ2-CVD method, it is possible to selectively deposit the following metal film containing l as a single component, and the quality of each film can be improved. It shows excellent properties. Tatoriba, alkyl aluminum hydride. In addition to gas and hydrogen, sing, Si, J', s, 5i31 (8,
5i (cuJ4, 5iCff+, si+-12cg
Gas containing 81 atoms such as z, 5tHCff n, T
xCffs, , Ti, Br4. Tl(CH3)
4th grade Q) Ti raw material contains C; gas and bisacetylacetonate! olC11 (CyoH, 02)
, bisdipivaloyl methanite copper CLIFCIllll
1102)2, bishexafluoroacetylacetonatocopper Cu(CsH) eL)2, etc., are introduced in appropriate combinations to create a mixed gas atmosphere, for example /l-5i, Ar- ] “i, Ar-Cu
, /l-3i-Ti, Aj2-5i-Cu, or the like may be selectively deposited to form the electrode. In addition, since the Al-CVD method is the first film forming method with superior selectivity and the surface properties of the deposited film are good, a non-selective film forming method is used in the next deposition process. 5102 by applying a series of selective depositions as an Ar film and a tightening film.
By forming a metal film containing Ar or l as a main component even on soils such as soils, it is possible to obtain a metal film suitable for highly versatile use as wiring for semiconductor devices. Such a metal film is as described above in terms of V-15. Selective stack 15. Ar, Aj2-3i, A, f
! -Ti, Al2-Cu, A7□', -Sj'I
i, Ar2- Deposited non-selectively with Si-Cu and Ar
:5. AF-SiAr-Ti, Ar-Cu, Aj:
! -3i-Ti, Aj7-3i Cu, etc. The film formation method is used for non-selective deposition, and the steps are as follows:
=AI-CV Shino! There are other methods such as CVD method and sputtering method. (Film Forming Apparatus) Next, a film forming apparatus suitable for forming the electrode according to the present invention will be described. FIGS. 2 to 24 show an apparatus for continuously forming a metal film suitable for applying the film forming method described in 1.13 in an R-frame format. As shown in Fig. 2, this metal film continuous forming apparatus consists of a loading chamber 311 which is connected to a load chamber 311 which is connected to the outside air by means of gate valves 310a to 31Of. , a CvD reaction chamber 312 as a first film forming chamber,
It consists of an Rf etching chamber 313, a sputtering chamber 314 as a second film forming chamber, and a load rUtching chamber 315, and each chamber is connected to an exhaust system 316a-3.
16e so that the pressure can be reduced. Here is the previous BE! The load lock chamber 311 is a chamber for replacing the substrate atmosphere before the deposition process with l(2 atmosphere) after exhausting it in order to improve the throughput property.Next Q]C
The VD reaction chamber 312 is a chamber in which selective deposition is performed on the substrate 1 at normal pressure or under reduced pressure (1-1) using the Al-CVD method described above.
A base boulder 318 having a heating resistor 317 that can be heated in the range of T is provided inside, and a bubbler 319 is installed inside the room by a CVD source gas introduction line 319.
A raw material gas such as alkyl aluminum hydride which has been vaporized by bubbling with hydrogen is introduced through the gas line 319, and hydrogen gas as a reaction gas is introduced through the gas line 319. The next Rf etching chamber 313 is a chamber for cleaning (etching) the surface of the substrate after selective deposition in an Ar atmosphere, and inside there is a substrate holder 320 that can heat the substrate at least in the range of 100°C to 250°C. Electrode line 3 for Rf etching
21 is installed, and Ar gas supply line 3 is also installed.
22 are connected. Next sputtering chamber 314i: This chamber selectively deposits a metal film 41' on the surface of the substrate by sputtering in an Ar atmosphere.
A base boulder 323 heated in the range of 00''C' to 250℃ is provided with a target electrode 324 to which a sputter target T, 1t324a is attached, and a
An r gas supply line 325 is connected. The last [1
- Drock chamber 315 is a metal film deposition chamber; after completion of the metal film deposition process, the substrate is exposed to the outside air. Another configuration example of a metal film continuous forming apparatus suitable for applying the film method is shown, and the same parts as in the above-mentioned Fig. 2 are given the same reference numerals. The difference is that a halogen lamp 330 is provided as a direct heating means so that the surface of the substrate can be directly heated.For this purpose, the substrate holder 312 is provided with a claw 331 that holds the substrate in a floating state. With this configuration, by directly heating the substrate surface, it is possible to further increase the deposition rate as described above.The metal H continuous forming apparatus with the above configuration is Practically, as shown in FIG. 4, the transfer chamber 326 is a relay chamber, 1' is divided into the load rotor chamber: Hl, CVD reaction chamber 3↑2, Rf etching chamber 313, sputtering chamber 314, and load ℃.
"Tsuku room 315 is connected to Aiou, with a side lever and 1
Qualitatively, it has a wisdom value of T゛. In this configuration, the load lock chamber 31
1 also serves as the 0-lock chamber 315. Said transfer chamber 3
26, as shown in the figure, is provided with an arm 327 as a conveying means that can be fixed and rotated in the AA force direction and extended and contracted in the BB1 direction. 327, the substrate is sequentially moved from the load lock chamber 311 according to the culm as shown by the arrow in FIG. 5 (: V 11.)
chamber 312, Rf etching chamber 313, sputtering chamber 3
14, so that it can be moved continuously into the load rotor chamber 315 without being exposed to the outside air. (Film Forming Procedure) A film forming procedure for forming electrodes and wiring according to the present invention will be described. FIG. 6 is a schematic perspective view τ' for explaining the film forming procedure for forming electrodes and wiring according to the present invention. First, the outline will be explained. 1Hj holes are formed in the insulating film. A prepared semiconductor substrate is placed in a film-forming chamber, and its surface is maintained at, for example, 260°C to 450°C. DMAII gas and hydrogen gas are mixed with pt, -C, and alkyl aluminum hydride. Thermal CV in atmosphere [1 method i' selectively deposits 1 on the exposed part of the cliff conductor in the opening.Of course, as mentioned above, a gas containing SN wire '+- etc. is introduced and AP- A metal film containing l as a main component such as 83 may be selectively deposited.Next, a metal film containing AP or Ajl' as a main component may be selectively deposited by a sputtering method on the AP2 and insulating film 7. The film is selectively formed. After the formation, electrodes and wiring can be formed by patterning the non-selectively deposited metal film into a desired wiring shape. This will be explained in detail with reference to the figure. First, the substrate is prepared. The substrate and the "r:." The 61st ta 1 (A) is a schematic side showing a part of this base. Here, 401 is a single crystal silicon base 7 as a conductive base, and 402 is an insulating film (layer). and 18 are thermally oxidized silicon films. 403 and 404 are openings (exposed parts), each having a different diameter. Referring to Figure 3, the process is as follows: First, the substrate described in 1. is placed in the load rotor chamber 311. Hydrogen is introduced into the load rotor chamber 311 as described above to create a hydrogen atmosphere. The inside of the reaction chamber 312 is approximately 1×1 by the exhaust system 316b.
Vent to 0-'Torr. However, the degree of vacuum in the second reaction chamber 312 is AP2 even if it is worse than I x 10-'Torr.
．． DM bubbled from the 2 gas dryer 319 after the film was formed.
1 to supply the AH gas, L is used for the gear rear gas of the DMAH line. The second gas line 319゛ is H as a reaction gas, and H2 flows from this second gas line 319゛.
The reaction chamber 3 is opened by adjusting the opening degree of a slow leak valve (not shown).
12 to a predetermined value. Typical pressure in this area (about 1.5 Torr is good. DMAI (DMAI) is introduced into the reaction tube from the line. The total pressure is about 1.5 Torr.
Torr, DMA11 partial pressure approximately 5. OX 1O-3
Torr. Thereafter, electricity is applied to the heat lamp 330 to heat the wafer in a curved manner. In this way, A is selectively deposited. After a predetermined deposition time has elapsed, the supply of DMAI (is temporarily stopped. The predetermined deposition time of the l film deposited in this process and ) The time it takes for the thickness of the AP film on the soil to become 2, which is equal to the film thickness of 5ins (thermal oxidation silicon film 2), can be determined in advance by experiment. The temperature is about 270° C. According to the steps up to this point, the l film 405 is selectively deposited inside the openings as shown in FIG. 6fB). The following is referred to as "first film formation for forming an electrode in the contact hole". Said first film formation 1. After that, the CVD reaction chamber 312 is
16b until a pressure of less than 5 x 10'' Torr is reached. At the same time, the Rf etching chamber 31
:3 is evacuated to below 5 x 10-'Torr. After confirming that both chambers have reached the degree of vacuum 1, the gate valve 310C is opened, the substrate is moved from the CVD reaction chamber 312 to the etching chamber 313 by the transport means, and the gate valve 310c is closed. Rf etching′i
11. '313, and is evacuated by the exhaust system 316c until a vacuum level of 131011 Torr or higher is reached above the Rf etching chamber. Thereafter, argon is supplied through the Rf etching argon common supply line 322, and the Rf etching chamber 313 is maintained in an argon atmosphere of 10'' = ~1 O-a Torr.The Rff etching substrate holder 320 is maintained at about 200°C, and the I'tf etching 7. Supply 1.00W of Rf power to the electrode 321 for about 60 seconds.
, an argon discharge is generated in the Rf etching chamber 313. In this way, the surface of the substrate can be coated with argon (7) to remove unnecessary surface layers of the CVD-deposited film.The etching depth in this case is approximately 10 mm (equivalent to oxide). In this case, the surface layer of the CVD film on the substrate transported in a vacuum is coated with the popular oxygen solution. Since R1 is not calculated by 6, R1
Egging 1] I can't beat it again. place name,
Rf! - Tsuching v3x3 is CVD li reception room 12
The temperature difference in the sputtering chamber 314 functions as a temperature changing chamber for changing the temperature in a short period of time. , the inflow of argon is stopped, and the argon in the Rf etching chamber 313 is exhausted. The upper part of the Rf etching chamber is evacuated to 135 x 10'' Torr, and the sputtering chamber 314 is evacuated to below 5 x 10'' Torr. After that, the gate valve 310d is opened.Then, the substrate is moved from the Rf etching chamber upper part 13 to the sputtering chamber 314 using a transport means, and the zegate valve 310d is closed.The substrate is transported to the sputtering chamber 314, and then the sputtering chamber 3
14 to the Rf etching room, io1 to 313 and 111]
The temperature of the substrate holder 323 on which the substrate is placed is set to 200-25.
Set it to about 0℃. Then, discharge argon with DC power of 5 to 100 kW, and discharge An or Ani-5i (
Scraping a target material such as Si (0.5%) with argon ions 1. 1000% of metal such as or Aj2-Si on the substrate.
The film is formed at a deposition rate of about 0 people/minute. This step is the first non-selective deposition. This is called the second film forming step for forming wiring to connect to the electrode. After forming about 5,000 metal films on the substrate, the inflow of argon and the application of DC power are stopped. The rotator chamber 311 is evacuated to below 5 x 10'' Torr. After that, the gate valve 310e is opened. Move the substrate. After closing the gate valve 310e, open the flow gate 1-valve 310f and take the substrate out of the device. According to the second Aβ film deposition process described below, an Aρ film 406 is formed on the 5i02 film 402 as shown in FIG. Wiring in the desired shape can be obtained by patterning as shown in Fig. 6 (D). We will explain on the basis of experimental results how good the film deposited on the substrate is. First, we thermally oxidize the surface of an N-type single crystal silicon wafer as a substrate to form 8,000 5iOz.
A plurality of holes were prepared in which a single Si single crystal was exposed by patterning apertures of various diameters from O, 25 μm square to lODμrn x 100 μv square. (Aβ film was formed on these samples by the Al-CVD method under the following conditions. DMA was used as the source gas) I, as the reaction gas,
hydrogen, total pressure 1.5 Torr, DMA8 partial pressure 5. Under the common conditions of OXl and 0'''3 Torr, adjust the amount of electricity applied to the halogen lamp and heat it directly!
From this, film formation was performed while setting the substrate surface temperature in the range of 200°C to 490°C. The results are shown in Table 1. (Margins below) As can be seen from Table 1, when the surface temperature of the substrate is 260°C or higher by direct heating, 3000-5000% of Ag is deposited in the openings.
It was selectively deposited at a high deposition rate of 1 person/min. When we investigated the characteristics of the Ag film inside the openings when the substrate surface temperature was in the range of 260°C to 440°C, we found that it contained no carbon, had a resistivity of 2.8 to 3.4 μΩl, and a reflectance of 91]-95. %, 1
It was found that the hillock density of 0 to 10 μm or more was good, with almost no spike occurrence (probability of failure of a 0.15 μm junction). On the other hand, when the substrate surface temperature is 200°C to 250°C, the pattern becomes 260°C and r at 1 compared to 440°C.
(Although it is bad, it is a fairly good film compared to the conventional technology, but the deposition rate was 1000 to 1500 sheets/min, which was not high enough, and the throughput was 7 to 0 sheets/h, which was relatively low.) Furthermore, when the substrate surface temperature is 450°C or higher, the reflectance is 60% or less, and the hillock density of 1 μm or more is 10 to 10'.
en+-', alloy spike generation is 30% to O, Ag in the pores, and membrane sheathing are low F and 1. Next, it will be explained how the above-mentioned strength can be suitably used for opening contact holes and through holes. That is, it is preferably applied to contact hole/through hole structures made of materials described in T. below. A film was formed on a substrate having the structure described below under the same conditions as when forming sample 1 on sample 1-1 described above. 1 of single crystal silicon as the first substrate surface material,
A silicon oxide film was formed using CVN droplets as the second substrate surface material, and buttering was performed by photolithography to partially expose the single crystal silicon surface. Oxidation S j, 0 *The thickness of the film is 8000 mm, and the size of the exposed part of the single crystal silicon (open) is 0°2
5μ [Xo, 25μσ1~100μm X 100μ
I did it at m. In this way, Zumburu 1-2 was prepared. (Hereinafter, refer to this sample as “CVD5i (h
(hereinafter abbreviated as SiO2)/single-crystal silicon), Sample 1.-3 is a boron-doped oxide film (hereinafter abbreviated as BSG)/single-crystal silicon, Sample 1. Sample 1-4 is a phosphorus-doped oxide film (hereinafter referred to as -F'PSG)/single-crystal silicon film formed by normal pressure CVD, and sample 1-5 is a phosphorus- and boron-doped oxide film formed by normal pressure CVD. (hereinafter abbreviated as BSPG 1)/single crystal silicon, sample 1-6 is a nitride film (hereinafter referred to as 1"P-3iN")/single crystal silicon, sample 1-6 is a nitride film formed by plasma CVD (hereinafter referred to as 1"P-3iN")/single crystal silicon, sample 1-6. Sample 7 is a thermal nitride film (hereinafter abbreviated as LP-3iN)/monocrystalline silicon, Sample 1-8 is a nitride film (hereinafter abbreviated as LP-3iN)/W crystal silicon, and sample 1-8 is a film formed by low pressure CVD. Reference numeral 1-9 is a nitride film (hereinafter abbreviated as ECR-3iN)/single-crystal silicon formed and deposited using an ECR apparatus. Furthermore, samples 1-11 to l-179 (note: sample number 1-1
0.20.30.40.50.60.70.80.90
,! , 00 , 110 , 1.20 , 130 , 14
0, 150.160.170 are missing numbers). The first substrate surface material 2 includes single crystal silicon (single crystal Si), polycrystalline silicon (polycrystalline Si), amorphous silicon (amorphous S1), tungsten (W), molybdenum (Mo), tantalum ( Ta), tungsten silicide (WSi), titanium silicide (1'1Si),
Aluminum (Aff), aluminum, rubber silicon (Aff)
g-3i), titanium aluminum (8β-Ti)
, titanium nitride (Ti-N), Cu (Cu),
Aluminum silicon copper (Ag-5i-Cu), aluminum palladium (1-Pd), titanium (Ti),
Molybdenum silicide (Mo-3i) and tantalum silicide (Ta-3j) were used. The second substrate surface material includes T-Sj, 0□, SiO□, and BSG. PSG, BPSG, P-3iN, T-5iN
, LP-3iN, ECR-Sj,N. Sample 1- as mentioned above for all samples such as edge soil.
A good Ag film comparable to No. 1 could be formed. Next, Aρ was selectively deposited on the substrate on which Aρ was selectively deposited as described in 1 above, and Aρ was selectively deposited using the sputtering method described above, and patterning was performed. As a result, the Aj2 film produced by the sputtering method and the Hep film selectively deposited inside the openings have good electrical and mechanical durability due to the good surface properties of one film inside the openings. It's a high level of contact. (Hereinafter, blank spaces) A method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIG. 7. First, a thermal oxide film 2 made of silicon oxide is formed by the CVD method on the surface of a semiconductor substrate 1 made of silicon on which a functional element such as a MOS transistor or a piezoelectric transistor is formed. A non-oxidizing film 3 such as a silicon nitride film was laminated on a predetermined region of the substrate by CVI method (see FIG. 7(A)). Next, for the thermal oxide film 2 and non-oxidizing film 3 described in
Perform selective oxidation to form thermal oxide film 2 and field oxide film 4
formed an area of Additionally, the non-oxidizing lI# knee 1 and the thermal oxide film 2 below it were removed and reoxidized to form a gate oxide film 5 region. Further, a polysilicon film (not shown) was laminated on a predetermined region of this gate oxide film 5, and then ions were implanted through resist patterning and heat treated to form a diffusion layer 6 (see Fig. 7). (See FB). Next, an interlayer insulating film 7 was formed on the entire surface layer of the semiconductor substrate j by the VD method (see FIG. 7(C)).
This is provided for electrical isolation from the VD film. Next, the glabellar insulating film 7 is coated with contact butter and a contact hole 8 is opened as an opening for taking out the electrode so that the diffusion layer 6 is exposed, and at the same time it reaches the inside of the field oxide film 4. A parent mark portion 9 as a stepped portion was formed (see FIG. 7fD). Next, Aρ-Si is selectively deposited in the 'T,':1 contact hole 8 by the selective deposition method described above, and the first wiring pattern 10 as a conductor is formed so that its upper surface is the glabella insulating film 7. (See Figure 7 (E))
. Next, the entire surface layer of the semiconductor substrate 1 (Zunao) is also subjected to RF plasma treatment on the first wiring layer 10, interlayer insulating film 7, and inside the parent mark portion 9, and then non-selectively treated by sputtering or the like. Aj2-8i is deposited and patterned to form a conductive layer (see FIG. 1 to form a second wiring layer 11). This connection, the parent mark part 9 as a stepped part
The concave shape was reflected on the second wiring layer 11(7), . This recess 11a is irradiated with a laser beam, the reflected signal is detected, and the rJ moving knife 2 is combined to apply wiring layer butter to the second wiring layer 11.・The semiconductor substrate 1 is formed exactly as shown in FIG. In the embodiment described above, before forming the second wiring layer 11 on the soil of the interlayer insulating film 7, the surface of the interlayer insulating film 7 is smoothed by 5OG (spin on glass).
Law J, ddeq, jl' 3 chemical 11 chemical engineering 1 is also good. That is, using a spin coater, apply a solution of a silanol compound in an organic solvent (alcohol, ketone, etc.) at a rotational speed of 3.00.
0-6,. Apply for 15-30 seconds with 000 rpm+2
At the time of spin coating, back-rinsing with isopropyl alcohol is performed, and after coating, the semiconductor substrate is heated to 80 to 200'C for 1 to 3 minutes using a Bodbur L/-h and subjected to low-temperature baking at 17. By performing such a treatment, unevenness on the surface of the interlayer insulating film can be improved.1. , t is almost gone,
Since a flat surface can be obtained, there is no possibility of an increase in resistance due to unevenness or breakage of steps in the second wiring layer ↓ζ. FIG. 8 is a schematic cross-sectional view showing another preferred embodiment of the present invention. In the semiconductor device shown in FIG.
is a semiconductor substrate made of silicon or the like on which functional elements such as bipolar elements are formed. This semiconductor substrate 12
An oxide film 13 is formed on the main surface of the oxide film 13.
A diffusion layer 14 is formed in the semiconductor substrate 12 below a predetermined region of the semiconductor substrate 12 . Above this diffusion layer 14, an oxide film 1
A contact hole 15 is formed by etching or the like to expose the soil portion of the diffusion layer 14. This contact hole 15 has a lower part 1.5 with a small planar area and whose bottom surface is the soil surface of the diffusion layer 14.
a, and a lower part 15b having a large planar area including the two edges of the lower part 15a on its bottom surface. Further, in a predetermined region of the oxide film 13, a parent mark portion 16 is provided as a step portion formed by etching from the main surface of the oxide film 13 to the inside. Inside the lower blade part 15a of the contact hole 15 mentioned above, a conductive material such as β can be selectively deposited up to the upper edge of the square part 15a by the selective deposition method described above. A first wiring layer j7 for taking out the formed electrode is provided. This first wiring layer 17 and oxidation Ill! 13 and inside the parent mark portion 16, a conductive material is deposited by a non-selective deposition method.
A wiring layer 18 is provided. of this second wiring layer 18.
-, an upper portion 19 is formed on the + side of the contact ball 15, and a recess 20 is formed in the parent mark portion 16. Therefore, in this example, the parent mark portion 1G
The recess 20 as a step corresponding to the shape of the recess 1. Like la, it can be used as a reference mark for automatic mask alignment in wiring layer patterning. Here, a method for manufacturing the semiconductor device shown in FIG. 8 will be briefly described with reference to FIG. 9. First, after forming a thermal oxide film 13 with a predetermined thickness on the main surface of the semiconductor substrate 12, resist patterning is applied to a predetermined region of the oxide film 13, and after ion implantation and heat treatment, an enlarged @M14 is formed. did. Next, the oxide film 13 is subjected to first contact patterning 7 to form a shallow opening 15c in a predetermined region of the oxide film 13 below the diffusion layer 14, and at the same time, a shallow opening 15c is formed in a predetermined region of the oxide film 13. Same depth as 15c
A recess 16 having a depth was opened (see FIG. 9(A)).
. Next, a second contact patterning process is performed on the oxide film 13, and the bottom surface of the opening 15 is etched to expose the diffusion layer 14, thereby forming the contact hole 1 as an opening.
Form the T force part 15a of No. 5, and at the same time open the gap 1 part 15c] Etch the periphery of the edge and make a contact hole.
A 5" cubic portion 15b was formed (see FIG. 9fB)). Next, the contact hole 1 is formed by the selective deposition method described above.
5 selectively deposits Al2-5i in the lower blade part 15a of
J, which is flush with the bottom surface of 5b, was formed (Fig. 9 (
C) 9). Next, after performing RF Buchsma treatment on the entire surface layer of the semiconductor substrate 12, that is, on the oxide film 13 and the first wiring layer 17 in the contact hole 15 and inside the parent and mark portions 16, the portion to be treated is subjected to sputtering, etc. Aff-5i was deposited non-selectively using the method, followed by patterning 2 to form a second wiring layer 18 as a conductor layer 7 (see FIG. 8). As a result, the concave shape of the parent mark portion 16 as a step portion was reflected on the upper surface of the second wiring layer 16, and a recess 20 as a first step portion was formed. The recess iiJ'i 20 was irradiated with L/- laser light, the reflected signal was detected, automatic mask mounting was performed, and wiring layer patterning was performed on the second wiring layer 16, resulting in a promising wiring pattern. precisely the semiconductor substrate 12
could be formed on top of. FIG. 10 is a schematic sectional view showing another preferred embodiment of the present invention. In the single conductor device shown in FIG. 10, or unlike the configuration of the above-described embodiment, the planar area of the parent mark portion 30 as a stepped portion is replaced by the contact hole 31 as an opening.
Form larger than the plane area of. It has a two-dimensional configuration. This takes advantage of the size dependence of the growth rate, which is a feature of selective metal deposition technology. In other words, when selective deposition techniques are used to deposit metal into holes of different sizes, the rate of metal growth into holes with smaller sizes is lower than the rate of metal growth into holes with larger sizes.
This method takes advantage of the phenomenon that the speed is relatively slow compared to 1. In this example, the metal acid growth rate on the parent mark portion 30 is slower than the long rate (relative to the metal growth rate on the J contact hole 31).Here, with reference to FIG. A method for manufacturing the semiconductor device shown in Fig. 10 will be briefly explained.A thermal oxide film 32 is formed on the main surface of the cliff conductor substrate 1, and then ion implantation and heat treatment are performed on the τ diffusion layer 6 by resist buttering. formed (
(See FIG. 11(A)) 6 Next, a glabellar insulating film 33 is deposited on the thermal oxide film 32 2 and heat treated 7 , and then contact holes 3 are formed by contact buttering and etching.
1 and the parent mark portion 30 are formed so that the parent mark portion 30 is larger in plan area than the contact hole 31 (see FIG. 11(B)). Next, Aρ-Sj was deposited on these parent mark portions 30 and contact holes 31 by a selective deposition method. This deposition1. The process was stopped at the time when the interlayer insulating film 33Q) soil surface and the wiring layer 2 as a conductor for taking out the electrode formed on the contact pole 31; Now, due to the size dependence in the selective deposition method described in 1-1, the metal film 35 deposited within the parent mark portion 3()
4 does not reach one upper surface of the interlayer insulating film 33, and the metal film 35 has a concave shape relative to the insulating film 3:3 (see FIG. 11(C)). With this tl, it is possible to use the ``-'' plane of the wiring layer 34 and the 1'' plane of the interlayer insulating film 33 at the contact portion on the side where the electrode is taken out.
The concave shape of 0 can be used as a reference mark for mask alignment in patterning a wiring layer. Next, the entire surface of the semiconductor substrate in the state shown in FIG.
A wiring layer 36 as a conductive layer is formed by depositing the same. As a result, the concave shape of the parent mark part 30 as a step was reflected on the surface of the wiring layer 36, forming a recess 37 as a step (see FIG. 10). Laser light was applied to this recess 37. 2, the reflected signal was detected, automatic mask alignment was performed, and wiring layer patterning was performed.As shown in FIG. It was possible to form a + of 1. [Effects of the Invention] As explained above, the present invention enables novel CVD
Since selective metal deposition technology is used, it is possible to form a conductor by selectively depositing a conductive material only in the openings where the surface of the conductive base is exposed. By forming a conductive layer using a non-selective deposition method on the soil at the stepped portion formed on the insulating film on the conductor and on the -1 ground surface, the resulting conductive layer A portion corresponding to the shape can be formed. By using this portion as a mark for mask alignment, it becomes possible to faithfully form a wiring pattern of a desired shape using, for example, art alignment when patterning the conductor layer.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view illustrating a preferred embodiment of the present invention; FIGS. 2 to 5 are views showing an example of a manufacturing apparatus preferable to apply the method of manufacturing a 1' conductor device according to the present invention; FIG. 6 is a schematic cross-sectional view for explaining how wiring layers are formed by the method of manufacturing a semiconductor device according to the present invention. FIG. 8 is a schematic sectional view showing a second embodiment of the present invention; FIG. 9 is a schematic sectional view illustrating the manufacturing method of the semiconductor device shown in FIG. 8; FIG. 11 is a schematic sectional view showing a third embodiment of the present invention. FIG. 11 is a schematic sectional view illustrating a method for manufacturing the semiconductor device shown in FIG. 10. DESCRIPTION OF SYMBOLS 1... Semiconductor base (conductive ground), 2... Oxide film, 3... Non-oxidizing film, 4... Field oxide film, 5... Gate oxide film, 6... Diffusion Layer, 7... Interlayer insulating film, 8... Contact hole (opening), 9... Parent mark part (step part), 10... First wiring layer (conductor), 11... 2nd wiring N (conductor layer), 1.1a... recess (step), 12... semiconductor substrate (conductive base), 13... oxide film, 14... diffusion layer, ]5 ...Contact hole (opening), 15a...Lower blade part, 15b...Upper part, 1.5e...Open (] part, 16...Main mark part (step part), 1st FIG. 17: first wiring layer (conductor), 18: second wiring layer (conductor layer), 19: recess), 20: recess (step), 30: Parent mark part (step part), 31... Contact hole (opening) 32... Thermal oxide film, 33... Interlayer insulating film, 34... Wiring layer (conductor), 35... Metal Film, 36... Wiring layer (conductor layer), 37... Recess (step). Figure 4 Figure 5 (A,) Figure (zo/11) □゛・1 (C) Figure (zoρ2) Figure Figure 10

Claims (1)

[Claims] 1) In an alignment method for a semiconductor device in which a conductive thin film is formed on a conductive base surface via an insulating film, the step of forming an opening in the insulating film through which the base surface is exposed. forming a stepped portion in the insulating film where the base surface is not exposed; selectively depositing a conductive material in the opening; and forming the conductive thin film on at least the insulating film. An alignment method comprising: performing alignment using the stepped portion. 2) A method for manufacturing a semiconductor device having a wiring layer provided on a conductive base surface via an insulating film, comprising: forming an opening in the insulating film through which the base surface is exposed; forming an unexposed stepped portion on the base surface; selectively depositing a conductive material in the opening; and depositing a conductive thin film for forming the wiring layer on at least the insulating film. A method for manufacturing a semiconductor device, comprising: a step of forming the wiring layer; and a step of patterning the conductive thin film to form the wiring layer. 3) The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming the wiring layer is performed by a CVD method using alkyl aluminum hydride gas and hydrogen gas. 4) The method for manufacturing a semiconductor device according to claim 3, wherein the alkyl aluminum hydride is dimethyl aluminum hydride. 5) In a semiconductor device in which a conductor layer is formed on a conductive base surface via an insulating film, a conductor formed in the insulating film and in an exposed opening on the base surface; A step portion formed on an insulating film and not exposed on the base surface, and a conductive layer formed on the insulating film, and the conductive layer is provided with a step corresponding to the step portion. A semiconductor device characterized by: 6) The semiconductor device according to claim 5, wherein the conductor is made of single crystal Al.