GB2332077A

GB2332077A - Circuit for the indication of the operating states of an appliance

Info

Publication number: GB2332077A
Application number: GB9903776A
Authority: GB
Inventors: Dietmar Traeger
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1996-08-20
Filing date: 1997-08-18
Publication date: 1999-06-09
Anticipated expiration: 2017-08-18
Also published as: DE19633550A1; WO1998008057A1; JP2001500253A; JP3535523B2; GB9903776D0; GB2332077B; USRE38184E1

Abstract

Disclosed is a circuit, which by means of at least 2 input signals produces exactly 3 output signals, whereby two of the output signals shine constantly in an activated state and the third output signal shines constantly or flashes in an activated state. Each time exactly one of the three output signals is activated.

Description

2332077 Circuit arrangement for the indication of operating states of a device is The invention relates to a circuit arrangement for the indication of operating states of a device.

Modern manufacturing processes in most cases today run in a highly automated manner. In this connection, however, it is often necessary to remove the intermediate products, which are formed at the individual manufacturing stages and are to be processed further, from a device, transport them on and load a device downstream in the manufacturing process with them. This applies in a similar manner to the start and the end of a process: the device used as the first machine in the manufacturing process must be loaded and the device used as the last machine in the manufacturing process must be unloaded. Furthermore, random tests are also often carried out on the respective intermediate products between two stages of manufacture, for example in order to be able to guarantee the quality of the products to be produced and/or to be able to establish whether any departures from requirements have occurred in the manufacturing process.

What is common to all of these procedures is that it is necessary to be able to make certain operating states, in which the respective devices are found apparent in some form, for example in the form of visual and/or audible signals for operating personnel or in the form of electric signals which can be automatically processed further, for example by means of linked computers or controls for further devices.

The object of the present invention is to provide a circuit arrangement of the generic type that detects operating states of a device and provides information about these operating states in a suitable manner for further use.

This object is achieved by means of the features of claim 1. Advantageous configurations and further developments are characterised in the subclaims.

In the case of the circuit arrangement in accordance with the invention it is advantageous to be able to use signals that are already present in that device whose operating state is to be detected as input signals of the circuit arrangement. Furthermore, it is advantageous to be able to indicate the operating state as simply as possible. For the purposes of indication, in this connection it is possible to use further devices, such as, for example, a computer, acoustic devices, such as horns, or else optical devices, for example in the form of traffic lights. The latter case serves in particular to provide information for operating, maintenance and/or repair personnel.

The invention is explained in greater detail in the following with reference to a drawing, in which Figure 1 shows the circuit arrangement C in Figure 2 Figure 3 accordance with the invention having an indicating unit Lp connected thereto; shows a possible embodiment of the circuit arrangement C in accordance with Figure 1; shows a timing diagram which, in an exemplifying manner, represents the input and output signals of the circuit arrangement C in accordance with the invention and their relationship with each other.

The circuit arrangement in accordance with the invention. diagrammatically represented in Figure 1 as circuit arrangement C, uses two input signals AUTO and PIEPS. At its outputs it provides three output signals Al, A2, A3 which can be fed, for example, to an indicating unit Lp in the form of traffic lights, the lights gn, rt, ge of which light up in accordance with the output signals Al, A2, A3. A possible characteristic of the input and output signals AUTO, PIEPS, Al, A2, A3, assumed for this exemplary embodiment, is diagrammatically represented in Figure 3. Neither the time characteristic of the signals nor their electrical levels are shown to scale.

The possible embodiment of the circuit arrangement C of Figure 1 shown in Figure 2 has a first and a second inverter Il, 12, which are arranged between the one input signal AUTO and a first NAND gate N1, so that a first input of the first NAND gate N1 is connected to the output of the second inverter 12. The first output signal Al is formed at the output of the first NAND gate N1.

A third and a fourth inverter 13, 14 are arranged between the other input signal PIEPS and a second input of the first NAND gate N1. A second NAND gate N2, at whose output the second output signal A2 is formed, is connected at a first input to the second input of the first NAND gate N1. A second input of the second NAND gate N2 is connected to a first circuit branch-point K1 which lies between the first two inverters Il, 12.

A second circuit branch-point K2, which lies between the third and the fourth inverter 13, 14, is connected to a first input of a third NAND gate N3.

The third output signal A3 is formed at the output of the third NAND gate N3.

A fourth NAND gate N4 with two inputs is likewise connected, at its one input, to the first circuit branch-point K1, whilst its other input is connected to an oscillator circuit arrangement Osc, for example a flashing-unit circuit arrangement. The output of the fourth NAND gate N4 is connected to a second input of the third NAND gate N3.

The assumption is made (in an arbitrary manner) that the one input signal AUTO is always in its active state (denoted with "1" in Figure 3) if the device, whose operating state is to be indicated, is starting its regular operation (for example as a result of manual actuation of a starting button or similar) and only then enters its inactive state (denoted with "0" in Figure 3) either when the device has come to the end of its planned operating steps in a regular manner or if as a result of intervention from outside (for example by maintenance personnel) the regular operation is aborted. For the other input signal PIEPS it is assumed that it is always inactive (denoted with "0" in Figure 3) except in the following two cases:

a) an error occurs in the sequence of operations of the device, or b) the planned operating steps have been terminated in a regular manner. The other input signal PIEPS exhibits its activated state (denoted with "1" in Figure 3) in these two cases.

It is assumed for the output signals Al, A2, A3, for example, that they activate lights gn, rt, ge of an indicating unit Lp, in which case the first output signal Al activates the light gn, the second output signal A2 activates the light rt and the third output signal A3 activates the light ge. On the basis of the embodiment of the circuit arrangement C in accordance with Figure 2 that is taken as an example, the effective values Veffl, Veff2, Veff3, Veff4 mentioned below with regard to the activated states H of the output signals Al, A2, A3 are constant electric potentials. Since, however, configurations of the circuit arrangement C are also possible in which the 1 output signals Al, A2, A3 could, for example, be pulse code or frequency- modulated signals, the activated states H are termed effective values Veffl,..., Veff4.

Figure 3 shows the signal characteristics at the inputs and the outputs of the circuit arrangement C in the case of an assumed process run and also, with regard to the indicating unit Lp, which of the lights is activated and caused to provide an indication on the basis of the output signals.

At the beginning of the process run, the one input signal AUTO is activated ("V') and the other input signal PIEPS is deactivated ("0".) This situation corresponds to a regular operation of the device, whose operating state is to be indicated.

On the basis of the circuit arrangement shown in Figure 2, the first output signal Al exclusively exhibits its activated state H with a first effective value Veffl, which is greater than a first reference potential Refl, and exclusively the green light gn lights (in continuous operation) as long as nothing changes with respect to the state of the two input signals AUTO, PIEPS. Let it be assumed that then, however, a disturbance of some kind occurs at the device and this is recognized by the device. Whilst the one input signal AUTO remains activated without change ("1"), the other input signal PIEPS is now also activated ("1") so that both input signals AUTO, PIEPS are activated. In this case, the first output signal Al is in a deactivated state L; the green light gn goes out. The second output signal A2 is in an activated state with a second effective value Veff2, which is greater than a second reference potential Ref2, and exclusively the red light rt lights, since the third output signal A3 maintains its deactivated state L.

If now, for example, a maintenance engineer in order to eliminate the disturbance puts the device into a state which can be termed "stand-by", "manual operation" or similar (that is, if he terminates the automatic operation of the device in a controlled manner), then both input signals AUTO, PIEPS become inactive ("0"). In this case, the first output signal Al maintains its deactivated state L, the second output signal A2 enters its deactivated state L and the third output signal A3 assumes its activated state H.

on the basis of the generation of the third output signal A3 shown in Figure 2 with the aid of the third NAND gate (N3) and the fourth NAND gate (N4) and also the oscillator circuit arrangement Osc, the third output signal A3 in this case has a third effective value Veff3 which lies above the value of a third reference potential Ref3. The third reference potential Ref3 is rated so that the light ge lights if the third output signal A3 has an effective value which is greater than the third reference potential Ref3. This means therefore in concrete terms that (exclusively) the amber light ge lights in an uninterrupted manner (the oscillator circuit arrangement Osc in this case has no effect upon the third output signal A3) as long as the state described persists.

If now at the end of this maintenance or repair work the device resumes its process, its regular process run, (as a result of a key "start", "automatic" or similar being pressed), the one input signal AUTO (again) assumes its active state "1", whilst the other input signal PIEPS remains inactive ("0"). As a result, the third output signal A3 is also deactivated (state L); the amber light ge goes out. Whilst the second output signal A2 remains deactivated (state L), the first output signal Al is (again) activated (state H) so that now exclusively the green light gn lights.

After a disturbance-free run of the process that takes place in the device, at the end of this process the first input signal AUTO enters its inactive state 0, whilst the second input signal PIEPS enters its active state 1. Consequently, the first output signal Al in turn assumes its deactivated state L, whilst the already existing deactivated state L of the second output signal A2 is maintained. The third output signal A3, on the other hand, assumes its activated state H. Given this constellation of the input signals AUTO, PIEPS, in contrast with the case described before ("stand-by-operation"), in which the amber light ge lights in an uninterrupted manner, now the oscillator circuit arrangement Osc has an effect upon the activated state H of the third output signal A3 so that in a first time segment Tl it has the third effective value Veff3, whilst subsequently for a second period of time T2 it has a fourth effective value Veff4 which lies below the value of the third reference potential Ref3 (typically the value of the reference potential of the whole circuit arrangement, mostly equal to earth). The amber light ge thus goes out. At the end of the second time segment T2, the activated state H of the third output signal A3 again assumes the third effective value Veff3 for the duration of the first time segment T1, then subsequently in turn the fourth effective value Veff4 for the second time segment T2, and so on. The length of these two time segments T1, T2 is determined or can be determined by the frequency of the output signal of the oscillator circuit arrangement Osc. This activated state of the third output signal A3, which causes the amber light ge to flash, persists as long as nothing changes with respect to the state of the two input signals AUTO, PIEPS. The first three effective values Veffl, Veff2, Veff3 of the activated states H of the three output signals Al, A2, A3 can all be different or be different in part from each other. They can, however, in accordance with the invention also be equal in part or else all be equal.

Accordingly, the reference potentials Refl, Ref2, Ref3 can also be equal in part or all be equal. Furthermore, it is advantageous that each of the two time segments Tl, T2 in each case persists for at least so long until an indicating device Lp linked up to the third output signal A3 can reliably recognize and indicate the respective presence of the third and fourth effective values Veff3, Veff4. This is important in particular if the indicating unit Lp is in the form of traffic lights with indicating lights, the indicators of which can be noted by human beings ("inertia of the human eye").

Claims

1. Circuit arrangement for the indication of operating states of a device having the following features: - three output signals (A1, A2, A3) having activated states (H) and deactivated states (L) are derived from at least two input signals (AUTO, PIEPS), - in each case precisely one of the output signals (A1, A2, A3) is activated, - the first two output signals (A1, A2) during their activated states (H) in terms of voltage have first and second effective values (Veffl, Veff2) which exceed the value of a respective reference potential (Refl; Ref2) of two given reference potentials (Refl, Ref2), - the third output signal (A3) during its activated state (H) in terms of voltage either has a third effective value (Veff3) which exceeds the value of a given third reference potential (Ref3) or in the activated state (H) during two successive time segments (T1, T2) in the first time segment (T1) has the third effective value (Veff3) and in the second time segment (T2) has a fourth effective value (Veff4) which is below the value of the third reference potential (Ref3), with the first time segment (T1) and the second time segment (T2) being repeated as long as the third output signal (A3) exhibits its activated state (H).

2. Circuit arrangement for the indication of operating states according to claim 1, characterised in that at least two of the first three effective values (Veffl, Veff2, Veff3) are equal.

3. Circuit arrangement for the indication of operating states according to claim 1 or 2, characterised in that at least two of the reference potentials (Refl, Ref2, Ref3,) are equal.

4. Circuit arrangement for the indication of operating states according to one of the preceding claims, characterised in that the two time segments (T1, T2) in each case persist for at least so long that an indicating device (Lp), which can be linked up to the third output signal (A3), can reliably recognize and indicate the respective presence of the third and fourth effective values (Veff3, Veff4).

5. Circuit arrangement for the indication of operating states according to one of the preceding claims, characterised in that the first input signal (AUTO) is connected through to a first input of a first NAND gate (N1) by way of a first inverter (I1) and a second inverter (12), - in that the second input signal (PIEPS) is connected through to a second input of the first NAND gate (N1) and a first input of a second NAND gate (N2) by way of a third inverter (13) and a fourth inverter (14), - in that a first circuit branch-point (K1), which is arranged between the first inverter (I1) and the second inverter (12), is connected to a second input of the second NAND gate (N2), - in that a second circuit branch-point (K2), which is arranged between the third inverter (13) and the fourth inverter (14), is connected to a first input of a third NAND gate (N3), - in that an oscillator circuit arrangement (Osc) is connected in terms of output to a first input of a fourth NAND gate (N4), - in that the first circuit branch-point (K1) is connected, furthermore, to a second input of the fourth NAND gate (N4), - in that the output of the fourth NAND gate (N4) is connected to a second input of the third NAND gate (N3), and - in that the output signals (A1, A2, A3) are formed at the outputs of the first three NAND gates (N1, N2, N3).