JPS60199233A - Counter - Google Patents

Abstract

PURPOSE:To prevent a pulse width from being decreased due to a fault by using an AND operation oscillator not oscillating any output in case of a circuit fault, and inputting an output of each self-hold circuit to the self-hold circuit of the next stage through a delay circuit having a delay time longer than the pulse width of a count input pulse and not causing a fault prolonging the delay time. CONSTITUTION:An output of a pulse generator 1 goes to a high level at fault, no calculation input pulse S3 is generated and the pulse width is not decreased. Furthermore, if a differentiating capacitor C4 inserted to synchronize with the relinquishment of a count instruction signal S0 is an open or short-circuit fault, no synchronizing pulse is inputted or a count input pulse signal S3 is grounded and no count input pulse signal S3 is generated. If a circuit fault takes place in AND oscillators OSC1-OSC3 and rectifier circuits RC1, RC3, no output is generated and then no output is generated to the self-hold circuit of the next stage. Thus, fail-safe is attained.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention provides a system in which the output voltage disappears after a predetermined time after a counting command is issued, and when a circuit failure occurs, the output voltage is not generated or the counting time is shortened. Concerning fail-safe counters. Such a counter is used, for example, in a railroad crossing warning device as a timer to start sounding after a predetermined period of time.

Prior art and its problems As a conventional counter of this type, there is a patent application published in
There is No. 852. However, this prior art has a steering circuit and requires three reconnaissance inputs, which tends to make the circuit configuration complicated.

OBJECTS OF THE INVENTION The present invention provides a counter that can have asymmetric error characteristics in the direction in which counting progresses in terms of output voltage and counting time without requiring a steering circuit or three-value input. With the goal.

In order to achieve the second object of "Configuration of the Present Invention", the present invention has a plurality of self-holding circuits, and on the condition that the output of the self-holding circuit in the previous stage disappears, the counting output voltage of the self-holding circuit in the next stage disappears. By doing this, in a counter that counts human input pulse signals, the self-holding circuit consists of an AND operation oscillator that does not generate an output due to a circuit failure, a rectifier circuit that rectifies the output of this AND operation oscillator, and a rectifier circuit that rectifies the output of this AND operation oscillator. and a delay circuit that is provided at a subsequent stage and does not cause a failure on the side where the delay time is shortened, and is configured to be self-maintained by a signal fed back to one of the input terminals of the AND operation oscillator through the delay circuit. The output of each self-holding circuit is input to the next self-holding circuit through a delay circuit that has a delay time longer than the pulse width of the counter coupler and does not cause a failure on the side where the delay time is extended. It is characterized in that it is counted using a counting human pulse signal whose width is not shortened due to a failure.

Embodiment FIG. 1 is an electrical circuit connection diagram of a counter according to the present invention. In this embodiment, a circuit that operates with a positive power supply is shown, but a circuit configuration that operates with a negative power supply is also possible. RCO is this AND operation oscillator 0
This is a rectifier circuit connected to the output side of 9Go. These circuits are configured so that no output is generated in the event of a failure. Such an AND operation oscillator OSG o and a rectifier circuit RCo are disclosed in, for example, Japanese Utility Model Application Publication No. 57-4764 and Japanese Patent Publication No. 51-382.
It is publicly known in Publication No. 11 and the like. FIG. 2 shows an example of an AND operation oscillator disclosed in these publications, in which transistors ↑rx and Tr2 are directly connected, and the collector of transistor Tr2 is connected to a Zener diode 201.
The connection point between the Zener diode ZD2 and the resistor R3, which is connected to the base of the transistor Trs through the resistor R4 and the collector of the transistor Tra, is connected to the base of the transistor Trx through the resistor R4. Rz, R2
is a collector resistance, A is an input terminal, and B is a power supply input terminal.

In the AND operation oscillator shown in FIG. 2, at the input terminal A,
The Zener voltages VZI and V22 of the Zener diode 201 and Zn2 are Vzl and Vz with respect to the power supply voltage vb.
When a voltage of 2>Vb is input, that is, when the potential at the input terminal A becomes a potential outside the power supply range, the transistors Tr to Tra repeat the on and off operations in sequence, and the output terminal C receives the voltage at the input terminal A. An oscillation output that gradually changes between the applied input voltage level and approximately zero level is obtained. On the other hand, if the input voltage applied to the input terminal A does not reach a sufficient level to operate the transistors Trz to Tr3, or if a disconnection failure occurs in the circuit, the oscillation operation will stop, and the output No output is generated at terminal C.

Next, Figure i3 shows a specific example of the rectifier circuit RCo,
AC voltage v given from AND operation oscillator OSG o
The circuit has a circuit configuration in which O is rectified and smoothed by diodes D1 and D2 and a capacitor C1, and a rectified output that becomes a counting command signal SO is obtained from an output terminal. This rectifier circuit is
In the event of a disconnection failure, etc., the rectified output will disappear.

In addition, when operating with a negative power supply, it is sufficient to convert the phase to a PNP transistor and an NPN transistor (π) and reverse the direction of the diode.

The explanation will be given by returning to FIG. 1 again. 1 is an example of the configuration of a pulse generator that generates the counting input pulse signal S3. This pulse generator l is constructed so that the pulse width will not be shortened in the event of a failure. If the pulse width is erroneously shortened, the AND operation oscillator O3Cl, which will be described later,
This is because O8C3 becomes unable to respond and there is a possibility that the counting will be erroneously delayed. FIG. 4 shows a specific embodiment of such a pulse generator l, which is an oscillation circuit using a programmable, unijunction, transistor PUT. Rs to R8 are resistors, C2 is a capacitor, and D3 is a diode.

In the pulse oscillator shown in FIG. 4, the counting command signal SO input from the AND operation oscillator 05Go causes
Charges capacitor C2 through diode D3, and C3
・26 programmable unijunction transistors are oscillated with a time constant determined by R6, and a count input pulse signal S3 is outputted through a resistor R8 connected between the gate and cathode. Here, the counting human pulse signal S3
When the period of t is t and n pulses are counted, if the time constant 02.R5 is C2eRs>>nt, the time constant C remains constant even after the counting command signal SO disappears.
2・Terminal voltage remains on capacitor C2 for the time determined by R5, during which time programmable, unijunction,
The transistor Pt1T continues its oscillation operation, and the counting manual pulse signal S3 is obtained.

In order to generate the counter clock signal S3 in synchronization with the disappearance of the counting command signal So, a differential pulse of the 51-contrast command signal SO may be input through the capacitor C4.

This pulse generator of FIG. 4 is a programmable, unijunction, transistor PU
T stops oscillating, and the voltage across the resistor R8, which becomes the counting input pulse signal S3, changes the power supply voltage vb to the resistor R7 and the resistor R8.
It is fixed at the voltage value divided by That is, the pulse width of the counting human pulse signal S3 is not shortened.
Although FIG. 4 shows a circuit configuration in which the terminal voltage of the resistor R8 is used as a pulse output, an amplifier may be provided at a subsequent stage.

OSC1~05Cs are AND operation oscillators, RC1~RC
3 is a rectifier circuit connected to each output of the AND operation oscillators 09Co to O3C3, and these are connected to the AND operation oscillator 05Co already explained in FIGS.
The circuit configuration is similar to that in which no output is generated in the event of a failure.

The AND operation oscillators OSCs, OSC2 and 'l5c
3, each of the input terminals B1. A counting input pulse signal S8 from the pulse generator 1 is inputted in parallel to B2 and B3. Each AND operation oscillator OSC1,
The counting pulse input circuit of OSC2 and OSCs has a configuration in which a capacitor C1l and a diode DI2 are connected in series, and a clamping diode Dll is connected to the connection point between the capacitor CLI and the diode D12. In addition, an AND operation oscillator 0SCQ is connected to the input terminal B1.
The counting command signal SO from the counter is sent to the counter signal S3.
It is designed to be supplied in parallel with. Counting command signal So
may also be supplied to the other input terminals B2 and B3.

Furthermore, AND operation oscillators 0SC1, OSC2 and 03C
s other input end A1. A reset signal S2, which is obtained by differentiating the counting command signal SO from the AND operation oscillator 09Go through a differentiating circuit 2, is manually applied to A2 and A3. The input circuit for the reset signal S2 connects a capacitor C22 and a diode D22 in series, and
A clamping diode D21 is connected to the connection point between the capacitor C22 and the diode D22.

DEll-DEa s is the rectifier circuit RCt~R(s
is a delay circuit connected to each of the. A part of the outputs of these delay circuits DEN t -DEa t are sent to AND operation oscillators O801 to O801 through feedback circuits f1 to f3.
3Ca is fed back to the input terminal A t -A 3 respectively. From the delay time T1 of the delay circuits DEs1 to 0E31, the AND operation oscillator O8Cl to 05CaQ input A1 to
When the pulse width of the reset signal S2 input to A3 is large, each of the AND operation oscillators OSCl to 08C3 performs a self-holding operation. That is, delay circuit DE1t~Ea
t constitutes a self-holding circuit together with AND operation oscillators 0'SC1 to O3Ca and rectifier circuits RCt to RCa.

Even if the present circuits DELL to DEst are not provided, the self-holding operation can be performed if the feedback circuits f1 to f3 are provided, but in this case, the AND operation oscillators O9C1 to OSCa mistakenly perform the self-holding operation due to noise. There is a danger. If there is a delay circuit IIEI 1-DEa 1, it is possible to prevent the self-holding error due to this noise.
These delay circuits DElt-DEs1 are feedback circuits f1-r
It may be provided within the loop of 8.

Ports E12 to DE32 send the output of each self-holding circuit to the next stage's AND operation oscillator 0SC after a certain delay time T2.
2 and OSCa are input terminals B2 and B3 respectively. The delay circuits DE12 to DE32 are connected to the input terminal B2 of the AND operation oscillators O9C2 and 0SC3.
The counting pulse signal S3, which is manually inputted in parallel to each of the oscillators O9C and B3, is provided in order to continue the oscillation operation of the AND operation oscillators O9C2 and O9C3 even if there is a negative input, that is, no voltage. , counting input pulse signal S3
It is configured to have a longer delay time than the pulse width T3 without voltage.

The delay circuits DEr1-DE3t are configured as delay circuits whose delay time T1 is not shortened due to a failure.

Such a delay circuit can be constructed using a four-terminal capacitor. A specific example of this is shown in FIG. 5. In the case of the embodiment shown in FIG. 5, there is no output in either case of disconnection or short circuit, so a failure mode in which the delay time is shortened does not occur.

In the embodiment of FIG. 5, a four-terminal capacitor C5 and a resistor R9
However, instead of resistor R9,
A coil may be used, or a multi-stage configuration may be used depending on the required delay time.

Next, the delay circuits DE12 to DE32 are configured as delay circuits whose delay time T2 is not extended due to failure. Such a delay circuit, for example, as shown in FIG.
This can be realized by a combination of o and a normal capacitor C6.

Next, the operation will be explained with reference to the time chart shown in FIG. First, as shown in Figure 87 (a), when the power is turned on at the time of to, the logic ayI'm oscillates! A high level counting command signal So is output from l09Co and the rectifier circuit RCo connected to its output, and the AND operation oscillator 09C1
is applied to the input end B1 of. At the same time, the counting command signal So is input to the quantity division circuit 2, and a reset signal S2 as a differential output as shown in FIG. 7(b) is generated. This reset signal S2 is generated by AND operation oscillators O9Cs to O3C:
A is input in parallel to each of the input terminals Al-A3, and in the AND operation oscillator 09Ct, the input terminal Bt
The manual logic between the count command signal So inputted to the input signal So and the logical product operation oscillator O9CI starts to oscillate, and a high-level rectification signal is generated in the rectifier circuit PCI.

This rectified output is fed back to the input terminal AI of the AND operation oscillator O3C1 through the delay circuit DELL and the feedback circuit f1, and the AND operation oscillator OSC1 is self-held.

Next, the output of the self-holding circuit by the AND operation oscillator O3Cs causes the next-stage AND operation oscillator 03C2 to start oscillating, and the output causes the AND operation oscillator OSCa to oscillate. In other words, AND operation oscillator 09
Cz-03c3 sequentially starts oscillation operation and is reset. Here, the pulse width T41j of the reset signal S2,
Delay circuit DE of AND operation oscillator oscl~O3C:3
It is assumed that the delay time is longer than the sum of the delay times of t1 to DE31.

The rectified outputs of the rectifier circuits RCt to RC3 are connected to the delay circuit DE1.
1 to DE31, the respective input terminals A1 to A
2, each will be returned. D4 is return, i1 circuit, ~f
This is the diode inserted in 3. Here, delay circuit D
Since the delay time T1 of E1t-DE3t is set to be shorter than the time width T4 of the reset signal S2, a self-holding operation is applied to the AND operation oscillators O3C1 to O3C3.
7(d) to (g) even after the reset signal S2 disappears.
), the oscillation operation continues. Note that when the counting command signal SO becomes high level, a counting input pulse signal S3 as shown in FIG. 7(C) is generated in the pulse generator 1. The input terminal Bl of the oscillator OSCI receives a logic 1 counting command signal S.
o is input, and the AND @ calculation oscillator O9C2,
Since the outputs of the 111-stage self-holding circuit are input to the input terminals B2 and B3 of the OSC3, counting does not proceed.

Next, when the counting command signal So becomes non-voltage at time t1,
A counting command is generated. That is, when the counting command signal So becomes zero voltage, the counting input pulse signal S8 from the pulse oscillator 1 is applied to the input terminal B of the AND operation oscillators 0501 to QSC3.
It will be man-powered by t-B3.

By the first human power of this counting human power pulse signal S2,
The AND operation oscillator O3CI stops oscillating as shown in FIG. 7(d), and the output disappears.

The counting input pulse signal S3 is also input to the AND operation oscillator 05C2 at the same time, but the output of the AND operation oscillator O3Ct is given to the input terminal B2 of the AND operation oscillator 09C2 through the delay circuit DE12. . The delay time T2 of this delay circuit DE12 is set to a time width longer than the pulse width T3 of the 81-some person pulse signal S3. In other words, from 11 o'clock when the output of the AND calculation oscillator 08C1 disappears, for a time T2 longer than the pulse width T3 of the counting human pulse signal S3, the AND oscillator circuit O5C2 inputs the input from the delay circuit [IE12 to the input terminal B2. The oscillation operation is maintained by the signal and one oscillation continues. Moreover, after the delay time T2 has elapsed, the count input pulse signal S3 has returned to the state with voltage.

After the delay time T2 has elapsed, it is held by this 81-man power pulse signal S3.

Next, when the counting human pulse signal S3 of 2 shots 1] is generated at 12 o'clock, the output of the AND calculation oscillator O9C2 is shown in FIG.
It disappears like f).

The above operation is repeated by the number n of stages of the self-holding circuit, and a counter is obtained in which the AND operation oscillator at the final stage counts the first pulse. In this embodiment, the number of stages is 3, so the logical product operation oscillator O9C3 for final termination is constructed as shown in FIG.
), the third counting human pulse signal S3 is counted.

Next, I give it an a+ for fail-safety.

First, the pulse generator l outputs a high level when it fails,
Since the calculation input pulse S3 is not generated and the pulse width is not shortened, this is a direction in which counting advances and is fail-safe. In addition, if the differential capacitor C4 inserted to synchronize with the extinction of the counting command signal SO has an open or short-circuit failure, the synchronizing pulse will not be input manually, or the counting input pulse signal S3 will be grounded, and the counting will start. The human power pulse signal S3 is not generated. When the synchronization pulse is not manually input, there are times when the first note of the il count input pulse S3 appears early, but at this time the counting is on the forward side on the time axis. This shortens the time from when the counting command signal SO is generated to when the AND operation oscillator 0SCz generates an output, and is therefore safe.

In addition, if a circuit failure occurs in the AND operation oscillator OS (: l~O3Ca and the rectifier circuits RC1 and RC3, no output will be generated, and therefore no output will be generated to the next-stage self-holding circuit, so the direction in which the counting advances This is a failsafe.

Next, delay circuit DE11. DE21. If a circuit failure occurs in DE3 t, there will be no output, and DE12,
If DE22 or DE32 fails, it becomes a failure mode in which the delay time is shortened or the output is lost, so it is fail-safe.

Furthermore, the input circuit of each self-holding circuit maintains first-order fail-safety.

(a) When the capacitors C1l and C22 are short-circuited, a clamp voltage cannot be obtained at the input terminals A1-A3 and Bt-B3, so the AND operation oscillators OS01 to OSC3 do not oscillate, and when there is an open-circuit failure, the reset (8 Since the signal S2 and the counting manual pulse signal S3 are not input, the AND operation oscillators 08C1 to 03C3 do not oscillate.

(b) When the diodes D1t and 021 are faulty and short-circuited, the counting manual pulse signal S3 or the reset signal S2 is not input. When the diodes D1t and 021 are open, there is no loop for discharging the accumulated charges in the capacitors C1l and C22, so no pulse can be input.

(c) Self-holding operation is not performed when the diodes D12 and D22 are faulty and short-circuited. For example, the AND operation oscillator O
If the diode D12 of 9C1 is short-circuited, when the input pulse disappears, the diode Dll will be connected to the capacitor CIl.
Since an electric current flows, at this time, the input terminal A1 becomes electric voltage </Vs and stops oscillating, and cannot be self-maintained. Moreover, when it is open, the pulse cannot be generated manually.

(d) Failure of diode D4 If it is opened, it will not be self-holding, and if it is short-circuited, the delay capacitors of the delay circuits DEt~DE3t will be connected in parallel to the inputs of the AND calculation oscillators O201~09II.
The reset signal S2 is not input to :3.

In other words, even in the event of a failure such as disconnection or short circuit in each circuit component constituting the input circuit, the counting continues in the direction of progress, which is fail-safe.

Effects of the Present Invention As described above, the present invention provides a plurality of self-holding circuits so that, on the condition that the output of the self-holding circuit in the previous stage disappears, the counting output voltage of the self-holding circuit in the next stage disappears. Therefore, in a counter that counts input pulse signals, the self-holding circuit consists of an AND operation oscillator that does not generate an output due to a circuit failure, a rectifier circuit that rectifies the output of this AND operation oscillator, and a subsequent stage of this rectifier circuit. and a delay circuit that does not cause a failure on the side where the delay time is shortened, and is configured to be self-maintained by a signal fed back to one of the input terminals of the AND operation oscillator through the delay circuit, The output of each self-holding circuit is input to the next self-holding circuit through a delay circuit that has a delay time longer than the pulse width of the counting input pulse and does not cause a failure on the side where the delay time is extended. Since counting is performed using a counting input pulse signal that is not shortened by a failure, asymmetric error characteristics in the direction in which counting progresses with respect to output voltage and counting time are achieved without the need for a steering circuit or three-value input. It is possible to provide a fail-safe counter that allows you to have .

[Brief Description of the Drawings] Fig. 1 is an electric circuit diagram of a counter according to the present invention, Fig. 2 is an electric circuit diagram of an AND operation oscillator that can be used in the present invention, and Fig. 3 is an electric circuit diagram of a counter according to the present invention.
The figure is an electric circuit diagram of the rectifier circuit, and FIG. 4 is an electric circuit diagram of the pulse generator. FIG. 5 is an electric circuit diagram of the same delay circuit, FIG. 6 is an electric circuit diagram of another delay circuit, and FIG. 7 is a time chart for explaining the operation of the counter according to the present invention. 1--9 Pulse generator O20L~QSCs-Φ/AND operation oscillator RC1-R
C3*/ψ rectifier circuit DEls, DEt 2, DE21. DE22. D
E3 t, DE32...Delay circuit Fig. 2 Δ 4 Fig. 3 Fig. 6

Claims (1)

[Claims] (1) In a counter that has a plurality of self-holding circuits and counts human-powered pulse signals when the counting output voltage of the next-stage self-holding circuit disappears under the condition that the output of the previous-stage self-holding circuit disappears, The self-holding circuit consists of an AND operation oscillator that does not generate an output if one circuit fails, a rectifier circuit that rectifies the output of this AND operation oscillator, and a rectifier circuit that is provided at the subsequent stage of this rectifier circuit to prevent failure of the side that shortens the delay time. The output of each self-holding circuit is configured to be self-maintained by a signal fed back to one of the input terminals of the AND operation oscillator through the delay circuit, and the output of each self-holding circuit is a delay circuit that does not generate a count input pulse. A counting input pulse signal that has a delay time longer than the pulse width and is input to the next stage self-holding circuit through a delay circuit that does not cause a failure on the side where the delay time is extended, and whose pulse width is not shortened by a failure. A counter characterized by counting.