JPH0360327A - Overcurrent limiting circuit for power supply - Google Patents

Abstract

PURPOSE:To logically judge the condition of output and limit current by letting a plurality of stages of a holding means to sequentially hold the condition of an overcurrent detection output, conducting the holding with a short period clock at the first stage and holding the output therefrom at a next stage with a long period clock. CONSTITUTION:When overcurrent flows through a line 21b, a detection signal 'L' is generated from a photocoupler pH2. The condition of the inputted signal 'L' is held in a flip-flop circuit 23 and its output is inputted to an FF circuit 24. When the output from the FF circuit 23 goes to 'L', a photocoupler pH1 becomes conductive whereby a transistor Tr1 is turned off. Since no overcurrent condition is present, a transistor Tr2 is turned on again. Then, the FF circuit 23 holds 'H' and the photocoupler pH1 is turned off to turn the transistor Tr1 on.

Description

[Detailed Description of the Invention] [Summary] Overcurrent detection means connected in series to a line and
An object of the present invention is to provide an overcurrent limiting circuit for a power feeding device that is capable of limiting overcurrent without using software, regarding an overcurrent limiting circuit for a power feeding device such as a terminal that is equipped with a switch means for switching off. and a clock generation means for generating at least two clocks, a short-cycle clock and a long-cycle clock, and a detection signal from an overcurrent detection means, which holds the input signal using the short-cycle clock, and holds the input signal. state holding means for shifting the output to the next stage using the long-cycle clock;
The device is configured to include at least logic means that receives each holding output of the state holding means as an input and generates a control output of the switch means.

[Field of Industrial Application] The present invention relates to an overcurrent limiting circuit for a power supply device to a terminal, etc., which includes overcurrent detection means connected in series to a line and switch means for switching on/off of current.

An example of a device that supplies power to a terminal remote from a central device is a terminal connected to a voice, data, etc. exchange. Conventionally, the power supply device of the exchange for such terminals used program processing to control the current by limiting the current when it detected an overcurrent, but this resulted in inconveniences such as the time it took for the central processing device to process it. There is a need for improvement.

[Conventional technology] Figure 6 shows the constituent countries of the conventional example.

In FIG. 6, a terminal 62 is connected to a power supply device provided in a solid equipment such as an exchange through wires 61a and 61b, and is operated by being supplied with power from a power source 60. The terminal 62 is, for example, a telephone device or a device that handles various data, and has a function of transmitting and receiving signals via a central device.

The wire 61a#l of the power supply device detects the amount of current based on the voltage drop across the resistor R6. Wire 61a between power supply device and terminal 62
, b or when a fault such as a short circuit occurs on the terminal side,
When an overcurrent flows and the voltage of the resistor R6 becomes larger than the normal value, the overcurrent detection transistor Tr2 is turned on, and its collector current is transferred to the power supply 60. It flows through line 61a.

Then, the light emitting diode of the photocoupler PH2 consisting of a light emitting diode and a light receiving transistor is driven, and a detection signal "1" is generated from the collector of the light receiving transistor and is supplied to the scanning input (indicated by SCN) of the signal circuit 63. . This signal is periodically scanned by a control circuit (indicated by CTL) 64, and if "1" is generated, the control circuit 64
Through program processing, a current limit control signal is supplied to the control output (indicated by SD) corresponding to the power supply device.

In response, the photocoupler PH1 of the power supply device is driven and its light-receiving transistor is turned on, and the base and terminal of the power supply control transistor Tri inserted in series with the line 61b are short-circuited, and the transistor Tri is turned on. By turning it off, the power supply current stops.

[Problems to be Solved by the Invention] In the configuration of the conventional example described above, the control circuit 64 periodically reads the scanning input SCN and processes it by a program to control the control output SD. When the control circuit 64 performs processing for the power supply devices, the software load increases as the number of devices increases, which poses a problem for the control circuit 64 to perform processes other than power supply control.

An object of the present invention is to provide an overcurrent limiting circuit in a power supply device that can implement overcurrent limiting without using software.

[Means to solve the problem] FIG. 1 is a diagram showing the principle configuration of the present invention.

In Figure 1, lo is the line connecting the power supply device and the terminal,
11 is a terminal, 12 is a switch means, 13 is an overcurrent detection means, 14 is a logic means, 15 is a state holding means, 16 is a clock generation means, and 17 is a power supply.

The present invention uses hardware to implement current limiting processing in the event of overcurrent, which was conventionally done using software. Holding is performed using a clock with a long period, and when the output is held in the next stage, a clock with a long period is used, and the current is limited by logically determining the state of these outputs.

[Effect] Terminal 11 is supplied with power from power source 17 via line 10 .

When an overcurrent flows through the line IO, it is detected by the overcurrent detection means 13 and the detection output is inputted to the state holding means 15. The state holding means 15 consists of at least two stages of holding means, and the first stage holding means 151 receives a short-cycle clock generated from the clock generation means 16 and controls the overcurrent detection means 1.
Hold the output of 3.

The next-stage holding means 152 receives the output of the first-stage holding means 151 and performs a holding operation using a long-cycle clock from the clock generation means 16. The state holding means 15 inputs the outputs of a plurality of holding means, performs a logical judgment, and outputs a control signal for current limitation to the switch means 12.

The reason why the state holding means 15 includes a plurality of stages of holding means, performs the holding operation using a plurality of clocks from the clock generation means 16, and determines the output of the state holding means by the logic means 14 is as follows. That is, when the switch means 12 turns off the switch in response to the control signal from the logic means 14 and stops the current, the overcurrent detection means 13 stops the current, so the overcurrent detection output stops, and the state holding means 15 Detection output disappears. If the state holding means immediately turns on the switch based on the detection output of the overcurrent detection means 13, the current limiting time will only be short. According to the present invention, it is possible to guarantee the current limit time for a predetermined period of time.

[Example] Figure 2 shows the constituent countries of Example 1 of the present invention, Figure 3 (a) shows the normal status chart of Example 1, and Figure 3 (b)
4 is a timing chart diagram of the abnormal state in the first embodiment, FIG. 4 is a timing chart diagram of the constituent countries of the second embodiment, and FIG. 5 is a timing chart diagram of the second embodiment.

In Fig. 2, 20 is a power supply, 21a and 21b are lines connecting to terminals, 22 is an AND circuit, 23 is flip-flop circuit 1 (represented by FFI), 24 is flip-flop circuit 2 (represented by FF2), and 25 is a clock. It represents a generation circuit, and the other parts represent the same components or circuits as in the conventional example, R1-R6 are resistors, Dl is a Zener diode,
Tri is a transistor for power supply control, Tr2 is a transistor that is turned on when overcurrent is detected, and PHI and PH2 are photocouplers. Note that the overcurrent detection means 13 in FIG. 1 includes a resistor R6, a transistor Tr2 . The switch means 12 in FIG. 1 corresponds to a circuit composed of a photocoupler PH2, etc., and the switch means 12 in FIG. 1 corresponds to a circuit composed of a photocoupler PH1, a transistor Tri, etc.

The operation of the embodiment will be explained using the timing charts of FIGS. 3(a) and 3(b). In both figures, i from the top
is the current flowing through the wire 21, and the detection signal is the photocoupler PH2
CKI is a short-frequency 31JI <for example, several milliseconds> clock signal generated from the clock generation circuit 25, FFI is the output of the flip-flop circuit 23,
CK2 is a clock signal generated from the clock generation circuit 25 with a long cycle (for example, several hundred milliseconds) and generated twice at a time, FF2 is the output of the flip-flop circuit 24, and AN
D represents the output of the AND circuit 22.

In FIG. 2, when an overcurrent flows through the line 21b, the transistor Tr2 is turned on as in the conventional case, and a detection signal u L n (low level) is generated from the photocoupler PH2.

In response to this detection signal, as shown in FIG. 3(a), the clock CK is
When I appears, the state of the input signal (“L”) is held in the flip-flop circuit 23, and its output (FIG. 3(a)
) is input to the flip-flop circuit 24.

At this time, the output of the flip-flop circuit 24 is in the "H" (high level) state until the clock CK2 shown in FIG.
) appears. That is, when the output of the flip-flop circuit 23 becomes "L", the output of the AND circuit 22 becomes "L", and the output of the photocoupler P
H1 becomes conductive.

This switches transistor Tri off,
Current i stops. Then, since the overcurrent condition disappears, the transistor Tr2 that detects the overcurrent shown in FIG. 2 starts operating again, and the output of the photocoupler PH2 becomes 11°'.
Therefore, "H" is supplied to the flip-flop circuit 23.

Then, the flip-flop circuit 23 holds "H" at the timing of the clock CKI, and the output of the 14p is supplied to the AND circuit 22, so the output of the AND circuit 22 becomes "H". Then, the photocoupler P111 is turned off and the transistor Trl is turned on. This causes the current to stop flowing again, and if the overcurrent condition continues, the sequential operations described above are performed.

If the output of the flip-flop circuit 23 is "H" when the second pulse of the two pulses of the long-period clock CK2 in FIG. 3(a) is generated, the flip-flop circuit 24 state Lq (as mentioned above, first 11
However, if the output of the flip-flop circuit 23 is "L" when the second pulse is generated, the output of the flip-flop circuit 23 is "L".
4 is held at "L", its output becomes "L", and "L" is output from the AND circuit 22. As a result, the transistor Trl is driven off. In this state, the next clock CK2 appears. The current continues until the line 21
a, it does not flow to 21b.

After this, when clock CK2 occurs after the next cycle,
As shown in FIG. 3(a), the flip-flop circuit 23
In response to the output "H" of C, it becomes I(" for a short time, the output of the AND circuit 22 becomes "H" and current flows, but C
CK1 generated after K2 causes the flip-flop circuit 23 to become "L", and the output of the AND circuit 22 immediately becomes "L", stopping the current flow.

In this way, when an overcurrent occurs, the power supply current can be stopped by the hardware circuit. By limiting the current in this way, the overcurrent to the terminal can be suppressed to a certain level or less on average, and the influence on the equipment can be reduced.

Next, in the operation of the first embodiment shown in FIG. 2, a timing chart when current limitation is not sufficiently performed is shown in FIG. 3(b).

The names of the respective waveforms shown in FIG. 3(b) are the same as those described for FIG. 3(a).

In the case of FIG. 3(b), the waveform of each part when an overcurrent first occurs is the same as that of FIG. 3(a), and the current l turns on and off in a rectangular waveform. And 2 of clock CK2
If the output of the flip-flop circuit 23 is "L" when the first pulse of the two pulses is generated (this is different from FIG. 3(a) above), the flip-flop circuit 24 holds "Shi". Ru.

However, when the second pulse of the clock CK2 occurs, if the output of the flip-flop circuit 23 changes to °゛H, the flip-flop circuit 24 holds "'H" and the output from the AND circuit 22 changes. supply As a result, the AND circuit 22 alternately outputs "H" and "L" depending on the output of the flip-flop circuit 23 (therefore, it changes with the cycle of the clock CKI) until the next pulse of the clock CK2 appears.

In the case of Fig. 3(b), the current is limited, but it cannot be said to be sufficient.In this way, in the configuration of Embodiment 1 shown in Fig. FIG. 4 shows a configuration of a second embodiment in which current limitation is not performed and this is improved.

In FIG. 4, 40 is a power supply, 41a and 41b are lines,
42 is an AND circuit, 43 to 45 are flip-flop circuits (represented as FF2, FFI, and FF3, respectively), and 46 is a clock generation circuit that generates three clocks CKI, CK2, and CK3, and is used for other overcurrent detection. , resistor R6° transistor Tr2. Photocoupler PH
transistor Tri for configuration and current control,
The configuration of the photocoupler PH1 and the like is the same as in the first embodiment.

FIG. 5 is a timing chart diagram of the second embodiment of FIG. 4, and 1. Detection signals, CKI, FFl, CK2.
FF2 represents the same signal as in Figure 3(a) and in Figure 3),
CK3 and FF3 represent the output of clock CK3 generated from clock generation circuit 46 and the output of flip-flop circuit 45 in FIG. As shown in FIG. 5, clock CK3 has the same period as clock CK2 and also
It generates several pulses, but they have a phase difference.

The operation of the second embodiment will be explained with reference to FIG.

When an overcurrent occurs, the transistor Tri and the photocoupler PH2 are turned on, and the detection signal "L" is input to the flip-flop circuit 44 and held at the timing of the clock CKI. The operation is the same as in the first embodiment. Yes. At this time, if the flip-flop circuits 43 and 45 are in the H" state (when clocks CK2 and CK3 are not generated)
, the output of the AND circuit 42 is intermittent by the output of the flip-flop circuit 44, and the current i flows intermittently in the same manner as described in the first embodiment.

Thereafter, the first pulse of clock CK3 is generated prior to clock CK2 as shown in the figure. At this time, if the output of the flip-flop circuit 44 is "L", that state is held in the flip-flop circuit 45. This "L" output is input to the AND circuit 42.

After that, when the second pulse of the clock CK3 is input, the output of the flip-flop circuit 44 is "H", so the output of the flip-flop circuit 45 also becomes "H".

At the timing of the second pulse generation of the clock CK3, the first pulse of the clock CK2 is generated, and the state of the flip-flop circuit 44 at this time (“H” at this time)
is held, but when the second pulse of the clock CK2 is generated thereafter, the output of the flip-flop circuit 44 becomes "L", so the flip-flop 43 generates an "L" output. As a result, the AND circuit 42 receives the next clock CK3. Since the output of "L+1" continues to be generated until CK2 is generated, the long-period current is stopped.In this way, two clocks CK2 and CK3 and the corresponding flip-flop circuits 43 and 45 are provided. This makes it possible to reliably limit the current.

[Effects of the Invention] According to the present invention, the overcurrent limiting operation that was previously achieved by software is realized by hardware, so that the burden on the control device that performs various processes can be reduced. Furthermore, when the line short-circuit condition is restored, normal power supply can be autonomously restored.

[Brief explanation of drawings]

FIG. 1 is a diagram of the principle of the present invention, FIG. 2 is a diagram of the configuration of the first embodiment, FIG. 3(a) is a timing chart of the first embodiment in normal operation, and FIG. 3(b) is a diagram of the first embodiment. FIG. 4 is a configuration diagram of the second embodiment, FIG. 5 is a timing chart diagram of the second embodiment, and FIG. 6 is a configuration diagram of a conventional example. In FIG. 1, 1 (1:1i path 11: terminal 12: switch means 13: overcurrent detection means 14: logic means 15: state holding means 16: clock generation means 17: power source actual method 112) Figure 4

Claims (1)

[Claims] Overcurrent detection means (13) connected in series to the line (10).
) and switch means (12) for switching on/off of the current.
In an overcurrent limiting circuit of a power supply device for a terminal etc., comprising: a clock generation means (16) for generating at least two clocks, a short-cycle clock and a long-cycle clock; and the overcurrent detection means (13). With the detection signal of
a state holding means (15) that holds the input signal using the short period clock and holds the held output in the next stage using the long period clock; and at least each holding output of the state holding means (15) is inputted. The switch means (
12) A logic means (14) for generating the control output of FIG. 12).