GB2325527A

GB2325527A - Detecting the state of an electrical conductor

Info

Publication number: GB2325527A
Application number: GB9710670A
Authority: GB
Inventors: Richard David Simpson
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 1997-05-23
Filing date: 1997-05-23
Publication date: 1998-11-25
Anticipated expiration: 2017-05-23
Also published as: GB2325527B; GB9710670D0

Abstract

An array of electrical conductors (112) is typically associated with a redundant 64-bit register of a semiconductor memory device, which stores a unique serial number for the device in the form of a binary numeric code. This binary numeric code is programmed into the register during fabrication and comprises a sequence of binary digits, the serial number being determined by the combination of the states of the array of electrical conductors (112). The invention is used to detect the state of each of these electrical conductors (i.e. high or low impedance), and is arranged so that no continuous DC current path exists. When "intact" the electrical conductor (112) forms part of an electrical circuit which acts as an inverter, the output of which corresponds to an anti-phase image of the clocking waveform (CLK1) at its input. When the electrical conductor is "blown", the electrical circuit is effectively open-circuit and consequently there is no potential to pull the output potential to a level corresponding to a logic high level.

Description

IMPROVEMENTS IN OR RELATING TO SEMICONDUCTOR DEVICES FIELD OF THE INVENTION The present invention relates to electrical conductors, and more particularly to electrical conductors used in the programming of a semiconductor device.

BACKGROUND OF THE INVENTION A problem commonly encountered by semiconductor device manufacturers is that increased miniaturisation has resulted in the surfaces of electronic sub-module packages having insufficient surface area to apply a serial number. The application of serial numbers to devices is desirable, as it allows the manufacturer to determine the manufacturing characteristics of the batch from which it came.

The application of serial numbers to products has become increasingly significant as it generates traceability of each component. Consequently, a detailed history of the manufacturing process may be obtained. This is particularly important where faults occur in devices, as it enables manufacturers to locate a particular stage during manufacture where the fault was introduced, and consequently limits the time necessary to locate likely sources of the fault.

Conversely, traceability allows manufacturers to characterise the desirable integers during the fabrication of a manufacturing batch. Therefore, following electrical characterisation of a device from a manufacturing batch, it may be possible to determine the integers which produce desirable characteristics. One example, may be a device which performs particularly well at high frequencies.

Manufacturers have looked to methods which do not require a serial number to be physically placed onto a device or sub module package. Typically, these methods have required additional logic circuitry, and have resulted in delayed access times.

A further solution to this problem has been the implementation of software techniques in which a serial number is stored in a redundant register on the device. An additional advantage of using software techniques is that it is typically unnecessary to dismantle an electronic product in order to ascertain the device serial number, this being achievable by interrogating the device remotely.

It has been proposed that semiconductor devices which comprise a redundant register can be programmed with a serial number in the form of a binary numeric code during fabrication.

The code is unique to each individual device and comprises a sequence of binary digits. The serial number is determined by the combination of the states of an array of fusible electrical conductors, the state of each conductor corresponding to either a binary digit "0" or to a binary digit " 1 Il.

These fusible electrical conductors are well. known in the semiconductor industry, but have typically been used to effect the replacement of redundant memory elements in memory devices.

For convenience an electrical conductor having a high electrical impedance will hereinafter be referred to as a conductor which is " ""blown", , and an electrical conductor having a low electrical impedance will hereinafter be referred to as a conductor which is ""intact"".

To determine the serial number of an individual device, it is necessary to identify the state of each electrical conductor in an array (i.e. whether the conductor is "blown" or "intact") . Conventionally, this has been achieved using a static method in which a DC current is passed through the electrical conductor.

It has been found that this method causes problems during the validation of semiconductor devices following manufacture, as some tests require that no DC path to ground is present. An additional problem exists with applications where power consumption is critical, such as portable cell power supplies.

SUMMARY OF THE INVENTION The present invention provides a method and apparatus for detecting the state of an electrical conductor without the requirement for a DC current path. An advantage of the present invention is that manufacturing tests may be performed on semiconductor devices which have not generally been possible with methods and apparatus according to the prior art. In particular it is possible to ensure that no DC current flows through the device when the device clocks are stopped (Iddq test), a defect being detected as a leakage between nodes (typically 20-30 micro-amps).

According to the present invention there is provided a method of detecting the state of an electrical conductor, which method comprising engaging said electrical conductor in circuitry responsive to a clocking waveform such that no continuous DC current path exists and applying a clocking waveform to said circuitry to produce an output signal indicative of the state of the electrical conductor.

In the preferred embodiment of the present invention the electrical conductor is located between two MIS transistors and together with the transistors forms an inverter. When the electrical conductor is "intact", and has a low impedance, the output signal will comprise an inverse image of the clocking waveform. Conversely, when the electrical conductor is "blown", and has a high impedance, an effective open-circuit condition will exist and the output will be held at a low level.

Further circuitry is provided to determine whether the output signal is consistently low, or the signal is switching in anti-phase with the clocking waveform.

According to a second aspect of the present invention there is provided an apparatus for detecting the state of an electrical conductor, which apparatus comprising circuitry responsive to a clocking waveform, and engagement means for engaging said electrical conductor such that no continuous electrical current path exists, wherein the application of the clocking waveform to said circuitry produces an output signal indicative of the state of the electrical conductor.

The circuitry produces an output signal corresponding to a binary logic voltage level in response to a clocking waveform.

In the particularly preferred embodiment of the second aspect of this invention a binary logic " 1 " corresponds to an electrical conductor having a low impedance, and a binary logic 'O" corresponds to an electrical conductor having a high impedance.

The circuitry also comprises means for determining whether the output signal is an anti-phase image of the clocking waveform.

This circuitry ensures that the output signal has not remained low following a positive cycle of the clocking waveform.

A feedback circuit is also provided which maintains the low level of the output signal during the negative cycle of the clocking waveform when the conductor is "blown", to ensure that the output signal is never floating. This circuit can be over-ridden by the main circuitry, which ensures that a false signal is not seen at the output.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be further described, by way of example, with reference to the accompanying drawings, in which; Figure 1 is a diagram of a circuit used for determining the state of an electrical conductor in accordance with the prior art; Figure 2 is a diagram of a preferred circuit for detecting the state of an electrical conductor in accordance with the present invention; Figure 3 is a detailed diagram of a feedback circuit of Figure 2; and Figure 4 is a detailed diagram of latching circuitry of Figure 2.

DETAILED DESCRIPTION OF THE DRAWINGS The electrical circuit (10) illustrated in Figure 1 is an example of a typical prior art apparatus which is used to determine the state of each electrical fuse (12) in an array.

The circuit (10) comprises an electrical fuse (12) located between a supply rail (14) and the source electrode (18) of a transistor (16). The supply rail (14) is also connected to the gate electrode (20) of transistor (16), and the drain electrode (22) of transistor (16) is connected to a ground rail (24). An output node (A) is located between the source electrode (18) and the fuse (12) is connected to an -inverter (26).

The operation of the electrical circuit (10) will now be explained with reference to a conducting fuse (12). A conducting fuse (12) will have a relatively low electrical impedance (typically less than 1 ohm), while the transistor (16) will have a higher effective impedance (typically several thousand ohms). Therefore, the voltage at the node (A) will approach that of the supply rail (14) and a DC current path will exist through the fuse (12) and the transistor (16)to the ground rail (24).

The level of the current will be determined by the electrical impedance of the transistor (16) and may be as low as a few micro-amps. However, the current will continually flow through the conducting fuse (12).

When a fuse (12) is "blown0, the node (A) will be held at the level of the ground rail (24) by the transistor (16) and the DC current path is removed. The inverter (26) acts as a buffer, and thereby produces an impedance match of this circuit (10) to the next stage of the electrical circuitry.

Referring now to Figure 2, which shows the circuit (110) of the invention according to the preferred embodiment, a fusible electrical conductor (112) is shown located between the drain electrode (122) of an P-channel MIS transistor (116) and the source electrode (128) of an N-channel MIS transistor (126).

The source electrode (118) of transistor (116) and the drain electrode (132) of the transistor (126) are connected to the supply rail (114) and the ground rail (124) respectively. A clock generator (not shown) is connected to the gate electrodes (120 & 130) of both transistors (116 and 126), and output node (B) is connected between the electrical conductor (112) and the source electrode (128) of transistor (126).

In operation the circuit (110) relies on a transient current flowing through the circuit (110), as no continuous DC current path exists between the supply rail (114) and the ground rail (124).

When the electrical conductor (112) is "intact" (i.e. has a low effective electrical impedance), and a clocking waveform (CLK1) is applied to the gate electrodes (120 & 130) of transistors (116 and 126), the positive cycle of the clocking waveform (CLKl) will result in transistor (116) being isolated. However, the positive cycle of the clocking waveform (CLKl) causes transistor (126) to conduct, pulling the potential at the output node (B) to that of the ground rail (124).

The negative cycle of the clocking waveform (CLKl) will result in transistor (116) conducting, and transferring a current from the supply rail (114) through the source and drain electrodes (118 & 122) of transistor (116), pulling the potential of the output node (B) to that of the supply rail (114). Conversely, the negative cycle of the clocking waveform (CLKl) causes transistor (126) to be isolated.

Consequently, an anti-phase image of the clocking waveform (CLKl) will be created.

When the electrical conductor (112) is "blown" (i.e. has a high effective impedance), no current path will exist between the supply rail (114) and the ground rail (124). Effectively, the transistor (116) and the output node (B) will be isolated, the output node (B) remaining permanently low as there is no potential to pull it high.

However, transistor (126) will continue to switch in sequence with the clocking waveform (CLKl) applied to the gate (130).

Therefore, it is necessary to provide further circuitry which maintains the potential at the output node (B) at a low level for an electrical conductor (112) which is "blown" during a negative half-cycle of the clocking waveform (CLK1).

The feedback circuit (140) shown in Figure 3 maintains output node (B) at a low potential when the electrical conductor (112) is "blown" and a negative cycle of the clocking waveform (CLKl) is applied to the gate (130) of transistor (126). The feedback circuit (140) comprises an N-channel MIS transistor (146) and an inverter (142).

The source electrode (148) of transistor (146) is connected to the output electrode (B), and the drain electrode (152) is connected to the ground rail (124). The inverter (142) is connected between the source electrode (148) and the gate electrode (150) of the transistor (146). Consequently, when the potential at the output node (B) is high, the potential at the gate electrode (150) of transistor (146) will be low.

However, when the potential of the output node (B) is low, the potential at the gate electrode (150) will be high and the transistor (146) will conduct pulling the potential of the output node (B) to that of the ground rail (124).

However, it is necessary to determine whether the output node (B) is permanently low potential, or whether the potential at output node (B) is an anti-phase image of the clocking waveform (CLKl). Figure 4 shows a two-stage latch circuit (160) comprising first latch circuit (200) and second latch circuit (300). Each circuit (200,300) comprises a N-channel MIS transistor (216,316) which receive non-overlapping clocking waveforms (CLK2 and CLK1 respectively).

The first latch circuit (200) further comprises an inverter (210), the output of which is connected to the input by a feedback inverter (212). The source electrode (218) of transistor (216) is connected to the output of the feedback circuit (C), so that a positive cycle of the clocking waveform (CLK2) will cause the potential at the output of the feedback circuit (C) to be transferred to the drain electrode (222), and hence also to the input (C) of the first latch circuit (200). An inverse of the potential at the drain electrode (222) will consequently appear at the output of the first latch circuit (D), which will be inverted by the feedback inverter (212) and fed-back to the input of first latch circuit (D).

The second latch circuit (300) also comprises an inverter (310), the output (E) of which is connected to the input (D) by a feedback inverter (312). The source electrode (318) of transistor (316) is connected to the output (D) of the first latch circuit (200), so that a positive cycle of the clocking waveform (CLKl) will cause the potential at the output of the first latch circuit (200) to be transferred to the drain electrode (322), and hence also to the input (D) of the second latch circuit (300). An inverse of the potential at the drain electrode (322) will consequently appear at the output (E) of the second latch circuit (300), which will be inverted by the feedback inverter (312) and fed-back to the input of second latch circuit (300).

Therefore, in operation when the electrical conductor (112) is "blown", the potential at the output node (B) will be low.

Consequently the output of the feedback circuit (140) will have a high potential, the output of the first latching circuit (200) will have a low potential, and the output of the second latching circuit (300) will be high.

For a condition where the electrical conductor (1 12) is "intact", the potential at the output node (B) will be an anti-phase image of the clocking waveform (CLK1), Consequently the output of the feedback circuit (140) will be in-phase with the clocking waveform (CLK1). The potential at the output of the feedback circuit (140) will be latched into the first latching circuit (200) on the falling edge of the second clocking waveform (CLK2). Since the first and second clocking waveforms (CLK1, CLK2) are non-overlapping this will occur when the potential at the output of the feedback circuit (140) is low. Thus, for a positive cycle of the first clocking waveform (CLKl) applied to the second latching circuit (300), the potential at the output of the first latching circuit (200) will be high, and consequently the potential at the output of the second latching circuit (300) will be low.

In an alternative embodiment of the present invention, the fuse (112) may be moved to the supply potential side of the Pchannel MIS transistor (116). This is advantageous where there is a concern that ESD events may cause damage or distrub the gates of the device.

Although the present invention has been described with reference to certain illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description.

Claims

1. A method of detecting the state of an electrical conductor (112), which method comprising; arranging said electrical conductor (112) in circuitry responsive to a clocking waveform (CLK1) such that no continuous DC current path exists; and applying a clocking waveform (CLK1) to said circuitry to produce an output signal indicative of the state of the electrical conductor (112).

2. The method as claimed in Claim 1 further comprising; producing an output signal which is an anti-phase image of the clocking waveform (CLKl) to indicate an electrical conductor (1 12) having a low impedance.

3. The method as claimed in Claim 1 or Claim 2 further comprising; producing an open-circuit to indicate an electrical conductor (1 12) having a high impedance.

4. The method as claimed in any preceding claim further comprising; determining whether the output signal is switching in anti-phase with the clocking waveform (CLKl).

5. A method of detecting the state of an electrical conductor (112) substantially as herein described with reference to any of the accompanying drawings.

6. Apparatus for detecting the state of an electrical conductor (112), which apparatus comprising; circuitry (11) responsive to a clocking waveform (CLK1) and comprising said electrical conductor arranged such that no continuous electrical current path exists; wherein the application of the clocking waveform (CLKl) to said circuitry (11) produces an output signal indicative of the state of the electrical conductor (112).

7. The apparatus as claimed in Claim 6, wherein said output signal comprises a binary logic level, said binary logic level being "1" in respect of an electrical conductor (112) having a low electrical impedance, and said logic level being "O" in respect of an electrical conductor (112) having a high electrical impedance.

8. The apparatus as claimed in Claim 6 or Claim 7, wherein said circuitry further comprises; monitor means (140,200,300) for monitoring the output signs such that the output signal is an anti-phase image of the clocking waveform (CLKl).

9. The apparatus as claimed in Claim 8, wherein said circuitry further comprises; feedback (140) means arranged to maintain the output signal at a substantially constant level.

10. The apparatus as claimed in Claim 9, wherein the circuitry further comprises; first latching means (200) responsive to a second clocking waveform (CLK2) and arranged to produce an inverse of a signal from said feedback means (140).

11. The apparatus as claimed in Claim 10, wherein the circuitry further comprises; second latching means (300) responsive to the first clocking waveform (CLK1) and arranged to produce an inverse of a signal from said first latching means(200).

12. The apparatus as claimed in any of Claims 6 to 11, further comprising: engagement means for engaging at least one electrical conductor (112) is said circuitry.

13. The apparatus as claimed in any of Claims 6 to 12, wherein said apparatus is adapted to detect the state of a plurality of electrical conductors (112).

14. The apparatus as claimed in any of Claims 6 to 13 substantially as herein described with reference to any of the accompanying drawings.