JP3170583B2 - Semiconductor integrated circuit testing method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method and an apparatus for testing a semiconductor integrated circuit.

[0002]

[Prior art]

With the increase in the degree of integration of semiconductor integrated circuits, the test time has increased, and the test cost has increased. Testing of semiconductor integrated circuits is roughly classified into an AC test for checking access time and the like and a DC test for checking power supply current and the like.

In the AC test, a probe is brought into contact with all the leads at the same time for a plurality of semiconductor integrated circuits of the same type, and a test signal is supplied to each semiconductor integrated circuit at the same time and in parallel to perform test processing in parallel. Is being shortened.

However, in the DC test for checking the current flowing to the external power supply terminal of each semiconductor integrated circuit, in order to detect the current flowing to each external power supply terminal at the same time, the DC power supply for the number of semiconductor integrated circuits to be tested at the same time is required. A unit and a current detection circuit are required, and the test equipment becomes expensive.

Therefore, as shown in FIG. 4, in the conventional DC test apparatus 20, one terminal of each of the relay contacts 21 to 26 is connected to an external power supply terminal TC of each of the semiconductor integrated circuits 10 to 15 via a probe. The other terminals of the relay contacts 21 to 26 are made common and connected to a voltage output terminal of a DC power supply 28 via a current detection circuit 27. Then, the relay contact switching circuit 29
Turn on any one of 21 to 26, turn off all others, switch on the relay contact 21 that is turned on at regular intervals, and detect the current flowing through each semiconductor integrated circuit 10 to 15 with the current detection circuit 27. However, it was checked by a circuit (not shown) whether this was within a specified range.

[0006]

[Problems to be solved by the invention]

However, since the operation time of the relay is several tens of ms, if the test is repeated many times, the test time becomes longer as a whole, which causes an increase in test cost.

An object of the present invention is to provide a method and an apparatus for testing a semiconductor integrated circuit having a configuration capable of reducing a test time in view of such a problem.

[0008]

[Means for Solving the Problems]

In the present invention, the external power supply terminal (TC) and the internal circuit (3
0) and a power switch control circuit (32) for turning on / off the power switch according to the voltage applied to the external terminal (T1). A semiconductor integrated circuit test apparatus for an integrated circuit (10A to 15A), wherein a voltage supplied to the external terminal is sequentially switched to turn on only one of a plurality of the power switches and to turn on the power switch. A switching control circuit (41 to
43), a DC voltage is selectively applied to the semiconductor integrated circuit having the power switch that is connected to the external power supply terminals of the plurality of semiconductor integrated circuits and turned on among the plurality of semiconductor integrated circuits. A DC test circuit (27, 28A) for checking a current supplied and flowing to an external power supply terminal of the semiconductor integrated circuit.

In the method of the present invention, the external power supply terminal (TC) and the internal circuit (3
0) and a power switch control circuit (32) for turning on / off the power switch according to the voltage applied to the external terminal (T1). A method for testing a semiconductor integrated circuit for an integrated circuit (10A to 15A), wherein a voltage supplied to the external terminal is sequentially switched so that only one of the plurality of power switches is turned on and the power switch is turned on. Switching in order, a DC test circuit commonly connected to the external power supply terminals of the plurality of semiconductor integrated circuits selects the semiconductor integrated circuit having the power switch turned on among the plurality of semiconductor integrated circuits. A DC voltage is supplied to check the current flowing to the external power supply terminal of the semiconductor integrated circuit.

[0010]

【Example】

Hereinafter, embodiments of a method and an apparatus for testing a semiconductor integrated circuit according to the present invention will be described with reference to the drawings.

FIG. 1 shows a main configuration of the semiconductor integrated circuit 10.

The semiconductor integrated circuit 10 is, for example, a semiconductor memory. The internal circuit 30 is connected to external input terminals T1 to Tm, external output terminals Tm + 1 to Tn, and a ground terminal TS. It is connected via a PMOS transistor 31 as a switch. The gate of the PMOS transistor 31 is controlled by a power switch control circuit 32, and the power switch control circuit 32 operates according to the voltage applied to the external input terminal T1.

That is, the power switch control circuit 32 includes a PMOS transistor 33 as a load element and CMOS inverters 34, 35 and 36 connected in series. This PMOS transistor 33
Has its source connected to the external input terminal T1, and its drain connected to its gate and the source of the PMOS transistor of the CMOS inverter. The input terminal of the CMOS inverter 34 is commonly connected to the sources of the PMOS transistors of the CMOS inverters 35 and 36, and is also connected to the external power supply terminal TC. The sources of the NMOS transistors of the CMOS inverters 34 to 36 are commonly connected to the ground terminal TS,
The output terminal of the OS inverter 36 is connected to the gate of the PMOS transistor 31.

Next, the operation of the semiconductor integrated circuit 10 configured as described above will be described.

A power supply voltage V _CC (for example, 5.0 V) is applied to the external power supply terminal TC, the ground terminal TS is grounded, and a normal operating voltage, for example, a voltage in the range of −0.6 to 7.3 V is applied to the external input terminal T 1. In addition, since the input level of the CMOS inverter 34 is at a high level and its NMOS transistor is on,
The output of the OS inverter 34 is at a low level, the output of the CMOS inverter 35 is at a high level, the output of the CMOS inverter 36 is at a low level, and the PMOS transistor 31 is on. Therefore, when data at the external input terminals T1 to Tm is input, corresponding data is output from the external output terminals Tm + 1 to Tn.

The external input terminal T1 is connected to a high voltage V higher than a normal operation voltage.
_{When HH is set to} , for example, 8 V, the PMOS transistor 33 of the CMOS inverter 34 is turned on, and the output of the CMOS inverter 34 becomes high. Therefore, the output of the CMOS inverter 35 goes low, the output of the CMOS inverter 36 goes high, and the PMOS transistor 31 is turned off.

Next, a test for a semiconductor integrated circuit having such a configuration will be described with reference to FIG.

In a test of a semiconductor integrated circuit, an AC test and a DC test are performed on a plurality of, for example, six, semiconductor integrated circuits 10A to 15A by simultaneously bringing probes into contact with all leads. In the AC test, the test signal is applied to each semiconductor integrated circuit
~ 15A common and simultaneous supply and parallel processing. Second
The figure shows a main configuration of a DC test apparatus 40 for checking a current flowing to an external power supply terminal TC of each of the semiconductor integrated circuits 10A to 15A.

The external power supply terminals TC of the semiconductor integrated circuits 10 A to 15 A are commonly connected, and are connected to the V _CC output terminal of the DC power supply 28 A via the current detection circuit 27 of the DC test device 40. Each external input terminal T1 of the semiconductor integrated circuits 10A to 15A is connected to each output terminal of the demultiplexer 41 via a probe (not shown). The input terminal of the demultiplexer 41 is connected to the V
Connected to _HH output terminal. Also, the clock generator 42
Are counted by the hexadecimal counter 43, and the counted value is supplied to the selection control terminal of the demultiplexer 41. When the clock generator 42 is activated, one of the outputs of the demultiplexer 41 becomes 0 V, and the other becomes a high voltage.
V _HH . The output that becomes 0 V is output from the clock generator 42.
Are sequentially switched at the cycle of the clock from Therefore, the current flowing through each of the external power supply terminals TC of the semiconductor integrated circuits 10A to 15A can be detected by the current detection circuit 27.

Since the response speed of the power switch control circuit 32 is usually several ns, the DC test can be performed at a higher speed than in the related art.

FIG. 3 shows a configuration for reducing power consumption when the semiconductor integrated circuit having the above configuration is a ROM.

Here, when a plurality of ROMs are used, usually, an address input terminal and a data output terminal are commonly connected to each ROM, and only one semiconductor integrated circuit is selected by a chip select signal. It is common. In this case, except for one ROM selected by the chip select signal is in a non-operation state, but since the power supply is not cut off,
Standby power is consumed even in a non-operation state. However, in the case where the present invention is used, the conventional configuration in which only one ROM is selected by the chip select terminal is replaced by a high voltage V to the external input terminal instead of the chip select terminal.
_{If HH} is applied, the power is shut off. As a result, standby power is no longer consumed and the operating ROM
Only power will be consumed. Such a use method is particularly effective when power must be supplied from a battery or the like.

In FIG. 3, address lines A _{0 to} A ₃ are connected to input terminals of the decoder 50 and address terminals (not shown) of the semiconductor integrated circuits 10A to 1nA, and output terminals of the decoder 50 are connected to the semiconductor integrated circuits 10A to 10A. It is connected to each 1nA external input terminal T1. The decoder 50 has one output terminal corresponding to the input address value.
0V and other output terminals to high voltage _VHH .

[0024] Thus, in the semiconductor integrated circuit 10A～1nA, when any of the semiconductor integrated circuit 1iA is selected, the semiconductor integrated circuit 1iA only to the supply voltage V _CC is supplied, the power supply voltage to the remaining semiconductor integrated circuit V _CC is not supplied and becomes completely inactive. Therefore, power consumption can be reduced by the amount of the non-operating semiconductor integrated circuit.

[0025]

【The invention's effect】

As described above, according to the method and apparatus for testing a semiconductor integrated circuit according to the present invention, the power supply switches of the plurality of semiconductor integrated circuits can be sequentially switched at high speed by the switching control circuit, so that the test time can be reduced. This has the effect of contributing to a reduction in test cost.

[Brief description of the drawings]

1 to 3 relate to an embodiment of the present invention, FIG. 1 is a main part circuit diagram of a semiconductor integrated circuit, FIG. 2 is a main part circuit diagram of a DC test apparatus for a plurality of semiconductor integrated circuits, The figure is a circuit diagram for reducing power consumption when the semiconductor integrated circuit is a ROM. FIG. 4 is a main part circuit diagram of a conventional DC test apparatus. In the figure, 10 to 15, 10A to 1nA are semiconductor integrated circuits 20, 40 are DC test equipment 31, 33 is a PMOS transistor 32 is a power switch control circuit 34, 35, 36 is a CMOS inverter T1 to Tm is an external input terminal Tm + 1 to Tn is an external output terminal TC is an external power supply terminal TS is a ground terminal T2 is a chip select terminal A _{0 to} A ₃ are address lines

Claims (3)

(57) [Claims] A plurality of semiconductors comprising: a power switch connected between an external power terminal and an internal circuit; and a power switch control circuit for controlling on / off of the power switch according to a voltage applied to the external terminal. A semiconductor integrated circuit test apparatus for an integrated circuit, comprising: a switching control circuit that sequentially switches a voltage supplied to the external terminal, turns on only one of the plurality of power switches, and sequentially switches the power switches that are turned on. And selectively supplying a DC voltage to a semiconductor integrated circuit having the power switch turned on among the plurality of semiconductor integrated circuits, the common being connected to the external power supply terminals of the plurality of semiconductor integrated circuits. A DC test circuit for checking a current flowing to an external power supply terminal of the semiconductor integrated circuit. 2. The external terminal is an input terminal for the internal circuit. The power switch control circuit turns on the power switch when the external terminal is set to a voltage for normal operation, and causes the external terminal to operate normally. When the voltage is higher than the voltage of the power switch, the power switch is turned off, the switching control circuit turns on the power switch by setting the external terminal to a voltage for normal operation, 2. The semiconductor integrated circuit test apparatus according to claim 1, wherein the power switch is turned off by setting the voltage to a voltage higher than a normal operation voltage. 3. A plurality of semiconductors comprising: a power switch connected between an external power terminal and an internal circuit; and a power switch control circuit for controlling on / off of the power switch according to a voltage applied to the external terminal. A semiconductor integrated circuit test method for an integrated circuit, wherein a voltage supplied to the external terminal is sequentially switched, only one of the plurality of power switches is turned on, and the power switches that are turned on are sequentially switched. A DC test circuit commonly connected to the external power supply terminal of the semiconductor integrated circuit of the semiconductor integrated circuit selectively applies a DC voltage to the semiconductor integrated circuit having the power switch turned on among the plurality of semiconductor integrated circuits. Checking a current supplied and flowing to an external power supply terminal of the semiconductor integrated circuit.