GB2246651A - Data input circuit for a dual-port memory with block write mode - Google Patents

Data input circuit for a dual-port memory with block write mode Download PDF

Info

Publication number
GB2246651A
GB2246651A GB9017094A GB9017094A GB2246651A GB 2246651 A GB2246651 A GB 2246651A GB 9017094 A GB9017094 A GB 9017094A GB 9017094 A GB9017094 A GB 9017094A GB 2246651 A GB2246651 A GB 2246651A
Authority
GB
United Kingdom
Prior art keywords
data
latch pulse
data latch
data input
input circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9017094A
Other languages
English (en)
Other versions
GB9017094D0 (en
Inventor
Seong-Ouk Jeong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB9017094D0 publication Critical patent/GB9017094D0/en
Publication of GB2246651A publication Critical patent/GB2246651A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Dram (AREA)
  • Static Random-Access Memory (AREA)
GB9017094A 1990-08-03 1990-08-03 Data input circuit for a dual-port memory with block write mode Withdrawn GB2246651A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9009993A FR2665568A1 (fr) 1990-08-03 1990-08-03 Circuit d'entree de donnees pour dispositif de memorisation a double port d'acces.

Publications (2)

Publication Number Publication Date
GB9017094D0 GB9017094D0 (en) 1990-09-19
GB2246651A true GB2246651A (en) 1992-02-05

Family

ID=9399431

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9017094A Withdrawn GB2246651A (en) 1990-08-03 1990-08-03 Data input circuit for a dual-port memory with block write mode

Country Status (3)

Country Link
DE (1) DE4024724A1 (fr)
FR (1) FR2665568A1 (fr)
GB (1) GB2246651A (fr)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4541075A (en) * 1982-06-30 1985-09-10 International Business Machines Corporation Random access memory having a second input/output port
JPS61267148A (ja) * 1985-05-22 1986-11-26 Hitachi Ltd 記憶回路
JPS62287497A (ja) * 1986-06-06 1987-12-14 Fujitsu Ltd 半導体記憶装置
JPS63166093A (ja) * 1986-12-26 1988-07-09 Toshiba Corp 半導体メモリの制御回路

Also Published As

Publication number Publication date
GB9017094D0 (en) 1990-09-19
FR2665568A1 (fr) 1992-02-07
DE4024724A1 (de) 1992-02-13

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)